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Fri, 17 Apr 2026 08:27:13 -0700 (PDT) X-Received: by 2002:a17:90a:d0f:b0:361:45df:114 with SMTP id 98e67ed59e1d1-36145df0462mr906229a91.19.1776439632683; Fri, 17 Apr 2026 08:27:12 -0700 (PDT) Received: from [10.206.105.200] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-36140fc575bsm2478649a91.4.2026.04.17.08.27.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Apr 2026 08:27:12 -0700 (PDT) Message-ID: <987f1ac3-1725-11d6-d257-9bc7192b2fb4@oss.qualcomm.com> Date: Fri, 17 Apr 2026 20:57:03 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 From: Vishnu Reddy Subject: Re: [PATCH 05/11] media: iris: Enable Secure PAS support with IOMMU managed by Linux To: Konrad Dybcio , Bryan O'Donoghue , Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joerg Roedel , Will Deacon , Robin Murphy , Bjorn Andersson , Konrad Dybcio , Stefan Schmidt , Hans Verkuil Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Mukesh Ojha References: <20260414-glymur-v1-0-7d3d1cf57b16@oss.qualcomm.com> <20260414-glymur-v1-5-7d3d1cf57b16@oss.qualcomm.com> <809e2ad6-258c-49ac-9f3b-4ced32807203@oss.qualcomm.com> Content-Language: en-US In-Reply-To: <809e2ad6-258c-49ac-9f3b-4ced32807203@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=d6/FDxjE c=1 sm=1 tr=0 ts=69e25152 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=0AyAw_TJNaHdl9VPQ8YA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-GUID: NHYeXcQkLzMtUlP-H6-CRPZKcV7T_q01 X-Proofpoint-ORIG-GUID: NHYeXcQkLzMtUlP-H6-CRPZKcV7T_q01 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDE3MDE1NSBTYWx0ZWRfX4j7tq72D+sC6 p3HsZeuj2EyPT2DT5PGNGnt1gJ6rtJu/KGto5+ng7DQrjKqZ8+x0PIFfe0OHUuGoNpPWx6N6ez9 YnlXGAB8V94BL/2HEMTaBaIaNsVfof5sOb9gg/EjarKhcpLToxZKUvN1j9ameC86p79oXGAJMS1 FDWEdkDnREIUiODF38dHqduiOu7G9WVOFwfvcc6MLTPOjPqXqD49HvICvWWcSixJaJXwMJxzJPK 1Ory+qkiRD6r/jYol4CgHg4MzExKUAVpOeM/kA5ZAhpL4+rUlEsS1xBdRq963mm+kjXhm5MUXuS MzshblFmbiaX3HnRwPUqAIgcj12/LkJ2I1o4psESbVUtvcJ8lLt+x/6ayeu+cJvpezKPQraRSE6 R92Eq8P91iMbuxsXJ9zGD4kymiE6HEazk3DZ6TO9b4CrPm/J7Wy4YU+LsPmSBG25ihROOFZdJpY xxHM4GHNAt5sdiQykXw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-17_01,2026-04-17_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 suspectscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604170155 On 4/14/2026 7:39 PM, Konrad Dybcio wrote: > On 4/14/26 7:00 AM, Vishnu Reddy wrote: >> From: Mukesh Ojha >> >> Most Qualcomm platforms feature a proprietary hypervisor (such as Gunyah >> or QHEE), which typically handles IOMMU configuration. This includes >> mapping memory regions and device memory resources for remote processors >> by intercepting qcom_scm_pas_auth_and_reset() calls. These mappings are >> later removed during teardown. Additionally, SHM bridge setup is required >> to enable memory protection for both remoteproc metadata and its memory >> regions. >> >> When the hypervisor is absent, the operating system must perform these >> configurations instead. >> >> Support for handling IOMMU and SHM setup in the absence of a hypervisor >> is now in place. Extend the Iris driver to enable this functionality on >> platforms where IOMMU is managed by Linux (i.e., non-Gunyah, non-QHEE). >> >> Additionally, the Iris driver must map the firmware and its required >> resources to the firmware SID, which is now specified via iommu-map in >> the device tree. >> >> Co-developed-by: Vikash Garodia >> Signed-off-by: Vikash Garodia >> Signed-off-by: Mukesh Ojha >> Signed-off-by: Vishnu Reddy >> --- > [...] > >> static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name) >> { >> + struct device *dev = core->dev_fw ? core->dev_fw : core->dev; > Maybe: > > struct device *fw_dev = core->dev_fw ?: core->dev; > > and preserve *dev to be the main Iris device? That's better, ack. Thanks, Vishnu Reddy. > Konrad