[PATCH v2] arm64: dts: ti: k3-am642-evm-pcie0-ep: Add boot phase tag to "pcie0_ep"

Hrushikesh Salunke
2025-06-10T05:49:32Z

AM64X SoC has one instance of PCIe which is PCIe0. To support PCIe boot
on AM64X SoC, PCIe0 needs to be in endpoint mode and it needs to be
functional at all stages of PCIe boot process. Thus add the
"bootph-all" boot phase tag to "pcie0_ep" device tree node.

Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
---
This patch is based on commit
475c850a7fdd Add linux-next specific files for 20250606

Changes since v1
As per feedback from Nishanth, changed the position of "bootph-all"
tag, according to ordering rules for device tree properties.

v1 : https://lore.kernel.org/all/20250609115930.w2s6jzg7xii55dlu@speckled/

arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso b/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso
index 432751774853..a7e8d4ea98ac 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso
@@ -46,6 +46,7 @@ pcie0_ep: pcie-ep@f102000 {
max-functions = /bits/ 8 <1>;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
+ bootph-all;
ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
};
};
--
2.34.1