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Thu, 30 Jan 2025 09:56:25 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 9EE874002D; Thu, 30 Jan 2025 09:54:02 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id BEB2C27EEB1; Thu, 30 Jan 2025 09:51:29 +0100 (CET) Received: from [10.48.87.62] (10.48.87.62) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Thu, 30 Jan 2025 09:51:28 +0100 Message-ID: <98f9bdfa-5107-412a-8b9b-41f8135954fc@foss.st.com> Date: Thu, 30 Jan 2025 09:51:28 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/9] dt-bindings: spi: Add STM32 OSPI controller To: Conor Dooley CC: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Torgue , Philipp Zabel , Maxime Coquelin , Greg Kroah-Hartman , Arnd Bergmann , Catalin Marinas , Will Deacon , , , , , , References: <20250128081731.2284457-1-patrice.chotard@foss.st.com> <20250128081731.2284457-2-patrice.chotard@foss.st.com> <20250128-panama-manly-a753d91c297c@spud> <20250129-feminize-spotlight-2cee53f8b463@spud> Content-Language: en-US From: Patrice CHOTARD In-Reply-To: <20250129-feminize-spotlight-2cee53f8b463@spud> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-30_05,2025-01-29_01,2024-11-22_01 On 1/29/25 18:53, Conor Dooley wrote: > On Wed, Jan 29, 2025 at 06:40:23PM +0100, Patrice CHOTARD wrote: >> On 1/28/25 19:02, Conor Dooley wrote: >>> On Tue, Jan 28, 2025 at 09:17:23AM +0100, patrice.chotard@foss.st.com wrote: >>>> + memory-region: >>>> + maxItems: 1 >>> >>> Whatever about not having descriptions for clocks or reg when there's >>> only one, I think a memory region should be explained. >> >> ok i will add : >> >> description: | > > The | isn't needed here. ok > >> Memory region to be used for memory-map read access. > > I don't think that's a good explanation, sorry. Why's a memory-region > required for read access? The OCTOSPI interface support 3 functional modes: _ indirect _ automatic polling status _ memory-mapped 256MB are reserved in the CPU memory map for the 2 OCTOSPI instance. This area is used when OCTOSPI1 and/or OCTOSPI2 operate in memory-mapped mode. In this mode, read access are performed from the memory device using the direct mapping. Thanks Patrice > >>>> + >>>> + clocks: >>>> + maxItems: 1 >>>> + >>>> + interrupts: >>>> + maxItems: 1 >>>> + >>>> + resets: >>>> + items: >>>> + - description: phandle to OSPI block reset >>>> + - description: phandle to delay block reset >>>> + >>>> + dmas: >>>> + maxItems: 2 >>>> + >>>> + dma-names: >>>> + items: >>>> + - const: tx >>>> + - const: rx >>>> + >>>> + st,syscfg-dlyb: >>>> + description: phandle to syscon block >>>> + Use to set the OSPI delay block within syscon to >>>> + tune the phase of the RX sampling clock (or DQS) in order >>>> + to sample the data in their valid window and to >>>> + tune the phase of the TX launch clock in order to meet setup >>>> + and hold constraints of TX signals versus the memory clock. >>>> + $ref: /schemas/types.yaml#/definitions/phandle-array >>> >>> Why do you need a phandle here? I assume looking up by compatible ain't >>> possible because you have multiple controllers on the SoC? Also, I don't >> >> Yes, we got 2 OCTOSPI controller, each of them have a dedicated delay block >> syscfg register. > > :+1: > >>> think your copy-paste "phandle to" stuff here is accurate: >>> st,syscfg-dlyb = <&syscfg 0x1000>; >>> There's an offset here that you don't mention in your description. >> >> I will add it as following: >> >> st,syscfg-dlyb: >> description: >> Use to set the OSPI delay block within syscon to >> tune the phase of the RX sampling clock (or DQS) in order >> to sample the data in their valid window and to >> tune the phase of the TX launch clock in order to meet setup >> and hold constraints of TX signals versus the memory clock. >> $ref: /schemas/types.yaml#/definitions/phandle-array >> items: >> - description: phandle to syscfg >> - description: register offset within syscfg > > :+1: > >>>> + access-controllers: >>>> + description: phandle to the rifsc device to check access right >>>> + and in some cases, an additional phandle to the rcc device for >>>> + secure clock control >>> >>> This should be described using items rather than a free-form list. >> >> access-controllers: >> description: phandle to the rifsc device to check access right >> and in some cases, an additional phandle to the rcc device for >> secure clock control >> items: >> - description: phandle to bus controller or to clock controller >> - description: access controller specifier >> minItems: 1 >> maxItems: 2 > > These updates look fine to me.