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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3a4f471b16asm6642130a91.9.2026.10.01.17.45.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 01 Oct 2026 17:45:52 -0700 (PDT) Message-ID: <9987c7a0-efba-4f9d-a3fa-877cc9d189ed@gmail.com> Date: Fri, 2 Oct 2026 08:45:50 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/3] spi: ma35d1: Add Nuvoton MA35D1 SPI controller support To: sashiko-reviews@lists.linux.dev Cc: robh@kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org References: <20261001131818.110028-1-cwweng.linux@gmail.com> <20261001131818.110028-3-cwweng.linux@gmail.com> <20261001133705.7C5A71F000FF@smtp.kernel.org> Content-Language: en-US From: Chi-Wen Weng In-Reply-To: <20261001133705.7C5A71F000FF@smtp.kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit sashiko-bot@kernel.org 於 2026/10/1 下午 09:37 寫道: > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: > - [Medium] spi: ma35d1: probe fails on valid DT with num-cs > 2 when using GPIO CS > -- > > commit 297501e7117bfad68b786ba4098b2489480c1405 > Author: Chi-Wen Weng > > spi: ma35d1: Add Nuvoton MA35D1 SPI controller support > > This commit adds a new driver for the SPI controller found in the Nuvoton > MA35D1 SoC. The driver supports SPI host mode using polling-based PIO > transfers, standard SPI modes, and natively controls up to two chip selects. > >> diff --git a/drivers/spi/spi-ma35d1.c b/drivers/spi/spi-ma35d1.c >> new file mode 100644 >> index 0000000000000..7560cb7e0b099 >> --- /dev/null >> +++ b/drivers/spi/spi-ma35d1.c > [ ... ] >> +static int nuvoton_spi_probe(struct platform_device *pdev) >> +{ > [ ... ] >> + ret = device_property_read_u32(dev, "num-cs", &num_cs); >> + if (ret && ret != -EINVAL) >> + return dev_err_probe(dev, ret, "failed to read num-cs\n"); >> + >> + if (!num_cs || num_cs > NUVOTON_SPI_MAX_NATIVE_CS) >> + return dev_err_probe(dev, -EINVAL, "invalid num-cs %u\n", >> + num_cs); > > [Severity: Medium] > Will this check inadvertently reject valid device tree configurations that use > GPIO chip selects for additional devices? > > The SPI core correctly supports expanding the total number of chip selects > beyond the native hardware limit when using GPIO descriptors. Since this > driver sets ctlr->use_gpio_descriptors to true, a device tree could specify a > num-cs value greater than NUVOTON_SPI_MAX_NATIVE_CS (which is 2) in order to > attach a 3rd or 4th SPI target using GPIOs. > > Because nuvoton_spi_probe() checks the total num-cs read from the device > tree directly against NUVOTON_SPI_MAX_NATIVE_CS and returns -EINVAL, could > this artificially limit the bus to 2 devices overall and prevent GPIO chip > select expansion? > >> + >> + ctlr->num_chipselect = num_cs; >> + ctlr->max_native_cs = NUVOTON_SPI_MAX_NATIVE_CS; >> + ctlr->use_gpio_descriptors = true; > [ ... ] > Hi, Thanks for the review. I don't think this check prevents additional GPIO chip selects. For the MA35D1 binding, `num-cs` is limited to the two native hardware chip selects: num-cs: minimum: 1 maximum: 2 default: 2 Additional chip selects are described by entries in `cs-gpios`, rather than by increasing `num-cs` beyond two. Since the driver sets: ctlr->max_native_cs = NUVOTON_SPI_MAX_NATIVE_CS; ctlr->use_gpio_descriptors = true; the SPI core handles the GPIO chip-select expansion in `spi_get_gpio_descs()`. In particular, it updates `num_chipselect` using the number of `cs-gpios` entries: ctlr->num_chipselect = max_t(int, nb, ctlr->num_chipselect); For example, with two native chip selects and two additional GPIO chip selects, `num-cs` remains 2 while `cs-gpios` contains four entries. The SPI core then expands `ctlr->num_chipselect` to 4. `max_native_cs` only limits chip-select indices which do not have a GPIO descriptor, so the additional GPIO-backed chip selects are not rejected. Therefore a DT with `num-cs > 2` is not valid for this controller binding, while valid configurations using additional GPIO chip selects continue to work through the SPI core. Thanks, Chi-Wen