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Fri, 12 Aug 2022 00:35:46 -0700 (PDT) Received: from [192.168.1.39] ([83.146.140.105]) by smtp.gmail.com with ESMTPSA id p2-20020a05651211e200b0048af60faabcsm118423lfs.131.2022.08.12.00.35.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 12 Aug 2022 00:35:46 -0700 (PDT) Message-ID: <99b5bddb-4a09-a3ac-e01b-d0ae624ad2f8@linaro.org> Date: Fri, 12 Aug 2022 10:35:39 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.12.0 Subject: Re: [PATCH 2/4] dt-bindings: PCI: microchip,pcie-host: fix missing clocks properties Content-Language: en-US To: Conor Dooley , Daire McNamara , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Greentime Hu , Palmer Dabbelt , Albert Ou , Lorenzo Pieralisi , Conor Dooley Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org References: <20220811203306.179744-1-mail@conchuod.ie> <20220811203306.179744-3-mail@conchuod.ie> From: Krzysztof Kozlowski In-Reply-To: <20220811203306.179744-3-mail@conchuod.ie> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 11/08/2022 23:33, Conor Dooley wrote: > From: Conor Dooley > > Upgrading dt-schema to v2022.08 reveals unevaluatedProperties issues > that were not previously visible, such as the missing clocks and > clock-names properties for PolarFire SoC's PCI controller: > arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: pcie@2000000000: Unevaluated properties are not allowed ('clock-names', 'clocks', 'legacy-interrupt-controller', 'microchip,axi-m-atr0' were unexpected) > From schema: Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml > > The clocks are required to enable interfaces between the FPGA fabric > and the core complex, so add them to the binding. > > Fixes: 6ee6c89aac35 ("dt-bindings: PCI: microchip: Add Microchip PolarFire host binding") > Signed-off-by: Conor Dooley > --- > .../bindings/pci/microchip,pcie-host.yaml | 25 +++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml > index edb4f81253c8..2a2166f09e2c 100644 > --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml > +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml > @@ -25,6 +25,31 @@ properties: > - const: cfg > - const: apb > > + clocks: > + description: > + Fabric Interface Controllers, FICs, are the interface between the FPGA > + fabric and the core complex on PolarFire SoC. The FICs require two clocks, > + one from each side of the interface. The "FIC clocks" described by this > + property are on the core complex side & communication through a FIC is not > + possible unless it's corresponding clock is enabled. A clock must be > + enabled for each of the interfaces the root port is connected through. > + minItems: 1 > + items: > + - description: FIC0's clock > + - description: FIC1's clock > + - description: FIC2's clock > + - description: FIC3's clock > + > + clock-names: > + items: > + enum: > + - fic0 > + - fic1 > + - fic2 > + - fic3 > + minItems: 1 > + maxItems: 4 No need for maxItems. Best regards, Krzysztof