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charset=UTF-8 Content-Transfer-Encoding: 8bit Feedback-ID: rr0801122721eb2b2cfbde78b1a786bd58000076718b310158f27cfa3464eca44859bce125b648e8a25c5d35:zu08011227a06aac7a5cd58a25162aad5300002c0f1abb8414dc1dd3cbc0a960524f2538d0f8a740f0c120ae:rf0801122cea59dc67dd6f1b730040746700001b15077359642322a5d7c756be2477dd7a8e8d4849b3c6f97bd5d5e0df3f:ZohoMail X-ZohoMailClient: External On 2025/9/9 15:02, Vivian Wang wrote: > On 9/8/25 22:13, Xukai Wang wrote: >>>> [...] >>>> >>>> + >>>> +static int k230_clk_set_rate_mul_div(struct clk_hw *hw, unsigned long rate, >>>> + unsigned long parent_rate) >>>> +{ >>>> + struct k230_clk_rate *clk = hw_to_k230_clk_rate(hw); >>>> + struct k230_clk_rate_self *rate_self = &clk->clk; >>>> + u32 div, mul, div_reg, mul_reg; >>>> + >>>> + if (rate > parent_rate) >>>> + return -EINVAL; >>>> + >>>> + if (rate_self->read_only) >>>> + return 0; >>>> + >>>> + if (k230_clk_find_approximate_mul_div(rate_self->mul_min, rate_self->mul_max, >>>> + rate_self->div_min, rate_self->div_max, >>>> + rate, parent_rate, &div, &mul)) >>>> + return -EINVAL; >>>> + >>>> + guard(spinlock)(rate_self->lock); >>>> + >>>> + div_reg = readl(rate_self->reg + clk->div_reg_off); >>>> + div_reg |= ((div - 1) & rate_self->div_mask) << (rate_self->div_shift); >>>> + div_reg |= BIT(rate_self->write_enable_bit); >>>> + writel(div_reg, rate_self->reg + clk->div_reg_off); >>>> + >>>> + mul_reg = readl(rate_self->reg + clk->mul_reg_off); >>>> + mul_reg |= ((mul - 1) & rate_self->mul_mask) << (rate_self->mul_shift); >>>> + mul_reg |= BIT(rate_self->write_enable_bit); >>>> + writel(mul_reg, rate_self->reg + clk->mul_reg_off); >>>> + >>>> + return 0; >>>> +} >>> There are three variants of rate clocks, mul-only, div-only and mul-div >>> ones, which are similar to clk-multiplier, clk-divider, >>> clk-fractional-divider. >>> >>> The only difference is to setup new parameters for K230's rate clocks, >>> a register bit, described as k230_clk_rate_self.write_enable_bit, must >>> be set first. >> Actually, I think the differences are not limited to just the >> write_enable_bit. There are also distinct mul_min, mul_max, div_min, and >> div_max values, which are not typically just 1 and (1 << bit_width) as >> in standard clock divider or multiplier structures. > So the part I have been thinking about is, consider just checking the > {mul,div}_{min,max} values to determine which kind it is? As is this is > just redundant information, since you can infer whether there is a > configurable multiplier by checking if mul_{min,max} are equal. Same for > div_{min,max}. > > Vivian "dramforever" Wang Thanks for pointing it out. I see your idea, but I don’t think it’s necessary to determine the clock type from {mul,div}_{min,max} dynamically since we already statically specify each mul, div, and mul-div clock by different macros.