[RESEND PATCH 1/2] dt-bindings: soc: altera: Move altera.yaml from arm to soc

[RESEND PATCH 1/2] dt-bindings: soc: altera: Move altera.yaml from arm to soc

[Dinh Nguyen]

All Altera boards can hosts soft core CPUs like NIOS V or a RISC V, so
it makes sense to move from the arm to soc folder. This change is similar
to what was done for xilinx.yaml by commit 6f3ecaea6324 ("dt-bindings:
soc: xilinx: Move xilinx.yaml from arm to soc").

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
 .../devicetree/bindings/{arm => soc/altera}/altera.yaml         | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
 rename Documentation/devicetree/bindings/{arm => soc/altera}/altera.yaml (97%)

diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/soc/altera/altera.yaml
similarity index 97%
rename from Documentation/devicetree/bindings/arm/altera.yaml
rename to Documentation/devicetree/bindings/soc/altera/altera.yaml
index db61537b7115..7c6827837b95 100644
--- a/Documentation/devicetree/bindings/arm/altera.yaml
+++ b/Documentation/devicetree/bindings/soc/altera/altera.yaml
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/arm/altera.yaml#
+$id: http://devicetree.org/schemas/soc/altera/altera.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: Altera's SoCFPGA platform
-- 
2.42.0.411.g813d9a9188

[RESEND PATCH 2/2] dt-bindings: soc: altera: combine Intel's SoCFPGA into altera.yaml

[Dinh Nguyen]

For all SoCFPGA platforms, whether it has the "intel" or "altr" vendor
prefix are referring to the same business unit that is responsible for
the platform. Thus, it would make sense to have the device bindings
documentation in the same location. Move the Intel AgileX board binding
documentations into the same file that contains the Altera ones.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
 .../bindings/arm/intel,socfpga.yaml           | 40 -------------------
 .../bindings/soc/altera/altera.yaml           | 28 ++++++++++++-
 2 files changed, 27 insertions(+), 41 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/intel,socfpga.yaml

diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
deleted file mode 100644
index c918837bd41c..000000000000
--- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
+++ /dev/null
@@ -1,40 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/arm/intel,socfpga.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Intel SoCFPGA platform
-
-maintainers:
-  - Dinh Nguyen <dinguyen@kernel.org>
-
-properties:
-  $nodename:
-    const: "/"
-  compatible:
-    oneOf:
-      - description: AgileX boards
-        items:
-          - enum:
-              - intel,n5x-socdk
-              - intel,socfpga-agilex-n6000
-              - intel,socfpga-agilex-socdk
-          - const: intel,socfpga-agilex
-      - description: Agilex3 boards
-        items:
-          - enum:
-              - intel,socfpga-agilex3-socdk
-          - const: intel,socfpga-agilex3
-          - const: intel,socfpga-agilex5
-      - description: Agilex5 boards
-        items:
-          - enum:
-              - intel,socfpga-agilex5-socdk
-              - intel,socfpga-agilex5-socdk-013b
-              - intel,socfpga-agilex5-socdk-nand
-          - const: intel,socfpga-agilex5
-
-additionalProperties: true
-
-...
diff --git a/Documentation/devicetree/bindings/soc/altera/altera.yaml b/Documentation/devicetree/bindings/soc/altera/altera.yaml
index 7c6827837b95..a853ba3daf80 100644
--- a/Documentation/devicetree/bindings/soc/altera/altera.yaml
+++ b/Documentation/devicetree/bindings/soc/altera/altera.yaml
@@ -4,7 +4,10 @@
 $id: http://devicetree.org/schemas/soc/altera/altera.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Altera's SoCFPGA platform
+title: Intel/Altera's SoCFPGA platform
+
+description:
+  Intel/Altera boards with ARM 32/64 bit cores
 
 maintainers:
   - Dinh Nguyen <dinguyen@kernel.org>
@@ -86,6 +89,29 @@ properties:
           - const: altr,socfpga-vt
           - const: altr,socfpga
 
+      - description: AgileX boards
+        items:
+          - enum:
+              - intel,n5x-socdk
+              - intel,socfpga-agilex-n6000
+              - intel,socfpga-agilex-socdk
+          - const: intel,socfpga-agilex
+
+      - description: Agilex3 boards
+        items:
+          - enum:
+              - intel,socfpga-agilex3-socdk
+          - const: intel,socfpga-agilex3
+          - const: intel,socfpga-agilex5
+
+      - description: Agilex5 boards
+        items:
+          - enum:
+              - intel,socfpga-agilex5-socdk
+              - intel,socfpga-agilex5-socdk-013b
+              - intel,socfpga-agilex5-socdk-nand
+          - const: intel,socfpga-agilex5
+
 additionalProperties: true
 
 ...
-- 
2.42.0.411.g813d9a9188

Re: [RESEND PATCH 1/2] dt-bindings: soc: altera: Move altera.yaml from arm to soc

[Krzysztof Kozlowski]

On Tue, Nov 25, 2025 at 07:40:02AM -0600, Dinh Nguyen wrote:
> All Altera boards can hosts soft core CPUs like NIOS V or a RISC V, so

Please send it with the user of this change, so with DTS for RISC-V or
NIOS-V.

This alone is not really correct, if all compatibles here are for ARM
and nothing in commit msg said that any compatible is not for ARM...
unless you claim that each of these SoCs are multi-arch?

Best regards,
Krzysztof

Re: [RESEND PATCH 2/2] dt-bindings: soc: altera: combine Intel's SoCFPGA into altera.yaml

[Krzysztof Kozlowski]

On Tue, Nov 25, 2025 at 07:40:03AM -0600, Dinh Nguyen wrote:
> For all SoCFPGA platforms, whether it has the "intel" or "altr" vendor
> prefix are referring to the same business unit that is responsible for
> the platform. Thus, it would make sense to have the device bindings
> documentation in the same location. Move the Intel AgileX board binding
> documentations into the same file that contains the Altera ones.

I had impression that "intel" is the new, thus preferred vendor prefix
and actual owner, so please describe here why this is the other way.

> 
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

Best regards,
Krzysztof

Re: [RESEND PATCH 2/2] dt-bindings: soc: altera: combine Intel's SoCFPGA into altera.yaml

[Dinh Nguyen]

On 11/26/25 03:49, Krzysztof Kozlowski wrote:
> On Tue, Nov 25, 2025 at 07:40:03AM -0600, Dinh Nguyen wrote:
>> For all SoCFPGA platforms, whether it has the "intel" or "altr" vendor
>> prefix are referring to the same business unit that is responsible for
>> the platform. Thus, it would make sense to have the device bindings
>> documentation in the same location. Move the Intel AgileX board binding
>> documentations into the same file that contains the Altera ones.
> 
> I had impression that "intel" is the new, thus preferred vendor prefix
> and actual owner, so please describe here why this is the other way.
> 

Altera has just spun off to be a separate business entity from Intel. 
Yes, while Intel is still a minority owner, Altera is technically on 
it's own. Moving forward, "altr" would be the preferred vendor prefix 
for SoCFPGA parts.

Dinh

Re: [RESEND PATCH 1/2] dt-bindings: soc: altera: Move altera.yaml from arm to soc

[Dinh Nguyen]

On 11/26/25 03:46, Krzysztof Kozlowski wrote:
> On Tue, Nov 25, 2025 at 07:40:02AM -0600, Dinh Nguyen wrote:
>> All Altera boards can hosts soft core CPUs like NIOS V or a RISC V, so
> 
> Please send it with the user of this change, so with DTS for RISC-V or
> NIOS-V.
> 
> This alone is not really correct, if all compatibles here are for ARM
> and nothing in commit msg said that any compatible is not for ARM...
> unless you claim that each of these SoCs are multi-arch?
> 

The SoCFPGA devices can house both the hardened ARM cluster running 
simultaneously with a number of soft Nios V cores in the FPGA fabric. 
They may be running independently or working together through shared 
memory or shared peripheral IO. I think that would be a qualify as a 
multi-arch device.

 From what we've seen of multi-arch use cases, there are separate DTS 
files for the soft-core CPU unit. Can you elaborate by what DTS you'd 
like to see to accomodate this change?

Thanks,
Dinh

Re: [RESEND PATCH 1/2] dt-bindings: soc: altera: Move altera.yaml from arm to soc

[Krzysztof Kozlowski]

On 02/12/2025 22:04, Dinh Nguyen wrote:
> 
> 
> On 11/26/25 03:46, Krzysztof Kozlowski wrote:
>> On Tue, Nov 25, 2025 at 07:40:02AM -0600, Dinh Nguyen wrote:
>>> All Altera boards can hosts soft core CPUs like NIOS V or a RISC V, so
>>
>> Please send it with the user of this change, so with DTS for RISC-V or
>> NIOS-V.
>>
>> This alone is not really correct, if all compatibles here are for ARM
>> and nothing in commit msg said that any compatible is not for ARM...
>> unless you claim that each of these SoCs are multi-arch?
>>
> 
> The SoCFPGA devices can house both the hardened ARM cluster running 

But "can" does not mean "does". None of the boards here do host. If they
do, it must be clearly expressed that you documented RISC-V under ARM.

> simultaneously with a number of soft Nios V cores in the FPGA fabric. 
> They may be running independently or working together through shared 
> memory or shared peripheral IO. I think that would be a qualify as a 
> multi-arch device.

Again, we speak ONLY about these few, very specific boards. Not SoCs.

> 
>  From what we've seen of multi-arch use cases, there are separate DTS 
> files for the soft-core CPU unit. Can you elaborate by what DTS you'd 
> like to see to accomodate this change?

We do not discuss DTS at all here.

Best regards,
Krzysztof