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Tue, 17 Mar 2026 22:53:11 -0700 (PDT) Message-ID: <9a9e13a5-411a-40bc-b52f-4345e7f6b92e@gmail.com> Date: Wed, 18 Mar 2026 11:23:30 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: tessolveupstream@gmail.com Subject: Re: [PATCH v2 2/2] drm: bridge: ti-sn65dsi83: Add support for dual-link LVDS video mode To: Luca Ceresoli , andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org Cc: Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, marex@denx.de, valentin@compulab.co.il, philippe.schenker@toradex.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20260312043743.261475-1-tessolveupstream@gmail.com> <20260312043743.261475-3-tessolveupstream@gmail.com> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 12-03-2026 21:17, Luca Ceresoli wrote: > Hello Sudarshan, > > On Thu Mar 12, 2026 at 5:37 AM CET, Sudarshan Shetty wrote: >> Some LVDS panels operating in dual-link mode require adjusted >> horizontal timing parameters when programmed into the SN65DSI84 >> bridge. According to TI documentation, horizontal timing values >> must be divided by two when operating in dual-link mode. Without >> this adjustment, the panel may fail to display or produce corrupted >> output. >> >> Add support for an optional DT property "ti,dual-link-video-mode" >> to enable configuration required for dual-link LVDS operation. >> These settings ensure correct LVDS output for panels that require >> this mode of operation. >> >> Signed-off-by: Sudarshan Shetty >> --- >> drivers/gpu/drm/bridge/ti-sn65dsi83.c | 52 ++++++++++++++++++++++++--- >> 1 file changed, 48 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge/ti-sn65dsi83.c >> index f6736b4457bb..9b7d35487bd8 100644 >> --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c >> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c >> @@ -164,6 +164,7 @@ struct sn65dsi83 { >> int irq; >> struct delayed_work monitor_work; >> struct work_struct reset_work; >> + bool dual_link_video_mode; > > As said in the reply to patch 1, there is already 'bool lvds_dual_link' > carrying the same info. > okay. >> static const struct regmap_range sn65dsi83_readable_ranges[] = { >> @@ -667,8 +668,43 @@ static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge, >> mode->hsync_start - mode->hdisplay); >> regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH, >> mode->vsync_start - mode->vdisplay); >> - regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00); >> >> + /* >> + * In dual-link LVDS mode, the SN65DSI84 requires the horizontal >> + * timing parameters to be adjusted before being programmed into >> + * the device. According to TI documentation, the horizontal timing >> + * values must be divided by two when operating in dual-link mode. >> + * Without this adjustment, the connected panel may fail to light up >> + * or display corrupted output. >> + * >> + * TI also provides recommended register settings for this mode, >> + * which were derived using the TI DSI-Tuner tool. When the optional >> + * DT property "ti,dual-link-video-mode" is present, apply these >> + * configuration settings to ensure correct dual-link LVDS operation. >> + */ >> + if (ctx->dual_link_video_mode) { >> + regmap_write(ctx->regmap, REG_RC_LVDS_PLL, 0x05); >> + regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); >> + regmap_write(ctx->regmap, REG_DSI_CLK, 0x53); >> + regmap_write(ctx->regmap, REG_LVDS_FMT, 0x6f); >> + regmap_write(ctx->regmap, REG_LVDS_VCOM, 0x00); >> + regmap_write(ctx->regmap, >> + REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 0x00); >> + regmap_write(ctx->regmap, >> + REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH, 0x00); >> + regmap_write(ctx->regmap, >> + REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 0x10); >> + regmap_write(ctx->regmap, >> + REG_VID_CHA_HORIZONTAL_BACK_PORCH, 0x28); >> + regmap_write(ctx->regmap, >> + REG_VID_CHA_VERTICAL_BACK_PORCH, 0x00); >> + regmap_write(ctx->regmap, >> + REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 0x00); >> + regmap_write(ctx->regmap, >> + REG_VID_CHA_VERTICAL_FRONT_PORCH, 0x00); >> + } > > I guess these hard-coded values are sepcific to your panel. They must > instead be computed based on the timings in order to work for every panel. > The hard-coded values were initially derived from the TI DSI Tuner output during our bring-up testing. TI had also mentioned that when PATGEN is enabled with dual-LVDS output on the SN65DSI84, the horizontal timings must be divided by 2. They also noted that the current driver does not appear to divide the horizontal timings when PATGEN is enabled in dual-LVDS mode. Based on that suggestion, we had tried adjusting the horizontal timing registers accordingly to match the tuner output. Could you please advise how these register values are expected to be derived from the mode timings so that they work correctly for different panels? >> + >> + regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00); >> /* Enable PLL */ >> regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN); >> usleep_range(3000, 4000); >> @@ -965,9 +1001,15 @@ static int sn65dsi83_host_attach(struct sn65dsi83 *ctx) >> >> dsi->lanes = dsi_lanes; >> dsi->format = MIPI_DSI_FMT_RGB888; >> - dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | >> - MIPI_DSI_MODE_VIDEO_NO_HFP | MIPI_DSI_MODE_VIDEO_NO_HBP | >> - MIPI_DSI_MODE_VIDEO_NO_HSA | MIPI_DSI_MODE_NO_EOT_PACKET; >> + if (ctx->dual_link_video_mode) >> + dsi->mode_flags = MIPI_DSI_MODE_VIDEO; >> + else >> + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | >> + MIPI_DSI_MODE_VIDEO_BURST | >> + MIPI_DSI_MODE_VIDEO_NO_HFP | >> + MIPI_DSI_MODE_VIDEO_NO_HBP | >> + MIPI_DSI_MODE_VIDEO_NO_HSA | >> + MIPI_DSI_MODE_NO_EOT_PACKET; > > There is no explanation about this, can you elaborate on why? > > I'm working on bringing up a dual-LVDS panel on a board with the SN65DSI84, > and the removing MIPI_DSI_MODE_VIDEO_BURST seems to help, but I still have > no idea why. Should you have any info, maybe from TI, it would be very > interesting. > During our earlier bring-up, TI mentioned that one possible reason for the DSI REFCLK not behaving as expected could be that the DSI output is configured in burst mode instead of non-burst mode. In burst mode the DSI clock may not be continuous, whereas non-burst mode provides a more predictable DSI clock. > Luca > > -- > Luca Ceresoli, Bootlin > Embedded Linux and Kernel engineering > https://bootlin.com