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[78.88.45.141]) by smtp.gmail.com with ESMTPSA id n19-20020a170906119300b00a4660b63502sm360863eja.12.2024.03.22.17.33.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 22 Mar 2024 17:33:20 -0700 (PDT) Message-ID: <9ac4117c-755e-4e49-b3a2-661e7195a7ed@linaro.org> Date: Sat, 23 Mar 2024 01:33:17 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V2 RESEND 6/6] arm64: dts: qcom: sm8650: Add video and camera clock controllers Content-Language: en-US To: Vladimir Zapolskiy , Jagadeesh Kona , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das , Satya Priya Kakitapalli , Ajit Pandey , Imran Shaik References: <20240321092529.13362-1-quic_jkona@quicinc.com> <20240321092529.13362-7-quic_jkona@quicinc.com> <0a7da687-18fb-437f-b33a-e4a1de20177e@linaro.org> From: Konrad Dybcio Autocrypt: addr=konrad.dybcio@linaro.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 21.03.2024 14:07, Vladimir Zapolskiy wrote: > Hello Jagadeesh, > > On 3/21/24 11:25, Jagadeesh Kona wrote: >> Add device nodes for video and camera clock controllers on Qualcomm >> SM8650 platform. >> >> Signed-off-by: Jagadeesh Kona >> --- >>   arch/arm64/boot/dts/qcom/sm8650.dtsi | 28 ++++++++++++++++++++++++++++ >>   1 file changed, 28 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi >> index 32c0a7b9aded..d862aa6be824 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi >> @@ -4,6 +4,8 @@ >>    */ >>     #include >> +#include >> +#include >>   #include >>   #include >>   #include >> @@ -3110,6 +3112,32 @@ opp-202000000 { >>               }; >>           }; >>   +        videocc: clock-controller@aaf0000 { >> +            compatible = "qcom,sm8650-videocc"; >> +            reg = <0 0x0aaf0000 0 0x10000>; >> +            clocks = <&bi_tcxo_div2>, >> +                 <&gcc GCC_VIDEO_AHB_CLK>; >> +            power-domains = <&rpmhpd RPMHPD_MMCX>; >> +            required-opps = <&rpmhpd_opp_low_svs>; > > Please add default status = "disabled"; > >> +            #clock-cells = <1>; >> +            #reset-cells = <1>; >> +            #power-domain-cells = <1>; >> +        }; >> + >> +        camcc: clock-controller@ade0000 { >> +            compatible = "qcom,sm8650-camcc"; >> +            reg = <0 0x0ade0000 0 0x20000>; >> +            clocks = <&gcc GCC_CAMERA_AHB_CLK>, >> +                 <&bi_tcxo_div2>, >> +                 <&bi_tcxo_ao_div2>, >> +                 <&sleep_clk>; >> +            power-domains = <&rpmhpd RPMHPD_MMCX>; >> +            required-opps = <&rpmhpd_opp_low_svs>; > > Please add default status = "disabled"; > >> +            #clock-cells = <1>; >> +            #reset-cells = <1>; >> +            #power-domain-cells = <1>; >> +        }; >> + >>           mdss: display-subsystem@ae00000 { >>               compatible = "qcom,sm8650-mdss"; >>               reg = <0 0x0ae00000 0 0x1000>; > > After disabling the clock controllers Clock controllers should never be disabled period, that defeats the entire point of having unused clk/pd cleanup. The only reason for them to be disabled is for cases where platform crashes on access due to stinky "security" settings (like with audio clocks), or when people are too lazy to upstream panel drivers and end up partially upstreaming display-related changes and continue using the bootloader-initialized framebuffer. This takes away from the very little determinism we have. Konrad