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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id z14-20020a056512308e00b0050e7a098a75sm2351099lfd.196.2024.01.23.10.17.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 23 Jan 2024 10:17:11 -0800 (PST) Message-ID: <9af6d68f-ccc0-4d2b-ab59-77864a628bb4@linaro.org> Date: Tue, 23 Jan 2024 19:17:10 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 06/11] arm64: dts: qcom: x1e80100: Add USB nodes Content-Language: en-US To: Abel Vesa , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Rajendra Nayak Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20240123-x1e80100-dts-missing-nodes-v4-0-072dc2f5c153@linaro.org> <20240123-x1e80100-dts-missing-nodes-v4-6-072dc2f5c153@linaro.org> From: Konrad Dybcio In-Reply-To: <20240123-x1e80100-dts-missing-nodes-v4-6-072dc2f5c153@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 1/23/24 12:01, Abel Vesa wrote: > Add nodes for all USB controllers and their PHYs for X1E80100 platform. > > Co-developed-by: Sibi Sankar > Signed-off-by: Sibi Sankar > Co-developed-by: Rajendra Nayak > Signed-off-by: Rajendra Nayak > Signed-off-by: Abel Vesa > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 435 ++++++++++++++++++++++++++++++++- > 1 file changed, 432 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index 2b6c55a486b2..593ead89706c 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -5,11 +5,13 @@ > > #include > #include > +#include > #include > #include > #include > #include > #include > +#include > #include > #include > #include > @@ -734,9 +736,9 @@ gcc: clock-controller@100000 { > <0>, > <0>, > <0>, > - <0>, > - <0>, > - <0>; > + <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, > + <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, > + <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; > > power-domains = <&rpmhpd RPMHPD_CX>; > #clock-cells = <1>; > @@ -2492,6 +2494,126 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, > }; > }; > > + usb_1_ss0_hsphy: phy@fd3000 { > + compatible = "qcom,x1e80100-snps-eusb2-phy", > + "qcom,sm8550-snps-eusb2-phy"; > + reg = <0 0x00fd3000 0 0x154>; > + #phy-cells = <0>; > + > + clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; > + clock-names = "ref"; You use this exact same clock for all HS PHYs. Are you sure? > + > + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; > + > + status = "disabled"; > + }; > + > + usb_1_ss0_qmpphy: phy@fd5000 { > + compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; > + reg = <0 0x00fd5000 0 0x4000>; > + > + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, > + <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, > + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; > + clock-names = "aux", > + "ref", > + "com_aux", > + "usb3_pipe"; > + > + power-domains = <&gcc GCC_USB_0_PHY_GDSC>; This is likely RPMHPD_MX(A/C) [...] > + usb_1_ss2_dwc3: usb@a000000 { > + compatible = "snps,dwc3"; > + reg = <0 0x0a000000 0 0xcd00>; > + interrupts = ; > + iommus = <&apps_smmu 0x14a0 0x0>; > + snps,dis_u2_susphy_quirk; > + snps,dis_enblslpm_quirk; > + snps,usb3_lpm_capable; > + phys = <&usb_1_ss2_hsphy>, > + <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>; > + phy-names = "usb2-phy", > + "usb3-phy"; Should this be marked dma-coherent? Konrad