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Thu, 25 Apr 2024 02:21:28 -0700 (PDT) Received: from [192.168.1.20] ([178.197.223.16]) by smtp.gmail.com with ESMTPSA id i21-20020a170906a29500b00a526a992d82sm9355428ejz.4.2024.04.25.02.21.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 Apr 2024 02:21:28 -0700 (PDT) Message-ID: <9b24ffdf-1247-4164-9841-6063106d76ea@linaro.org> Date: Thu, 25 Apr 2024 11:21:25 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 4/5] arm64: Add initial support for Blaize BLZP1600 CB2 To: Niko Pasaloukos , "robh@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "conor+dt@kernel.org" , "catalin.marinas@arm.com" , "will@kernel.org" , "arnd@arndb.de" , "olof@lixom.net" , Neil Jones , Matt Redfearn , James Cowgill , "heiko.stuebner@cherry.de" , "shawnguo@kernel.org" , "macromorgan@hotmail.com" , "sre@kernel.org" , "hvilleneuve@dimonoff.com" , "andre.przywara@arm.com" , "rafal@milecki.pl" , "linus.walleij@linaro.org" , "andersson@kernel.org" , "konrad.dybcio@linaro.org" , "geert+renesas@glider.be" , "neil.armstrong@linaro.org" , "m.szyprowski@samsung.com" , "nfraprado@collabora.com" , "u-kumar1@ti.com" Cc: "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" References: <20240425091403.17483-1-nikolaos.pasaloukos@blaize.com> <20240425091403.17483-5-nikolaos.pasaloukos@blaize.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzysztof.kozlowski@linaro.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 25/04/2024 11:15, Niko Pasaloukos wrote: > Adds support for the Blaize CB2 development board based on > BLZP1600 SoC. This consists of a Carrier-Board-2 and a SoM. Subject: missing dts prefix. ... > + > +/ { > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <1>; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + enable-method = "psci"; > + reg = <0x0 0x0>; > + next-level-cache = <&l2>; > + }; > + > + cpu1: cpu@1 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + enable-method = "psci"; > + reg = <0x0 0x1>; > + next-level-cache = <&l2>; > + }; > + > + l2: l2-cache0 { > + compatible = "cache"; > + cache-level = <2>; > + cache-unified; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = /* Physical Secure PPI */ > + + IRQ_TYPE_LEVEL_LOW)>, > + /* Physical Non-Secure PPI */ > + + IRQ_TYPE_LEVEL_LOW)>, > + /* Hypervisor PPI */ > + + IRQ_TYPE_LEVEL_LOW)>, > + /* Virtual PPI */ > + + IRQ_TYPE_LEVEL_LOW)>; > + }; > + > + psci { > + compatible = "arm,psci-1.0", "arm,psci-0.2"; > + method = "smc"; > + }; > + > + pmu { Nodes in top-level look randomly ordered. Any reason why not using DTS coding style in this regard? > + compatible = "arm,cortex-a53-pmu"; > + interrupts = , > + ; > + interrupt-affinity = <&cpu0>, <&cpu1>; > + }; > + > + sram@0 { > + /* > + * On BLZP1600 there is no general purpose (non-secure) SRAM. > + * A small DDR memory space has been reserved for general use. > + */ > + compatible = "mmio-sram"; > + reg = <0x0 0x00000000 0x00001000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x0 0x00000000 0x1000>; ranges follow reg > + > + /* SCMI reserved buffer space on DDR space */ > + scmi0_shm: scmi-sram@800 { > + compatible = "arm,scmi-shmem"; > + reg = <0x800 0x80>; > + }; > + }; > + > + firmware { > + scmi { > + compatible = "arm,scmi-smc"; > + arm,smc-id = <0x82002000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + shmem = <&scmi0_shm>; > + > + scmi_clk: protocol@14 { > + reg = <0x14>; > + #clock-cells = <1>; > + }; > + > + scmi_rst: protocol@16 { > + reg = <0x16>; > + #reset-cells = <1>; > + }; > + }; > + }; > + > + soc { This does not cause dtbs_check W=1 warnings? Surprising a bit... This should cause big fat warning, so I have doubts patchset was tested. Best regards, Krzysztof