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[83.9.29.181]) by smtp.gmail.com with ESMTPSA id x22-20020ac25dd6000000b004fbab1f023csm50300lfq.138.2023.07.17.12.18.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Jul 2023 12:18:25 -0700 (PDT) Message-ID: <9b28a17a-fe9c-3ff0-fa1d-320e75e174d0@linaro.org> Date: Mon, 17 Jul 2023 21:18:21 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH 15/15] arm64: dts: qcom: sm6115: Add VDD_CX to GPU_CCC Content-Language: en-US To: Stephan Gerhold Cc: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> <20230717-topic-branch_aon_cleanup-v1-15-27784d27a4f4@linaro.org> <8c5dc146-c305-bef9-0d97-76a91345ed1a@linaro.org> From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 17.07.2023 19:23, Stephan Gerhold wrote: > On Mon, Jul 17, 2023 at 07:11:33PM +0200, Konrad Dybcio wrote: >> On 17.07.2023 18:56, Stephan Gerhold wrote: >>> On Mon, Jul 17, 2023 at 06:50:18PM +0200, Konrad Dybcio wrote: >>>> On 17.07.2023 18:28, Stephan Gerhold wrote: >>>>> On Mon, Jul 17, 2023 at 05:19:22PM +0200, Konrad Dybcio wrote: >>>>>> The GPU_CC block is powered by VDD_CX. Describe that. >>>>>> >>>>>> Signed-off-by: Konrad Dybcio >>>>>> --- >>>>>> arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 ++ >>>>>> 1 file changed, 2 insertions(+) >>>>>> >>>>>> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi >>>>>> index 29b5b388cd94..bfaaa1801a4d 100644 >>>>>> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi >>>>>> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi >>>>>> @@ -1430,6 +1430,8 @@ gpucc: clock-controller@5990000 { >>>>>> clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, >>>>>> <&gcc GCC_GPU_GPLL0_CLK_SRC>, >>>>>> <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; >>>>>> + power-domains = <&rpmpd SM6115_VDDCX>; >>>>>> + required-opps = <&rpmpd_opp_low_svs>; >>>>> >>>>> Where is this required-opp coming from? The clocks in gpucc seem to have >>>>> different voltage requirements depending on the rates, but we usually >>>>> handle that in the OPP tables of the consumer. >>>> The only lower levels defined for this SoC are VDD_MIN and VDD_RET, >>>> but quite obviously the GPU won't work then >>>> >>> >>> The levels needed for the GPU clocks to run should be in the GPU OPP >>> table though, just like e.g. sdhc2_opp_table for the SDCC clocks. >>> >>> I still don't really understand why this is specified here. :) >> The GPU_CC block needs this rail to be at a certain power level for >> register access. This describes that requirement. >> > > Can you show where this is defined downstream? On a quick look I didn't > see something like that anywhere. Or is this from some secret > documentation? As far as downstream goes, you can notice that no branch's or RCG's vdd tables ever define a level lower than the one I mentioned. Konrad