[PATCH v3 0/4] Add support for AST2700 clk driver

[PATCH v3 0/4] Add support for AST2700 clk driver

[Ryan Chen]

This patch series is add clk driver for AST2700.

AST2700 is the 8th generation of Integrated Remote Management Processor
introduced by ASPEED Technology Inc. Which is Board Management controller
(BMC) SoC family. AST2700 have two SoC connected, one is SoC0, another
is SoC1, it has it's own scu, this driver inlcude SCU0 and SCU1 driver.

v3:
-yaml: v2 missing send yaml patch, v3 add.
-yaml: drop 64bits address example.
-yaml: add discription about soc0 and soc1
-dt-bindings: remove (), *_NUMS, reserved.
-dt-bindings: remove dulipated define number.
-dt-bindings: merge clk and reset to be one patch.
-reset-aspeed: add auxiliary device for reset driver.
-clk-ast2700: modify reset to be auxiliary add.
-clk-ast2700: modify to be platform driver.
-clk-ast2700: modify each clk to const clk array.

v2:
-yaml: drop 64bits address example.
-yaml: add discription about soc0 and soc1
-dt-bindings: remove (), *_NUMS, reserved.
-dt-bindings: remove dulipated define number
-clk-ast2700: drop WARN_ON, weird comment.

Ryan Chen (4):
  dt-bindings: mfd: aspeed: support for AST2700
  dt-bindings: Add AST2700 bindings
  reset: aspeed: register AST2700 reset auxiliary bus device
  clk: aspeed: add AST2700 clock driver.

 .../bindings/mfd/aspeed,ast2x00-scu.yaml      |   13 +-
 drivers/clk/Kconfig                           |    8 +
 drivers/clk/Makefile                          |    1 +
 drivers/clk/clk-ast2700.c                     | 1548 +++++++++++++++++
 drivers/reset/Kconfig                         |    6 +
 drivers/reset/Makefile                        |    1 +
 drivers/reset/reset-aspeed.c                  |  259 +++
 .../dt-bindings/clock/aspeed,ast2700-clk.h    |  163 ++
 .../dt-bindings/reset/aspeed,ast2700-reset.h  |  124 ++
 9 files changed, 2121 insertions(+), 2 deletions(-)
 create mode 100644 drivers/clk/clk-ast2700.c
 create mode 100644 drivers/reset/reset-aspeed.c
 create mode 100644 include/dt-bindings/clock/aspeed,ast2700-clk.h
 create mode 100644 include/dt-bindings/reset/aspeed,ast2700-reset.h

-- 
2.34.1

[PATCH v3 1/4] dt-bindings: mfd: aspeed: support for AST2700

[Ryan Chen]

Add compatible support for AST2700 clk, reset, pinctrl, silicon-id for AST2700 scu.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
 .../devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
index 86ee69c0f45b..127a357051cd 100644
--- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
+++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
@@ -9,6 +9,8 @@ title: Aspeed System Control Unit
 description:
   The Aspeed System Control Unit manages the global behaviour of the SoC,
   configuring elements such as clocks, pinmux, and reset.
+  In AST2700 SOC which has two soc connection, each soc have its own scu
+  register control, ast2700-scu0 for soc0, ast2700-scu1 for soc1.
 
 maintainers:
   - Joel Stanley <joel@jms.id.au>
@@ -21,6 +23,8 @@ properties:
           - aspeed,ast2400-scu
           - aspeed,ast2500-scu
           - aspeed,ast2600-scu
+          - aspeed,ast2700-scu0
+          - aspeed,ast2700-scu1
       - const: syscon
       - const: simple-mfd
 
@@ -30,10 +34,12 @@ properties:
   ranges: true
 
   '#address-cells':
-    const: 1
+    minimum: 1
+    maximum: 2
 
   '#size-cells':
-    const: 1
+    minimum: 1
+    maximum: 2
 
   '#clock-cells':
     const: 1
@@ -56,6 +62,8 @@ patternProperties:
             - aspeed,ast2400-pinctrl
             - aspeed,ast2500-pinctrl
             - aspeed,ast2600-pinctrl
+            - aspeed,ast2700-soc0-pinctrl
+            - aspeed,ast2700-soc1-pinctrl
 
     required:
       - compatible
@@ -76,6 +84,7 @@ patternProperties:
               - aspeed,ast2400-silicon-id
               - aspeed,ast2500-silicon-id
               - aspeed,ast2600-silicon-id
+              - aspeed,ast2700-silicon-id
           - const: aspeed,silicon-id
 
       reg:
-- 
2.34.1

Re: [PATCH v3 1/4] dt-bindings: mfd: aspeed: support for AST2700

[Krzysztof Kozlowski]

On 16/09/2024 11:10, Ryan Chen wrote:
> Add compatible support for AST2700 clk, reset, pinctrl, silicon-id for AST2700 scu.

Please wrap commit message according to Linux coding style / submission
process (neither too early nor over the limit):
https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597

> 
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> ---
>  .../devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
> index 86ee69c0f45b..127a357051cd 100644
> --- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
> +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
> @@ -9,6 +9,8 @@ title: Aspeed System Control Unit
>  description:
>    The Aspeed System Control Unit manages the global behaviour of the SoC,
>    configuring elements such as clocks, pinmux, and reset.
> +  In AST2700 SOC which has two soc connection, each soc have its own scu
> +  register control, ast2700-scu0 for soc0, ast2700-scu1 for soc1.
>  
>  maintainers:
>    - Joel Stanley <joel@jms.id.au>
> @@ -21,6 +23,8 @@ properties:
>            - aspeed,ast2400-scu
>            - aspeed,ast2500-scu
>            - aspeed,ast2600-scu
> +          - aspeed,ast2700-scu0
> +          - aspeed,ast2700-scu1
>        - const: syscon
>        - const: simple-mfd
>  
> @@ -30,10 +34,12 @@ properties:
>    ranges: true
>  
>    '#address-cells':
> -    const: 1
> +    minimum: 1
> +    maximum: 2
>  
>    '#size-cells':
> -    const: 1
> +    minimum: 1
> +    maximum: 2

Why do the children have 64 bit addressing?

>  
>    '#clock-cells':
>      const: 1
> @@ -56,6 +62,8 @@ patternProperties:
>              - aspeed,ast2400-pinctrl
>              - aspeed,ast2500-pinctrl
>              - aspeed,ast2600-pinctrl
> +            - aspeed,ast2700-soc0-pinctrl
> +            - aspeed,ast2700-soc1-pinctrl

Are these devices different?

Where is this binding documented (fully)? Provide link to lore patch in
the changelog.

>  
>      required:
>        - compatible
> @@ -76,6 +84,7 @@ patternProperties:
>                - aspeed,ast2400-silicon-id
>                - aspeed,ast2500-silicon-id
>                - aspeed,ast2600-silicon-id
> +              - aspeed,ast2700-silicon-id

This one is fine.

>            - const: aspeed,silicon-id
>  
>        reg:

Best regards,
Krzysztof

RE: [PATCH v3 1/4] dt-bindings: mfd: aspeed: support for AST2700

[Ryan Chen]

> Subject: Re: [PATCH v3 1/4] dt-bindings: mfd: aspeed: support for AST2700
> 
> On 16/09/2024 11:10, Ryan Chen wrote:
> > Add compatible support for AST2700 clk, reset, pinctrl, silicon-id for AST2700
> scu.
> 
> Please wrap commit message according to Linux coding style / submission
> process (neither too early nor over the limit):
> https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/sub
> mitting-patches.rst#L597

Will update it.
> 
> >
> > Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> > ---
> >  .../devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml | 13
> > +++++++++++--
> >  1 file changed, 11 insertions(+), 2 deletions(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
> > b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
> > index 86ee69c0f45b..127a357051cd 100644
> > --- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
> > +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
> > @@ -9,6 +9,8 @@ title: Aspeed System Control Unit
> >  description:
> >    The Aspeed System Control Unit manages the global behaviour of the
> SoC,
> >    configuring elements such as clocks, pinmux, and reset.
> > +  In AST2700 SOC which has two soc connection, each soc have its own
> > + scu  register control, ast2700-scu0 for soc0, ast2700-scu1 for soc1.
> >
> >  maintainers:
> >    - Joel Stanley <joel@jms.id.au>
> > @@ -21,6 +23,8 @@ properties:
> >            - aspeed,ast2400-scu
> >            - aspeed,ast2500-scu
> >            - aspeed,ast2600-scu
> > +          - aspeed,ast2700-scu0
> > +          - aspeed,ast2700-scu1
> >        - const: syscon
> >        - const: simple-mfd
> >
> > @@ -30,10 +34,12 @@ properties:
> >    ranges: true
> >
> >    '#address-cells':
> > -    const: 1
> > +    minimum: 1
> > +    maximum: 2
> >
> >    '#size-cells':
> > -    const: 1
> > +    minimum: 1
> > +    maximum: 2
> 
> Why do the children have 64 bit addressing?

AST2700 is 64bit address, so it also.
It is children example for pinctrl.

                syscon1: syscon@14c02000 {
                        compatible = "aspeed,ast2700-scu1", "syscon", "simple-mfd";
                        reg = <0x0 0x14c02000 0x0 0x1000>;
                        ranges = <0x0 0x0 0x0 0x14c02000 0x0 0x1000>;
                        #address-cells = <2>;
                        #size-cells = <2>;
                        #clock-cells = <1>;
                        #reset-cells = <1>;

                        pinctrl1: pinctrl@400 {
                                compatible = "aspeed,ast2700-soc1-pinctrl";
                                reg = <0x0 0x400 0x0 0x100>;
                        };
                };
> 
> >
> >    '#clock-cells':
> >      const: 1
> > @@ -56,6 +62,8 @@ patternProperties:
> >              - aspeed,ast2400-pinctrl
> >              - aspeed,ast2500-pinctrl
> >              - aspeed,ast2600-pinctrl
> > +            - aspeed,ast2700-soc0-pinctrl
> > +            - aspeed,ast2700-soc1-pinctrl
> 
> Are these devices different?
> 
> Where is this binding documented (fully)? Provide link to lore patch in the
> changelog.

I will remove it in next submit. 
It will add in another pinctrl submit patch.
> 
> >
> >      required:
> >        - compatible
> > @@ -76,6 +84,7 @@ patternProperties:
> >                - aspeed,ast2400-silicon-id
> >                - aspeed,ast2500-silicon-id
> >                - aspeed,ast2600-silicon-id
> > +              - aspeed,ast2700-silicon-id
> 
> This one is fine.
Thanks.
> 
> >            - const: aspeed,silicon-id
> >
> >        reg:
> 
> Best regards,
> Krzysztof

Re: [PATCH v3 1/4] dt-bindings: mfd: aspeed: support for AST2700

[Krzysztof Kozlowski]

On 19/09/2024 08:05, Ryan Chen wrote:
>>> diff --git
>>> a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
>>> b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
>>> index 86ee69c0f45b..127a357051cd 100644
>>> --- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
>>> +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
>>> @@ -9,6 +9,8 @@ title: Aspeed System Control Unit
>>>  description:
>>>    The Aspeed System Control Unit manages the global behaviour of the
>> SoC,
>>>    configuring elements such as clocks, pinmux, and reset.
>>> +  In AST2700 SOC which has two soc connection, each soc have its own
>>> + scu  register control, ast2700-scu0 for soc0, ast2700-scu1 for soc1.
>>>
>>>  maintainers:
>>>    - Joel Stanley <joel@jms.id.au>
>>> @@ -21,6 +23,8 @@ properties:
>>>            - aspeed,ast2400-scu
>>>            - aspeed,ast2500-scu
>>>            - aspeed,ast2600-scu
>>> +          - aspeed,ast2700-scu0
>>> +          - aspeed,ast2700-scu1
>>>        - const: syscon
>>>        - const: simple-mfd
>>>
>>> @@ -30,10 +34,12 @@ properties:
>>>    ranges: true
>>>
>>>    '#address-cells':
>>> -    const: 1
>>> +    minimum: 1
>>> +    maximum: 2
>>>
>>>    '#size-cells':
>>> -    const: 1
>>> +    minimum: 1
>>> +    maximum: 2
>>
>> Why do the children have 64 bit addressing?
> 
> AST2700 is 64bit address, so it also.

But why do they need it?


Best regards,
Krzysztof

RE: [PATCH v3 1/4] dt-bindings: mfd: aspeed: support for AST2700

[Ryan Chen]

> Subject: Re: [PATCH v3 1/4] dt-bindings: mfd: aspeed: support for AST2700
> 
> On 19/09/2024 08:05, Ryan Chen wrote:
> >>> diff --git
> >>> a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
> >>> b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
> >>> index 86ee69c0f45b..127a357051cd 100644
> >>> --- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
> >>> +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
> >>> @@ -9,6 +9,8 @@ title: Aspeed System Control Unit
> >>>  description:
> >>>    The Aspeed System Control Unit manages the global behaviour of
> >>> the
> >> SoC,
> >>>    configuring elements such as clocks, pinmux, and reset.
> >>> +  In AST2700 SOC which has two soc connection, each soc have its
> >>> + own scu  register control, ast2700-scu0 for soc0, ast2700-scu1 for
> soc1.
> >>>
> >>>  maintainers:
> >>>    - Joel Stanley <joel@jms.id.au>
> >>> @@ -21,6 +23,8 @@ properties:
> >>>            - aspeed,ast2400-scu
> >>>            - aspeed,ast2500-scu
> >>>            - aspeed,ast2600-scu
> >>> +          - aspeed,ast2700-scu0
> >>> +          - aspeed,ast2700-scu1
> >>>        - const: syscon
> >>>        - const: simple-mfd
> >>>
> >>> @@ -30,10 +34,12 @@ properties:
> >>>    ranges: true
> >>>
> >>>    '#address-cells':
> >>> -    const: 1
> >>> +    minimum: 1
> >>> +    maximum: 2
> >>>
> >>>    '#size-cells':
> >>> -    const: 1
> >>> +    minimum: 1
> >>> +    maximum: 2
> >>
> >> Why do the children have 64 bit addressing?
> >
> > AST2700 is 64bit address, so it also.
> 
> But why do they need it?
> 
Sorry, I may not understand your point.
Since address-cell = <2>, Do you mean size-cell still 1?
If yes. I do the dts check it need size-cells=<2>, when I do address-cells = <2>
> 
> Best regards,
> Krzysztof

Re: [PATCH v3 1/4] dt-bindings: mfd: aspeed: support for AST2700

[Krzysztof Kozlowski]

On 19/09/2024 09:13, Ryan Chen wrote:
>> Subject: Re: [PATCH v3 1/4] dt-bindings: mfd: aspeed: support for AST2700
>>
>> On 19/09/2024 08:05, Ryan Chen wrote:
>>>>> diff --git
>>>>> a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
>>>>> b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
>>>>> index 86ee69c0f45b..127a357051cd 100644
>>>>> --- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
>>>>> +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
>>>>> @@ -9,6 +9,8 @@ title: Aspeed System Control Unit
>>>>>  description:
>>>>>    The Aspeed System Control Unit manages the global behaviour of
>>>>> the
>>>> SoC,
>>>>>    configuring elements such as clocks, pinmux, and reset.
>>>>> +  In AST2700 SOC which has two soc connection, each soc have its
>>>>> + own scu  register control, ast2700-scu0 for soc0, ast2700-scu1 for
>> soc1.
>>>>>
>>>>>  maintainers:
>>>>>    - Joel Stanley <joel@jms.id.au>
>>>>> @@ -21,6 +23,8 @@ properties:
>>>>>            - aspeed,ast2400-scu
>>>>>            - aspeed,ast2500-scu
>>>>>            - aspeed,ast2600-scu
>>>>> +          - aspeed,ast2700-scu0
>>>>> +          - aspeed,ast2700-scu1
>>>>>        - const: syscon
>>>>>        - const: simple-mfd
>>>>>
>>>>> @@ -30,10 +34,12 @@ properties:
>>>>>    ranges: true
>>>>>
>>>>>    '#address-cells':
>>>>> -    const: 1
>>>>> +    minimum: 1
>>>>> +    maximum: 2
>>>>>
>>>>>    '#size-cells':
>>>>> -    const: 1
>>>>> +    minimum: 1
>>>>> +    maximum: 2
>>>>
>>>> Why do the children have 64 bit addressing?
>>>
>>> AST2700 is 64bit address, so it also.
>>
>> But why do they need it?
>>
> Sorry, I may not understand your point.

I asked why do you think children require 64-bit addressing, instead of
working with existing 32-bit address.

> Since address-cell = <2>, Do you mean size-cell still 1?

No... although that's another point, how bug address size is there? For
the children?

> If yes. I do the dts check it need size-cells=<2>, when I do address-cells = <2>

Well, I talk about bus and children addressing. It's kind of obvious
that changing one property means using different reg...

Best regards,
Krzysztof

RE: [PATCH v3 1/4] dt-bindings: mfd: aspeed: support for AST2700

[Ryan Chen]

> Subject: Re: [PATCH v3 1/4] dt-bindings: mfd: aspeed: support for AST2700
> 
> On 19/09/2024 09:13, Ryan Chen wrote:
> >> Subject: Re: [PATCH v3 1/4] dt-bindings: mfd: aspeed: support for
> >> AST2700
> >>
> >> On 19/09/2024 08:05, Ryan Chen wrote:
> >>>>> diff --git
> >>>>> a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
> >>>>> b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
> >>>>> index 86ee69c0f45b..127a357051cd 100644
> >>>>> ---
> >>>>> a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
> >>>>> +++
> b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yam
> >>>>> +++ l
> >>>>> @@ -9,6 +9,8 @@ title: Aspeed System Control Unit
> >>>>>  description:
> >>>>>    The Aspeed System Control Unit manages the global behaviour of
> >>>>> the
> >>>> SoC,
> >>>>>    configuring elements such as clocks, pinmux, and reset.
> >>>>> +  In AST2700 SOC which has two soc connection, each soc have its
> >>>>> + own scu  register control, ast2700-scu0 for soc0, ast2700-scu1
> >>>>> + for
> >> soc1.
> >>>>>
> >>>>>  maintainers:
> >>>>>    - Joel Stanley <joel@jms.id.au> @@ -21,6 +23,8 @@ properties:
> >>>>>            - aspeed,ast2400-scu
> >>>>>            - aspeed,ast2500-scu
> >>>>>            - aspeed,ast2600-scu
> >>>>> +          - aspeed,ast2700-scu0
> >>>>> +          - aspeed,ast2700-scu1
> >>>>>        - const: syscon
> >>>>>        - const: simple-mfd
> >>>>>
> >>>>> @@ -30,10 +34,12 @@ properties:
> >>>>>    ranges: true
> >>>>>
> >>>>>    '#address-cells':
> >>>>> -    const: 1
> >>>>> +    minimum: 1
> >>>>> +    maximum: 2
> >>>>>
> >>>>>    '#size-cells':
> >>>>> -    const: 1
> >>>>> +    minimum: 1
> >>>>> +    maximum: 2
> >>>>
> >>>> Why do the children have 64 bit addressing?
> >>>
> >>> AST2700 is 64bit address, so it also.
> >>
> >> But why do they need it?
> >>
> > Sorry, I may not understand your point.
> 
> I asked why do you think children require 64-bit addressing, instead of working
> with existing 32-bit address.
> 
> > Since address-cell = <2>, Do you mean size-cell still 1?
> 
> No... although that's another point, how bug address size is there? For the
> children?
> 
> > If yes. I do the dts check it need size-cells=<2>, when I do
> > address-cells = <2>
> 
> Well, I talk about bus and children addressing. It's kind of obvious that
> changing one property means using different reg...
> 
Understood your point, I don’t use so much for size, size-cell = <1> is enough, will keep <1>
> Best regards,
> Krzysztof

[PATCH v3 2/4] dt-bindings: Add AST2700 bindings

[Ryan Chen]

Add reset, clock dt bindings for AST2700.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
 .../dt-bindings/clock/aspeed,ast2700-clk.h    | 163 ++++++++++++++++++
 .../dt-bindings/reset/aspeed,ast2700-reset.h  | 124 +++++++++++++
 2 files changed, 287 insertions(+)
 create mode 100644 include/dt-bindings/clock/aspeed,ast2700-clk.h
 create mode 100644 include/dt-bindings/reset/aspeed,ast2700-reset.h

diff --git a/include/dt-bindings/clock/aspeed,ast2700-clk.h b/include/dt-bindings/clock/aspeed,ast2700-clk.h
new file mode 100644
index 000000000000..63021af3caf5
--- /dev/null
+++ b/include/dt-bindings/clock/aspeed,ast2700-clk.h
@@ -0,0 +1,163 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Device Tree binding constants for AST2700 clock controller.
+ *
+ * Copyright (c) 2024 Aspeed Technology Inc.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_AST2700_H
+#define __DT_BINDINGS_CLOCK_AST2700_H
+
+/* SOC0 clk */
+#define SCU0_CLKIN		0
+#define SCU0_CLK_24M		1
+#define SCU0_CLK_192M		2
+#define SCU0_CLK_UART		3
+#define SCU0_CLK_UART_DIV13	3
+#define SCU0_CLK_PSP		4
+#define SCU0_CLK_HPLL		5
+#define SCU0_CLK_HPLL_DIV2	6
+#define SCU0_CLK_HPLL_DIV4	7
+#define SCU0_CLK_HPLL_DIV_AHB	8
+#define SCU0_CLK_DPLL		9
+#define SCU0_CLK_MPLL		10
+#define SCU0_CLK_MPLL_DIV2	11
+#define SCU0_CLK_MPLL_DIV4	12
+#define SCU0_CLK_MPLL_DIV8	13
+#define SCU0_CLK_MPLL_DIV_AHB	14
+#define SCU0_CLK_D0		15
+#define SCU0_CLK_D1		16
+#define SCU0_CLK_CRT0		17
+#define SCU0_CLK_CRT1		18
+#define SCU0_CLK_MPHY		19
+#define SCU0_CLK_AXI0		20
+#define SCU0_CLK_AXI1		21
+#define SCU0_CLK_AHB		22
+#define SCU0_CLK_APB		23
+#define SCU0_CLK_UART4		24
+#define SCU0_CLK_EMMCMUX	25
+#define SCU0_CLK_EMMC		26
+#define SCU0_CLK_U2PHY_CLK12M	27
+#define SCU0_CLK_U2PHY_REFCLK	28
+
+/* SOC0 clk-gate */
+#define SCU0_CLK_GATE_MCLK	29
+#define SCU0_CLK_GATE_ECLK	30
+#define SCU0_CLK_GATE_2DCLK	31
+#define SCU0_CLK_GATE_VCLK	32
+#define SCU0_CLK_GATE_BCLK	33
+#define SCU0_CLK_GATE_VGA0CLK	34
+#define SCU0_CLK_GATE_REFCLK	35
+#define SCU0_CLK_GATE_PORTBUSB2CLK	36
+#define SCU0_CLK_GATE_UHCICLK	37
+#define SCU0_CLK_GATE_VGA1CLK	38
+#define SCU0_CLK_GATE_DDRPHYCLK	39
+#define SCU0_CLK_GATE_E2M0CLK	40
+#define SCU0_CLK_GATE_HACCLK	41
+#define SCU0_CLK_GATE_PORTAUSB2CLK	42
+#define SCU0_CLK_GATE_UART4CLK	43
+#define SCU0_CLK_GATE_SLICLK	44
+#define SCU0_CLK_GATE_DACCLK	45
+#define SCU0_CLK_GATE_DP	46
+#define SCU0_CLK_GATE_E2M1CLK	47
+#define SCU0_CLK_GATE_CRT0CLK	48
+#define SCU0_CLK_GATE_CRT1CLK	49
+#define SCU0_CLK_GATE_ECDSACLK	50
+#define SCU0_CLK_GATE_RSACLK	51
+#define SCU0_CLK_GATE_RVAS0CLK	52
+#define SCU0_CLK_GATE_UFSCLK	53
+#define SCU0_CLK_GATE_EMMCCLK	54
+#define SCU0_CLK_GATE_RVAS1CLK	55
+
+/* SOC1 clk */
+#define SCU1_CLKIN		0
+#define SCU1_CLK_HPLL		1
+#define SCU1_CLK_APLL		2
+#define SCU1_CLK_APLL_DIV2	3
+#define SCU1_CLK_APLL_DIV4	4
+#define SCU1_CLK_DPLL		5
+#define SCU1_CLK_UXCLK		6
+#define SCU1_CLK_HUXCLK		7
+#define SCU1_CLK_UARTX		8
+#define SCU1_CLK_HUARTX		9
+#define SCU1_CLK_AHB		10
+#define SCU1_CLK_APB		11
+#define SCU1_CLK_UART0		12
+#define SCU1_CLK_UART1		13
+#define SCU1_CLK_UART2		14
+#define SCU1_CLK_UART3		15
+#define SCU1_CLK_UART5		16
+#define SCU1_CLK_UART6		17
+#define SCU1_CLK_UART7		18
+#define SCU1_CLK_UART8		19
+#define SCU1_CLK_UART9		20
+#define SCU1_CLK_UART10		21
+#define SCU1_CLK_UART11		22
+#define SCU1_CLK_UART12		23
+#define SCU1_CLK_UART13		24
+#define SCU1_CLK_UART14		25
+#define SCU1_CLK_APLL_DIVN	26
+#define SCU1_CLK_SDMUX		27
+#define SCU1_CLK_SDCLK		28
+#define SCU1_CLK_RMII		29
+#define SCU1_CLK_RGMII		30
+#define SCU1_CLK_MACHCLK	31
+#define SCU1_CLK_MAC0RCLK	32
+#define SCU1_CLK_MAC1RCLK	33
+#define SCU1_CLK_CAN		34
+
+/* SOC1 clk gate */
+#define SCU1_CLK_GATE_LCLK0		35
+#define SCU1_CLK_GATE_LCLK1		36
+#define SCU1_CLK_GATE_ESPI0CLK		37
+#define SCU1_CLK_GATE_ESPI1CLK		38
+#define SCU1_CLK_GATE_SDCLK		39
+#define SCU1_CLK_GATE_IPEREFCLK		40
+#define SCU1_CLK_GATE_REFCLK		41
+#define SCU1_CLK_GATE_LPCHCLK		42
+#define SCU1_CLK_GATE_MAC0CLK		43
+#define SCU1_CLK_GATE_MAC1CLK		44
+#define SCU1_CLK_GATE_MAC2CLK		45
+#define SCU1_CLK_GATE_UART0CLK		46
+#define SCU1_CLK_GATE_UART1CLK		47
+#define SCU1_CLK_GATE_UART2CLK		48
+#define SCU1_CLK_GATE_UART3CLK		49
+#define SCU1_CLK_GATE_I2CCLK		50
+#define SCU1_CLK_GATE_I3C0CLK		51
+#define SCU1_CLK_GATE_I3C1CLK		52
+#define SCU1_CLK_GATE_I3C2CLK		53
+#define SCU1_CLK_GATE_I3C3CLK		54
+#define SCU1_CLK_GATE_I3C4CLK		55
+#define SCU1_CLK_GATE_I3C5CLK		56
+#define SCU1_CLK_GATE_I3C6CLK		57
+#define SCU1_CLK_GATE_I3C7CLK		58
+#define SCU1_CLK_GATE_I3C8CLK		59
+#define SCU1_CLK_GATE_I3C9CLK		60
+#define SCU1_CLK_GATE_I3C10CLK		61
+#define SCU1_CLK_GATE_I3C11CLK		62
+#define SCU1_CLK_GATE_I3C12CLK		63
+#define SCU1_CLK_GATE_I3C13CLK		64
+#define SCU1_CLK_GATE_I3C14CLK		65
+#define SCU1_CLK_GATE_I3C15CLK		66
+#define SCU1_CLK_GATE_UART5CLK		67
+#define SCU1_CLK_GATE_UART6CLK		68
+#define SCU1_CLK_GATE_UART7CLK		69
+#define SCU1_CLK_GATE_UART8CLK		70
+#define SCU1_CLK_GATE_UART9CLK		71
+#define SCU1_CLK_GATE_UART10CLK		72
+#define SCU1_CLK_GATE_UART11CLK		73
+#define SCU1_CLK_GATE_UART12CLK		74
+#define SCU1_CLK_GATE_FSICLK		75
+#define SCU1_CLK_GATE_LTPIPHYCLK	76
+#define SCU1_CLK_GATE_LTPICLK		77
+#define SCU1_CLK_GATE_VGALCLK		78
+#define SCU1_CLK_GATE_UHCICLK		79
+#define SCU1_CLK_GATE_CANCLK		80
+#define SCU1_CLK_GATE_PCICLK		81
+#define SCU1_CLK_GATE_SLICLK		82
+#define SCU1_CLK_GATE_E2MCLK		83
+#define SCU1_CLK_GATE_PORTCUSB2CLK	84
+#define SCU1_CLK_GATE_PORTDUSB2CLK	85
+#define SCU1_CLK_GATE_LTPI1TXCLK	86
+
+#endif
diff --git a/include/dt-bindings/reset/aspeed,ast2700-reset.h b/include/dt-bindings/reset/aspeed,ast2700-reset.h
new file mode 100644
index 000000000000..c5fbb91d9341
--- /dev/null
+++ b/include/dt-bindings/reset/aspeed,ast2700-reset.h
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Device Tree binding constants for AST2700 reset controller.
+ *
+ * Copyright (c) 2024 Aspeed Technology Inc.
+ */
+
+#ifndef _MACH_ASPEED_AST2700_RESET_H_
+#define _MACH_ASPEED_AST2700_RESET_H_
+
+/* SOC0 */
+#define SCU0_RESET_SDRAM		(0)
+#define SCU0_RESET_DDRPHY		(1)
+#define SCU0_RESET_RSA		(2)
+#define SCU0_RESET_SHA3		(3)
+#define SCU0_RESET_HACE		(4)
+#define SCU0_RESET_SOC		(5)
+#define SCU0_RESET_VIDEO		(6)
+#define SCU0_RESET_2D			(7)
+#define SCU0_RESET_PCIS		(8)
+#define SCU0_RESET_RVAS0		(9)
+#define SCU0_RESET_RVAS1		(10)
+#define SCU0_RESET_SM3		(11)
+#define SCU0_RESET_SM4		(12)
+#define SCU0_RESET_CRT0		(13)
+#define SCU0_RESET_ECC		(14)
+#define SCU0_RESET_DP_PCI		(15)
+#define SCU0_RESET_UFS		(16)
+#define SCU0_RESET_EMMC		(17)
+#define SCU0_RESET_PCIE1RST		(18)
+#define SCU0_RESET_PCIE1RSTOE	(19)
+#define SCU0_RESET_PCIE0RST		(20)
+#define SCU0_RESET_PCIE0RSTOE	(21)
+#define SCU0_RESET_JTAG			(22)
+#define SCU0_RESET_MCTP0		(23)
+#define SCU0_RESET_MCTP1		(24)
+#define SCU0_RESET_XDMA0		(25)
+#define SCU0_RESET_XDMA1		(26)
+#define SCU0_RESET_H2X1		(27)
+#define SCU0_RESET_DP			(28)
+#define SCU0_RESET_DP_MCU		(29)
+#define SCU0_RESET_SSP		(30)
+#define SCU0_RESET_H2X0		(31)
+#define SCU0_RESET_PORTA_VHUB		(32)
+#define SCU0_RESET_PORTA_PHY3		(33)
+#define SCU0_RESET_PORTA_XHCI		(34)
+#define SCU0_RESET_PORTB_VHUB		(35)
+#define SCU0_RESET_PORTB_PHY3		(36)
+#define SCU0_RESET_PORTB_XHCI		(37)
+#define SCU0_RESET_PORTA_VHUB_EHCI	(38)
+#define SCU0_RESET_PORTB_VHUB_EHCI	(39)
+#define SCU0_RESET_UHCI		(40)
+#define SCU0_RESET_TSP		(41)
+#define SCU0_RESET_E2M0		(42)
+#define SCU0_RESET_E2M1		(43)
+#define SCU0_RESET_VLINK		(44)
+
+/* SOC1 */
+#define SCU1_RESET_LPC0		(0)
+#define SCU1_RESET_LPC1		(1)
+#define SCU1_RESET_MII		(2)
+#define SCU1_RESET_PECI		(3)
+#define SCU1_RESET_PWM		(4)
+#define SCU1_RESET_MAC0		(5)
+#define SCU1_RESET_MAC1		(6)
+#define SCU1_RESET_MAC2		(7)
+#define SCU1_RESET_ADC		(8)
+#define SCU1_RESET_SD			(9)
+#define SCU1_RESET_ESPI0		(10)
+#define SCU1_RESET_ESPI1		(11)
+#define SCU1_RESET_JTAG1		(12)
+#define SCU1_RESET_SPI0		(13)
+#define SCU1_RESET_SPI1		(14)
+#define SCU1_RESET_SPI2		(15)
+#define SCU1_RESET_I3C0		(16)
+#define SCU1_RESET_I3C1		(17)
+#define SCU1_RESET_I3C2		(18)
+#define SCU1_RESET_I3C3		(19)
+#define SCU1_RESET_I3C4		(20)
+#define SCU1_RESET_I3C5		(21)
+#define SCU1_RESET_I3C6		(22)
+#define SCU1_RESET_I3C7		(23)
+#define SCU1_RESET_I3C8		(24)
+#define SCU1_RESET_I3C9		(25)
+#define SCU1_RESET_I3C10		(26)
+#define SCU1_RESET_I3C11		(27)
+#define SCU1_RESET_I3C12		(28)
+#define SCU1_RESET_I3C13		(29)
+#define SCU1_RESET_I3C14		(30)
+#define SCU1_RESET_I3C15		(31)
+#define SCU1_RESET_MCU0		(32)
+#define SCU1_RESET_MCU1		(33)
+#define SCU1_RESET_H2A_SPI1		(34)
+#define SCU1_RESET_H2A_SPI2		(35)
+#define SCU1_RESET_UART0		(36)
+#define SCU1_RESET_UART1		(37)
+#define SCU1_RESET_UART2		(38)
+#define SCU1_RESET_UART3		(39)
+#define SCU1_RESET_I2C_FILTER		(40)
+#define SCU1_RESET_CALIPTRA		(41)
+#define SCU1_RESET_XDMA			(42)
+#define SCU1_RESET_FSI		(43)
+#define SCU1_RESET_CAN		(44)
+#define SCU1_RESET_MCTP		(45)
+#define SCU1_RESET_I2C		(46)
+#define SCU1_RESET_UART6		(47)
+#define SCU1_RESET_UART7		(48)
+#define SCU1_RESET_UART8		(49)
+#define SCU1_RESET_UART9		(50)
+#define SCU1_RESET_LTPI0		(51)
+#define SCU1_RESET_VGAL		(52)
+#define SCU1_RESET_LTPI1		(53)
+#define SCU1_RESET_ACE		(54)
+#define SCU1_RESET_E2M		(55)
+#define SCU1_RESET_UHCI		(56)
+#define SCU1_RESET_PORTC_USB2UART	(57)
+#define SCU1_RESET_PORTC_VHUB_EHCI	(58)
+#define SCU1_RESET_PORTD_USB2UART	(59)
+#define SCU1_RESET_PORTD_VHUB_EHCI	(60)
+#define SCU1_RESET_H2X		(61)
+#define SCU1_RESET_I3CDMA             (62)
+#define SCU1_RESET_PCIE2RST	(63)
+
+#endif  /* _MACH_ASPEED_AST2700_RESET_H_ */
-- 
2.34.1

Re: [PATCH v3 2/4] dt-bindings: Add AST2700 bindings

[Krzysztof Kozlowski]

On 16/09/2024 11:10, Ryan Chen wrote:
> Add reset, clock dt bindings for AST2700.
> 
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> ---
>  .../dt-bindings/clock/aspeed,ast2700-clk.h    | 163 ++++++++++++++++++
>  .../dt-bindings/reset/aspeed,ast2700-reset.h  | 124 +++++++++++++
>  2 files changed, 287 insertions(+)

This is supposed to be part of the commit adding these bindings. You got
this comment already, didn't you?

>  create mode 100644 include/dt-bindings/clock/aspeed,ast2700-clk.h
>  create mode 100644 include/dt-bindings/reset/aspeed,ast2700-reset.h
> 
> diff --git a/include/dt-bindings/clock/aspeed,ast2700-clk.h b/include/dt-bindings/clock/aspeed,ast2700-clk.h
> new file mode 100644
> index 000000000000..63021af3caf5
> --- /dev/null
> +++ b/include/dt-bindings/clock/aspeed,ast2700-clk.h

Use compatible as filename.


Best regards,
Krzysztof

RE: [PATCH v3 2/4] dt-bindings: Add AST2700 bindings

[Ryan Chen]

> Subject: Re: [PATCH v3 2/4] dt-bindings: Add AST2700 bindings
> 
> On 16/09/2024 11:10, Ryan Chen wrote:
> > Add reset, clock dt bindings for AST2700.
> >
> > Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> > ---
> >  .../dt-bindings/clock/aspeed,ast2700-clk.h    | 163
> ++++++++++++++++++
> >  .../dt-bindings/reset/aspeed,ast2700-reset.h  | 124 +++++++++++++
> >  2 files changed, 287 insertions(+)
> 
> This is supposed to be part of the commit adding these bindings. You got this
> comment already, didn't you?

Sorry, I may mis-understood your point in previous.
I think you are ask, yaml and dt-binding header to be the same patch, right?

> 
> >  create mode 100644 include/dt-bindings/clock/aspeed,ast2700-clk.h
> >  create mode 100644 include/dt-bindings/reset/aspeed,ast2700-reset.h
> >
> > diff --git a/include/dt-bindings/clock/aspeed,ast2700-clk.h
> > b/include/dt-bindings/clock/aspeed,ast2700-clk.h
> > new file mode 100644
> > index 000000000000..63021af3caf5
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/aspeed,ast2700-clk.h
> 
> Use compatible as filename.
Modify from aspeed,ast2700-clk.h to aspeed, clk-ast2700.h, is it ok?
How about the aspeed,ast2700-reset.h file name is ok ?
> 
> 
> Best regards,
> Krzysztof

Re: [PATCH v3 2/4] dt-bindings: Add AST2700 bindings

[Krzysztof Kozlowski]

On 19/09/2024 08:01, Ryan Chen wrote:
>> Subject: Re: [PATCH v3 2/4] dt-bindings: Add AST2700 bindings
>>
>> On 16/09/2024 11:10, Ryan Chen wrote:
>>> Add reset, clock dt bindings for AST2700.
>>>
>>> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
>>> ---
>>>  .../dt-bindings/clock/aspeed,ast2700-clk.h    | 163
>> ++++++++++++++++++
>>>  .../dt-bindings/reset/aspeed,ast2700-reset.h  | 124 +++++++++++++
>>>  2 files changed, 287 insertions(+)
>>
>> This is supposed to be part of the commit adding these bindings. You got this
>> comment already, didn't you?
> 
> Sorry, I may mis-understood your point in previous.
> I think you are ask, yaml and dt-binding header to be the same patch, right?

It is one patch adding the binding for the device and headers.

> 
>>
>>>  create mode 100644 include/dt-bindings/clock/aspeed,ast2700-clk.h
>>>  create mode 100644 include/dt-bindings/reset/aspeed,ast2700-reset.h
>>>
>>> diff --git a/include/dt-bindings/clock/aspeed,ast2700-clk.h
>>> b/include/dt-bindings/clock/aspeed,ast2700-clk.h
>>> new file mode 100644
>>> index 000000000000..63021af3caf5
>>> --- /dev/null
>>> +++ b/include/dt-bindings/clock/aspeed,ast2700-clk.h
>>
>> Use compatible as filename.
> Modify from aspeed,ast2700-clk.h to aspeed, clk-ast2700.h, is it ok?
> How about the aspeed,ast2700-reset.h file name is ok ?

No. For both use the same filename, so the full compatible. FULL.

Best regards,
Krzysztof

RE: [PATCH v3 2/4] dt-bindings: Add AST2700 bindings

[Ryan Chen]

> Subject: Re: [PATCH v3 2/4] dt-bindings: Add AST2700 bindings
> 
> On 19/09/2024 08:01, Ryan Chen wrote:
> >> Subject: Re: [PATCH v3 2/4] dt-bindings: Add AST2700 bindings
> >>
> >> On 16/09/2024 11:10, Ryan Chen wrote:
> >>> Add reset, clock dt bindings for AST2700.
> >>>
> >>> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> >>> ---
> >>>  .../dt-bindings/clock/aspeed,ast2700-clk.h    | 163
> >> ++++++++++++++++++
> >>>  .../dt-bindings/reset/aspeed,ast2700-reset.h  | 124 +++++++++++++
> >>>  2 files changed, 287 insertions(+)
> >>
> >> This is supposed to be part of the commit adding these bindings. You
> >> got this comment already, didn't you?
> >
> > Sorry, I may mis-understood your point in previous.
> > I think you are ask, yaml and dt-binding header to be the same patch, right?
> 
> It is one patch adding the binding for the device and headers.
Thanks.
> 
> >
> >>
> >>>  create mode 100644 include/dt-bindings/clock/aspeed,ast2700-clk.h
> >>>  create mode 100644 include/dt-bindings/reset/aspeed,ast2700-reset.h
> >>>
> >>> diff --git a/include/dt-bindings/clock/aspeed,ast2700-clk.h
> >>> b/include/dt-bindings/clock/aspeed,ast2700-clk.h
> >>> new file mode 100644
> >>> index 000000000000..63021af3caf5
> >>> --- /dev/null
> >>> +++ b/include/dt-bindings/clock/aspeed,ast2700-clk.h
> >>
> >> Use compatible as filename.
> > Modify from aspeed,ast2700-clk.h to aspeed, clk-ast2700.h, is it ok?
> > How about the aspeed,ast2700-reset.h file name is ok ?
> 
> No. For both use the same filename, so the full compatible. FULL.

Do you mean remove aspeed,ast2700-reset.h?
And move reset information into "aspeed, clk-ast2700.h"
> 
> Best regards,
> Krzysztof

Re: [PATCH v3 2/4] dt-bindings: Add AST2700 bindings

[Krzysztof Kozlowski]

On 19/09/2024 09:15, Ryan Chen wrote:
>>>>
>>>>>  create mode 100644 include/dt-bindings/clock/aspeed,ast2700-clk.h
>>>>>  create mode 100644 include/dt-bindings/reset/aspeed,ast2700-reset.h
>>>>>
>>>>> diff --git a/include/dt-bindings/clock/aspeed,ast2700-clk.h
>>>>> b/include/dt-bindings/clock/aspeed,ast2700-clk.h
>>>>> new file mode 100644
>>>>> index 000000000000..63021af3caf5
>>>>> --- /dev/null
>>>>> +++ b/include/dt-bindings/clock/aspeed,ast2700-clk.h
>>>>
>>>> Use compatible as filename.
>>> Modify from aspeed,ast2700-clk.h to aspeed, clk-ast2700.h, is it ok?
>>> How about the aspeed,ast2700-reset.h file name is ok ?
>>
>> No. For both use the same filename, so the full compatible. FULL.
> 
> Do you mean remove aspeed,ast2700-reset.h?
> And move reset information into "aspeed, clk-ast2700.h"
>>

I did not say that. "For both" means for both files, so you can keep
both files.


Best regards,
Krzysztof

RE: [PATCH v3 2/4] dt-bindings: Add AST2700 bindings

[Ryan Chen]

> Subject: Re: [PATCH v3 2/4] dt-bindings: Add AST2700 bindings
> 
> On 19/09/2024 09:15, Ryan Chen wrote:
> >>>>
> >>>>>  create mode 100644 include/dt-bindings/clock/aspeed,ast2700-clk.h
> >>>>>  create mode 100644
> >>>>> include/dt-bindings/reset/aspeed,ast2700-reset.h
> >>>>>
> >>>>> diff --git a/include/dt-bindings/clock/aspeed,ast2700-clk.h
> >>>>> b/include/dt-bindings/clock/aspeed,ast2700-clk.h
> >>>>> new file mode 100644
> >>>>> index 000000000000..63021af3caf5
> >>>>> --- /dev/null
> >>>>> +++ b/include/dt-bindings/clock/aspeed,ast2700-clk.h
> >>>>
> >>>> Use compatible as filename.
> >>> Modify from aspeed,ast2700-clk.h to aspeed, clk-ast2700.h, is it ok?
> >>> How about the aspeed,ast2700-reset.h file name is ok ?
> >>
> >> No. For both use the same filename, so the full compatible. FULL.
> >
> > Do you mean remove aspeed,ast2700-reset.h?
> > And move reset information into "aspeed, clk-ast2700.h"
> >>
> 
> I did not say that. "For both" means for both files, so you can keep both files.
> 
So, I think you want both file use the same name right? To be following
include/dt-bindings/clock/aspeed,ast2700-scu.h
include/dt-bindings/reset/aspeed,ast2700-scu.h

> 
> Best regards,
> Krzysztof

[PATCH v3 3/4] reset: aspeed: register AST2700 reset auxiliary bus device

[Ryan Chen]

The AST2700 reset driver is registered as an auxiliary device
due to reset and clock controller share the same register region.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
 drivers/reset/Kconfig        |   6 +
 drivers/reset/Makefile       |   1 +
 drivers/reset/reset-aspeed.c | 259 +++++++++++++++++++++++++++++++++++
 3 files changed, 266 insertions(+)
 create mode 100644 drivers/reset/reset-aspeed.c

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 67bce340a87e..612f22e1180d 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -22,6 +22,12 @@ config RESET_A10SR
 	  This option enables support for the external reset functions for
 	  peripheral PHYs on the Altera Arria10 System Resource Chip.
 
+config RESET_ASPEED
+	tristate "ASPEED Reset Driver"
+	depends on ARCH_ASPEED || COMPILE_TEST
+	help
+	  This enables the reset controller driver for AST2700.
+
 config RESET_ATH79
 	bool "AR71xx Reset Driver" if COMPILE_TEST
 	default ATH79
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 27b0bbdfcc04..97482bb56416 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -5,6 +5,7 @@ obj-y += starfive/
 obj-y += sti/
 obj-y += tegra/
 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
+obj-$(CONFIG_RESET_ASPEED) += reset-aspeed.o
 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
 obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
 obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
diff --git a/drivers/reset/reset-aspeed.c b/drivers/reset/reset-aspeed.c
new file mode 100644
index 000000000000..2ec662610855
--- /dev/null
+++ b/drivers/reset/reset-aspeed.c
@@ -0,0 +1,259 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2024 ASPEED Technology Inc.
+ */
+
+#include <linux/auxiliary_bus.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/reset/aspeed,ast2700-reset.h>
+
+#define SCU0_RESET_CTRL1 0x200
+#define SCU0_RESET_CTRL2 0x220
+#define SCU1_RESET_CTRL1 0x200
+#define SCU1_RESET_CTRL2 0x220
+#define SCU1_PCIE3_CTRL 0x908
+
+struct ast2700_reset_signal {
+	bool dedicated_clr; /* dedicated reset clr offset */
+	u32 offset, bit;
+};
+
+struct aspeed_reset_info {
+	unsigned int nr_resets;
+	const struct ast2700_reset_signal *signal;
+};
+
+struct aspeed_reset {
+	struct reset_controller_dev rcdev;
+	struct aspeed_reset_info *info;
+	spinlock_t lock; /* Protect read-modify-write cycle */
+	void __iomem *base;
+};
+
+static const struct ast2700_reset_signal ast2700_reset0_signals[] = {
+	[SCU0_RESET_SDRAM] = { true, SCU0_RESET_CTRL1, BIT(0) },
+	[SCU0_RESET_DDRPHY] = { true, SCU0_RESET_CTRL1, BIT(1) },
+	[SCU0_RESET_RSA]     = { true, SCU0_RESET_CTRL1, BIT(2) },
+	[SCU0_RESET_SHA3]	= { true, SCU0_RESET_CTRL1, BIT(3) },
+	[SCU0_RESET_HACE]	= { true, SCU0_RESET_CTRL1, BIT(4) },
+	[SCU0_RESET_SOC]	= { true, SCU0_RESET_CTRL1, BIT(5) },
+	[SCU0_RESET_VIDEO]	= { true, SCU0_RESET_CTRL1, BIT(6) },
+	[SCU0_RESET_2D]	= { true, SCU0_RESET_CTRL1, BIT(7) },
+	[SCU0_RESET_PCIS]	= { true, SCU0_RESET_CTRL1, BIT(8) },
+	[SCU0_RESET_RVAS0]		= { true, SCU0_RESET_CTRL1, BIT(9) },
+	[SCU0_RESET_RVAS1]		= { true, SCU0_RESET_CTRL1, BIT(10) },
+	[SCU0_RESET_SM3]		= { true, SCU0_RESET_CTRL1, BIT(11) },
+	[SCU0_RESET_SM4]		= { true, SCU0_RESET_CTRL1, BIT(12) },
+	[SCU0_RESET_CRT0]	= { true, SCU0_RESET_CTRL1, BIT(13) },
+	[SCU0_RESET_ECC]	= { true, SCU0_RESET_CTRL1, BIT(14) },
+	[SCU0_RESET_DP_PCI]	= { true, SCU0_RESET_CTRL1, BIT(15) },
+	[SCU0_RESET_UFS]	= { true, SCU0_RESET_CTRL1, BIT(16) },
+	[SCU0_RESET_EMMC]	= { true, SCU0_RESET_CTRL1, BIT(17) },
+	[SCU0_RESET_PCIE1RST]	= { true, SCU0_RESET_CTRL1, BIT(18) },
+	[SCU0_RESET_PCIE1RSTOE]	= { true, SCU0_RESET_CTRL1, BIT(19) },
+	[SCU0_RESET_PCIE0RST]		= { true, SCU0_RESET_CTRL1, BIT(20) },
+	[SCU0_RESET_PCIE0RSTOE]	= { true, SCU0_RESET_CTRL1, BIT(21) },
+	[SCU0_RESET_JTAG]	= { true, SCU0_RESET_CTRL1, BIT(22) },
+	[SCU0_RESET_MCTP0] = { true, SCU0_RESET_CTRL1, BIT(23) },
+	[SCU0_RESET_MCTP1]		= { true, SCU0_RESET_CTRL1, BIT(24) },
+	[SCU0_RESET_XDMA0]	= { true, SCU0_RESET_CTRL1, BIT(25) },
+	[SCU0_RESET_XDMA1]	= { true, SCU0_RESET_CTRL1, BIT(26) },
+	[SCU0_RESET_H2X1]	= { true, SCU0_RESET_CTRL1, BIT(27) },
+	[SCU0_RESET_DP]	= { true, SCU0_RESET_CTRL1, BIT(28) },
+	[SCU0_RESET_DP_MCU]	= { true, SCU0_RESET_CTRL1, BIT(29) },
+	[SCU0_RESET_SSP]	= { true, SCU0_RESET_CTRL1, BIT(30) },
+	[SCU0_RESET_H2X0]	= { true, SCU0_RESET_CTRL1, BIT(31) },
+	[SCU0_RESET_PORTA_VHUB]	= { true, SCU0_RESET_CTRL2, BIT(0) },
+	[SCU0_RESET_PORTA_PHY3]	= { true, SCU0_RESET_CTRL2, BIT(1) },
+	[SCU0_RESET_PORTA_XHCI]	= { true, SCU0_RESET_CTRL2, BIT(2) },
+	[SCU0_RESET_PORTB_VHUB]	= { true, SCU0_RESET_CTRL2, BIT(3) },
+	[SCU0_RESET_PORTB_PHY3]	= { true, SCU0_RESET_CTRL2, BIT(4) },
+	[SCU0_RESET_PORTB_XHCI]	= { true, SCU0_RESET_CTRL2, BIT(5) },
+	[SCU0_RESET_PORTA_VHUB_EHCI]	= { true, SCU0_RESET_CTRL2, BIT(6) },
+	[SCU0_RESET_PORTB_VHUB_EHCI]	= { true, SCU0_RESET_CTRL2, BIT(7) },
+	[SCU0_RESET_UHCI]	= { true, SCU0_RESET_CTRL2, BIT(8) },
+	[SCU0_RESET_TSP]	= { true, SCU0_RESET_CTRL2, BIT(9) },
+	[SCU0_RESET_E2M0]	= { true, SCU0_RESET_CTRL2, BIT(10) },
+	[SCU0_RESET_E2M1]	= { true, SCU0_RESET_CTRL2, BIT(11) },
+	[SCU0_RESET_VLINK]	= { true, SCU0_RESET_CTRL2, BIT(12) },
+};
+
+static const struct ast2700_reset_signal ast2700_reset1_signals[] = {
+	[SCU1_RESET_LPC0] = { true, SCU1_RESET_CTRL1, BIT(0) },
+	[SCU1_RESET_LPC1] = { true, SCU1_RESET_CTRL1, BIT(1) },
+	[SCU1_RESET_MII]     = { true, SCU1_RESET_CTRL1, BIT(2) },
+	[SCU1_RESET_PECI]	= { true, SCU1_RESET_CTRL1, BIT(3) },
+	[SCU1_RESET_PWM]	= { true, SCU1_RESET_CTRL1, BIT(4) },
+	[SCU1_RESET_MAC0]	= { true, SCU1_RESET_CTRL1, BIT(5) },
+	[SCU1_RESET_MAC1]	= { true, SCU1_RESET_CTRL1, BIT(6) },
+	[SCU1_RESET_MAC2]	= { true, SCU1_RESET_CTRL1, BIT(7) },
+	[SCU1_RESET_ADC]	= { true, SCU1_RESET_CTRL1, BIT(8) },
+	[SCU1_RESET_SD]		= { true, SCU1_RESET_CTRL1, BIT(9) },
+	[SCU1_RESET_ESPI0]		= { true, SCU1_RESET_CTRL1, BIT(10) },
+	[SCU1_RESET_ESPI1]		= { true, SCU1_RESET_CTRL1, BIT(11) },
+	[SCU1_RESET_JTAG1]		= { true, SCU1_RESET_CTRL1, BIT(12) },
+	[SCU1_RESET_SPI0]	= { true, SCU1_RESET_CTRL1, BIT(13) },
+	[SCU1_RESET_SPI1]	= { true, SCU1_RESET_CTRL1, BIT(14) },
+	[SCU1_RESET_SPI2]	= { true, SCU1_RESET_CTRL1, BIT(15) },
+	[SCU1_RESET_I3C0]	= { true, SCU1_RESET_CTRL1, BIT(16) },
+	[SCU1_RESET_I3C1]	= { true, SCU1_RESET_CTRL1, BIT(17) },
+	[SCU1_RESET_I3C2]	= { true, SCU1_RESET_CTRL1, BIT(18) },
+	[SCU1_RESET_I3C3]	= { true, SCU1_RESET_CTRL1, BIT(19) },
+	[SCU1_RESET_I3C4]		= { true, SCU1_RESET_CTRL1, BIT(20) },
+	[SCU1_RESET_I3C5]	= { true, SCU1_RESET_CTRL1, BIT(21) },
+	[SCU1_RESET_I3C6]	= { true, SCU1_RESET_CTRL1, BIT(22) },
+	[SCU1_RESET_I3C7] = { true, SCU1_RESET_CTRL1, BIT(23) },
+	[SCU1_RESET_I3C8]		= { true, SCU1_RESET_CTRL1, BIT(24) },
+	[SCU1_RESET_I3C9]	= { true, SCU1_RESET_CTRL1, BIT(25) },
+	[SCU1_RESET_I3C10]	= { true, SCU1_RESET_CTRL1, BIT(26) },
+	[SCU1_RESET_I3C11]	= { true, SCU1_RESET_CTRL1, BIT(27) },
+	[SCU1_RESET_I3C12]	= { true, SCU1_RESET_CTRL1, BIT(28) },
+	[SCU1_RESET_I3C13]	= { true, SCU1_RESET_CTRL1, BIT(29) },
+	[SCU1_RESET_I3C14]	= { true, SCU1_RESET_CTRL1, BIT(30) },
+	[SCU1_RESET_I3C15]	= { true, SCU1_RESET_CTRL1, BIT(31) },
+	[SCU1_RESET_MCU0]	= { true, SCU1_RESET_CTRL2, BIT(0) },
+	[SCU1_RESET_MCU1]	= { true, SCU1_RESET_CTRL2, BIT(1) },
+	[SCU1_RESET_H2A_SPI1]	= { true, SCU1_RESET_CTRL2, BIT(2) },
+	[SCU1_RESET_H2A_SPI2]	= { true, SCU1_RESET_CTRL2, BIT(3) },
+	[SCU1_RESET_UART0]	= { true, SCU1_RESET_CTRL2, BIT(4) },
+	[SCU1_RESET_UART1]	= { true, SCU1_RESET_CTRL2, BIT(5) },
+	[SCU1_RESET_UART2]	= { true, SCU1_RESET_CTRL2, BIT(6) },
+	[SCU1_RESET_UART3]	= { true, SCU1_RESET_CTRL2, BIT(7) },
+	[SCU1_RESET_I2C_FILTER]	= { true, SCU1_RESET_CTRL2, BIT(8) },
+	[SCU1_RESET_CALIPTRA]	= { true, SCU1_RESET_CTRL2, BIT(9) },
+	[SCU1_RESET_XDMA]	= { true, SCU1_RESET_CTRL2, BIT(10) },
+	[SCU1_RESET_FSI]	= { true, SCU1_RESET_CTRL2, BIT(12) },
+	[SCU1_RESET_CAN]	= { true, SCU1_RESET_CTRL2, BIT(13) },
+	[SCU1_RESET_MCTP]	= { true, SCU1_RESET_CTRL2, BIT(14) },
+	[SCU1_RESET_I2C]	= { true, SCU1_RESET_CTRL2, BIT(15) },
+	[SCU1_RESET_UART6]	= { true, SCU1_RESET_CTRL2, BIT(16) },
+	[SCU1_RESET_UART7]	= { true, SCU1_RESET_CTRL2, BIT(17) },
+	[SCU1_RESET_UART8]	= { true, SCU1_RESET_CTRL2, BIT(18) },
+	[SCU1_RESET_UART9]	= { true, SCU1_RESET_CTRL2, BIT(19) },
+	[SCU1_RESET_LTPI0]	= { true, SCU1_RESET_CTRL2, BIT(20) },
+	[SCU1_RESET_VGAL]	= { true, SCU1_RESET_CTRL2, BIT(21) },
+	[SCU1_RESET_LTPI1]	= { true, SCU1_RESET_CTRL2, BIT(22) },
+	[SCU1_RESET_ACE]	= { true, SCU1_RESET_CTRL2, BIT(23) },
+	[SCU1_RESET_E2M]	= { true, SCU1_RESET_CTRL2, BIT(24) },
+	[SCU1_RESET_UHCI]	= { true, SCU1_RESET_CTRL2, BIT(25) },
+	[SCU1_RESET_PORTC_USB2UART]	= { true, SCU1_RESET_CTRL2, BIT(26) },
+	[SCU1_RESET_PORTC_VHUB_EHCI]	= { true, SCU1_RESET_CTRL2, BIT(27) },
+	[SCU1_RESET_PORTD_USB2UART]	= { true, SCU1_RESET_CTRL2, BIT(28) },
+	[SCU1_RESET_PORTD_VHUB_EHCI]	= { true, SCU1_RESET_CTRL2, BIT(29) },
+	[SCU1_RESET_H2X]	= { true, SCU1_RESET_CTRL2, BIT(30) },
+	[SCU1_RESET_I3CDMA]	= { true, SCU1_RESET_CTRL2, BIT(31) },
+	[SCU1_RESET_PCIE2RST]	= { false, SCU1_PCIE3_CTRL, BIT(0) },
+};
+
+#define to_aspeed_reset(p) container_of(p, struct aspeed_reset, rcdev)
+
+static int aspeed_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+	struct aspeed_reset *rc = to_aspeed_reset(rcdev);
+	void __iomem *reg_offset = rc->base + rc->info->signal[id].offset;
+	unsigned long flags;
+
+	if (rc->info->signal[id].dedicated_clr) {
+		writel(rc->info->signal[id].bit, reg_offset);
+	} else {
+		spin_lock_irqsave(&rc->lock, flags);
+		writel(readl(reg_offset) & ~rc->info->signal[id].bit, reg_offset);
+		spin_unlock_irqrestore(&rc->lock, flags);
+	}
+
+	return 0;
+}
+
+static int aspeed_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+	struct aspeed_reset *rc = to_aspeed_reset(rcdev);
+	void __iomem *reg_offset = rc->base + rc->info->signal[id].offset;
+	unsigned long flags;
+
+	if (rc->info->signal[id].dedicated_clr) {
+		writel(rc->info->signal[id].bit, reg_offset + 0x04);
+	} else {
+		spin_lock_irqsave(&rc->lock, flags);
+		writel(readl(reg_offset) | rc->info->signal[id].bit, reg_offset);
+		spin_unlock_irqrestore(&rc->lock, flags);
+	}
+
+	return 0;
+}
+
+static int aspeed_reset_status(struct reset_controller_dev *rcdev, unsigned long id)
+{
+	struct aspeed_reset *rc = to_aspeed_reset(rcdev);
+	void __iomem *reg_offset = rc->base + rc->info->signal[id].offset;
+
+	return (readl(reg_offset) & rc->info->signal[id].bit) ? 1 : 0;
+}
+
+static const struct reset_control_ops aspeed_reset_ops = {
+	.assert = aspeed_reset_assert,
+	.deassert = aspeed_reset_deassert,
+	.status = aspeed_reset_status,
+};
+
+static int aspeed_reset_probe(struct auxiliary_device *adev,
+			      const struct auxiliary_device_id *id)
+{
+	struct aspeed_reset *reset;
+	struct device *dev = &adev->dev;
+
+	reset = devm_kzalloc(dev, sizeof(*reset), GFP_KERNEL);
+	if (!reset)
+		return -ENOMEM;
+
+	spin_lock_init(&reset->lock);
+
+	reset->info	= (struct aspeed_reset_info *)(id->driver_data);
+	reset->rcdev.owner     = THIS_MODULE;
+	reset->rcdev.nr_resets = reset->info->nr_resets;
+	reset->rcdev.ops       = &aspeed_reset_ops;
+	reset->rcdev.of_node   = dev->parent->of_node;
+	reset->rcdev.dev	      = dev;
+	reset->rcdev.of_reset_n_cells = 1;
+	reset->base            = (void __iomem *)adev->dev.platform_data;
+
+	if (!reset->base)
+		return -ENOMEM;
+
+	dev_set_drvdata(dev, reset);
+
+	return devm_reset_controller_register(dev, &reset->rcdev);
+}
+
+static const struct aspeed_reset_info ast2700_reset0_info = {
+	.nr_resets = ARRAY_SIZE(ast2700_reset0_signals),
+	.signal = ast2700_reset0_signals,
+};
+
+static const struct aspeed_reset_info ast2700_reset1_info = {
+	.nr_resets = ARRAY_SIZE(ast2700_reset1_signals),
+	.signal = ast2700_reset1_signals,
+};
+
+static const struct auxiliary_device_id aspeed_reset_ids[] = {
+	{ .name = "clk_ast2700.reset0", .driver_data = (kernel_ulong_t)&ast2700_reset0_info },
+	{ .name = "clk_ast2700.reset1", .driver_data = (kernel_ulong_t)&ast2700_reset1_info },
+	{ }
+};
+MODULE_DEVICE_TABLE(auxiliary, aspeed_reset_ids);
+
+static struct auxiliary_driver aspeed_reset_driver = {
+	.probe		= aspeed_reset_probe,
+	.id_table	= aspeed_reset_ids,
+};
+
+module_auxiliary_driver(aspeed_reset_driver);
+
+MODULE_AUTHOR("Ryan Chen <ryan_chen@aspeedtech.com>");
+MODULE_DESCRIPTION("ASPEED SoC Reset Controller Driver");
+MODULE_LICENSE("GPL");
-- 
2.34.1

Re: [PATCH v3 3/4] reset: aspeed: register AST2700 reset auxiliary bus device

[Christophe JAILLET]

Le 16/09/2024 à 11:10, Ryan Chen a écrit :
> The AST2700 reset driver is registered as an auxiliary device
> due to reset and clock controller share the same register region.
> 
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>

Hi,

...

> +static const struct ast2700_reset_signal ast2700_reset0_signals[] = {
> +	[SCU0_RESET_SDRAM] = { true, SCU0_RESET_CTRL1, BIT(0) },
> +	[SCU0_RESET_DDRPHY] = { true, SCU0_RESET_CTRL1, BIT(1) },
> +	[SCU0_RESET_RSA]     = { true, SCU0_RESET_CTRL1, BIT(2) },
> +	[SCU0_RESET_SHA3]	= { true, SCU0_RESET_CTRL1, BIT(3) },
> +	[SCU0_RESET_HACE]	= { true, SCU0_RESET_CTRL1, BIT(4) },
> +	[SCU0_RESET_SOC]	= { true, SCU0_RESET_CTRL1, BIT(5) },
> +	[SCU0_RESET_VIDEO]	= { true, SCU0_RESET_CTRL1, BIT(6) },
> +	[SCU0_RESET_2D]	= { true, SCU0_RESET_CTRL1, BIT(7) },
> +	[SCU0_RESET_PCIS]	= { true, SCU0_RESET_CTRL1, BIT(8) },
> +	[SCU0_RESET_RVAS0]		= { true, SCU0_RESET_CTRL1, BIT(9) },
> +	[SCU0_RESET_RVAS1]		= { true, SCU0_RESET_CTRL1, BIT(10) },
> +	[SCU0_RESET_SM3]		= { true, SCU0_RESET_CTRL1, BIT(11) },
> +	[SCU0_RESET_SM4]		= { true, SCU0_RESET_CTRL1, BIT(12) },
> +	[SCU0_RESET_CRT0]	= { true, SCU0_RESET_CTRL1, BIT(13) },
> +	[SCU0_RESET_ECC]	= { true, SCU0_RESET_CTRL1, BIT(14) },
> +	[SCU0_RESET_DP_PCI]	= { true, SCU0_RESET_CTRL1, BIT(15) },
> +	[SCU0_RESET_UFS]	= { true, SCU0_RESET_CTRL1, BIT(16) },
> +	[SCU0_RESET_EMMC]	= { true, SCU0_RESET_CTRL1, BIT(17) },
> +	[SCU0_RESET_PCIE1RST]	= { true, SCU0_RESET_CTRL1, BIT(18) },
> +	[SCU0_RESET_PCIE1RSTOE]	= { true, SCU0_RESET_CTRL1, BIT(19) },
> +	[SCU0_RESET_PCIE0RST]		= { true, SCU0_RESET_CTRL1, BIT(20) },
> +	[SCU0_RESET_PCIE0RSTOE]	= { true, SCU0_RESET_CTRL1, BIT(21) },
> +	[SCU0_RESET_JTAG]	= { true, SCU0_RESET_CTRL1, BIT(22) },
> +	[SCU0_RESET_MCTP0] = { true, SCU0_RESET_CTRL1, BIT(23) },
> +	[SCU0_RESET_MCTP1]		= { true, SCU0_RESET_CTRL1, BIT(24) },
> +	[SCU0_RESET_XDMA0]	= { true, SCU0_RESET_CTRL1, BIT(25) },
> +	[SCU0_RESET_XDMA1]	= { true, SCU0_RESET_CTRL1, BIT(26) },
> +	[SCU0_RESET_H2X1]	= { true, SCU0_RESET_CTRL1, BIT(27) },
> +	[SCU0_RESET_DP]	= { true, SCU0_RESET_CTRL1, BIT(28) },
> +	[SCU0_RESET_DP_MCU]	= { true, SCU0_RESET_CTRL1, BIT(29) },
> +	[SCU0_RESET_SSP]	= { true, SCU0_RESET_CTRL1, BIT(30) },
> +	[SCU0_RESET_H2X0]	= { true, SCU0_RESET_CTRL1, BIT(31) },
> +	[SCU0_RESET_PORTA_VHUB]	= { true, SCU0_RESET_CTRL2, BIT(0) },
> +	[SCU0_RESET_PORTA_PHY3]	= { true, SCU0_RESET_CTRL2, BIT(1) },
> +	[SCU0_RESET_PORTA_XHCI]	= { true, SCU0_RESET_CTRL2, BIT(2) },
> +	[SCU0_RESET_PORTB_VHUB]	= { true, SCU0_RESET_CTRL2, BIT(3) },
> +	[SCU0_RESET_PORTB_PHY3]	= { true, SCU0_RESET_CTRL2, BIT(4) },
> +	[SCU0_RESET_PORTB_XHCI]	= { true, SCU0_RESET_CTRL2, BIT(5) },
> +	[SCU0_RESET_PORTA_VHUB_EHCI]	= { true, SCU0_RESET_CTRL2, BIT(6) },
> +	[SCU0_RESET_PORTB_VHUB_EHCI]	= { true, SCU0_RESET_CTRL2, BIT(7) },
> +	[SCU0_RESET_UHCI]	= { true, SCU0_RESET_CTRL2, BIT(8) },
> +	[SCU0_RESET_TSP]	= { true, SCU0_RESET_CTRL2, BIT(9) },
> +	[SCU0_RESET_E2M0]	= { true, SCU0_RESET_CTRL2, BIT(10) },
> +	[SCU0_RESET_E2M1]	= { true, SCU0_RESET_CTRL2, BIT(11) },
> +	[SCU0_RESET_VLINK]	= { true, SCU0_RESET_CTRL2, BIT(12) },
> +};

The sapces and tabs in both tables look not consistent.

> +
> +static const struct ast2700_reset_signal ast2700_reset1_signals[] = {
> +	[SCU1_RESET_LPC0] = { true, SCU1_RESET_CTRL1, BIT(0) },
> +	[SCU1_RESET_LPC1] = { true, SCU1_RESET_CTRL1, BIT(1) },
> +	[SCU1_RESET_MII]     = { true, SCU1_RESET_CTRL1, BIT(2) },
> +	[SCU1_RESET_PECI]	= { true, SCU1_RESET_CTRL1, BIT(3) },
> +	[SCU1_RESET_PWM]	= { true, SCU1_RESET_CTRL1, BIT(4) },
> +	[SCU1_RESET_MAC0]	= { true, SCU1_RESET_CTRL1, BIT(5) },
> +	[SCU1_RESET_MAC1]	= { true, SCU1_RESET_CTRL1, BIT(6) },
> +	[SCU1_RESET_MAC2]	= { true, SCU1_RESET_CTRL1, BIT(7) },
> +	[SCU1_RESET_ADC]	= { true, SCU1_RESET_CTRL1, BIT(8) },
> +	[SCU1_RESET_SD]		= { true, SCU1_RESET_CTRL1, BIT(9) },
> +	[SCU1_RESET_ESPI0]		= { true, SCU1_RESET_CTRL1, BIT(10) },
> +	[SCU1_RESET_ESPI1]		= { true, SCU1_RESET_CTRL1, BIT(11) },
> +	[SCU1_RESET_JTAG1]		= { true, SCU1_RESET_CTRL1, BIT(12) },
> +	[SCU1_RESET_SPI0]	= { true, SCU1_RESET_CTRL1, BIT(13) },
> +	[SCU1_RESET_SPI1]	= { true, SCU1_RESET_CTRL1, BIT(14) },
> +	[SCU1_RESET_SPI2]	= { true, SCU1_RESET_CTRL1, BIT(15) },
> +	[SCU1_RESET_I3C0]	= { true, SCU1_RESET_CTRL1, BIT(16) },
> +	[SCU1_RESET_I3C1]	= { true, SCU1_RESET_CTRL1, BIT(17) },
> +	[SCU1_RESET_I3C2]	= { true, SCU1_RESET_CTRL1, BIT(18) },
> +	[SCU1_RESET_I3C3]	= { true, SCU1_RESET_CTRL1, BIT(19) },
> +	[SCU1_RESET_I3C4]		= { true, SCU1_RESET_CTRL1, BIT(20) },
> +	[SCU1_RESET_I3C5]	= { true, SCU1_RESET_CTRL1, BIT(21) },
> +	[SCU1_RESET_I3C6]	= { true, SCU1_RESET_CTRL1, BIT(22) },
> +	[SCU1_RESET_I3C7] = { true, SCU1_RESET_CTRL1, BIT(23) },
> +	[SCU1_RESET_I3C8]		= { true, SCU1_RESET_CTRL1, BIT(24) },
> +	[SCU1_RESET_I3C9]	= { true, SCU1_RESET_CTRL1, BIT(25) },
> +	[SCU1_RESET_I3C10]	= { true, SCU1_RESET_CTRL1, BIT(26) },
> +	[SCU1_RESET_I3C11]	= { true, SCU1_RESET_CTRL1, BIT(27) },
> +	[SCU1_RESET_I3C12]	= { true, SCU1_RESET_CTRL1, BIT(28) },
> +	[SCU1_RESET_I3C13]	= { true, SCU1_RESET_CTRL1, BIT(29) },
> +	[SCU1_RESET_I3C14]	= { true, SCU1_RESET_CTRL1, BIT(30) },
> +	[SCU1_RESET_I3C15]	= { true, SCU1_RESET_CTRL1, BIT(31) },
> +	[SCU1_RESET_MCU0]	= { true, SCU1_RESET_CTRL2, BIT(0) },
> +	[SCU1_RESET_MCU1]	= { true, SCU1_RESET_CTRL2, BIT(1) },
> +	[SCU1_RESET_H2A_SPI1]	= { true, SCU1_RESET_CTRL2, BIT(2) },
> +	[SCU1_RESET_H2A_SPI2]	= { true, SCU1_RESET_CTRL2, BIT(3) },
> +	[SCU1_RESET_UART0]	= { true, SCU1_RESET_CTRL2, BIT(4) },
> +	[SCU1_RESET_UART1]	= { true, SCU1_RESET_CTRL2, BIT(5) },
> +	[SCU1_RESET_UART2]	= { true, SCU1_RESET_CTRL2, BIT(6) },
> +	[SCU1_RESET_UART3]	= { true, SCU1_RESET_CTRL2, BIT(7) },
> +	[SCU1_RESET_I2C_FILTER]	= { true, SCU1_RESET_CTRL2, BIT(8) },
> +	[SCU1_RESET_CALIPTRA]	= { true, SCU1_RESET_CTRL2, BIT(9) },
> +	[SCU1_RESET_XDMA]	= { true, SCU1_RESET_CTRL2, BIT(10) },
> +	[SCU1_RESET_FSI]	= { true, SCU1_RESET_CTRL2, BIT(12) },
> +	[SCU1_RESET_CAN]	= { true, SCU1_RESET_CTRL2, BIT(13) },
> +	[SCU1_RESET_MCTP]	= { true, SCU1_RESET_CTRL2, BIT(14) },
> +	[SCU1_RESET_I2C]	= { true, SCU1_RESET_CTRL2, BIT(15) },
> +	[SCU1_RESET_UART6]	= { true, SCU1_RESET_CTRL2, BIT(16) },
> +	[SCU1_RESET_UART7]	= { true, SCU1_RESET_CTRL2, BIT(17) },
> +	[SCU1_RESET_UART8]	= { true, SCU1_RESET_CTRL2, BIT(18) },
> +	[SCU1_RESET_UART9]	= { true, SCU1_RESET_CTRL2, BIT(19) },
> +	[SCU1_RESET_LTPI0]	= { true, SCU1_RESET_CTRL2, BIT(20) },
> +	[SCU1_RESET_VGAL]	= { true, SCU1_RESET_CTRL2, BIT(21) },
> +	[SCU1_RESET_LTPI1]	= { true, SCU1_RESET_CTRL2, BIT(22) },
> +	[SCU1_RESET_ACE]	= { true, SCU1_RESET_CTRL2, BIT(23) },
> +	[SCU1_RESET_E2M]	= { true, SCU1_RESET_CTRL2, BIT(24) },
> +	[SCU1_RESET_UHCI]	= { true, SCU1_RESET_CTRL2, BIT(25) },
> +	[SCU1_RESET_PORTC_USB2UART]	= { true, SCU1_RESET_CTRL2, BIT(26) },
> +	[SCU1_RESET_PORTC_VHUB_EHCI]	= { true, SCU1_RESET_CTRL2, BIT(27) },
> +	[SCU1_RESET_PORTD_USB2UART]	= { true, SCU1_RESET_CTRL2, BIT(28) },
> +	[SCU1_RESET_PORTD_VHUB_EHCI]	= { true, SCU1_RESET_CTRL2, BIT(29) },
> +	[SCU1_RESET_H2X]	= { true, SCU1_RESET_CTRL2, BIT(30) },
> +	[SCU1_RESET_I3CDMA]	= { true, SCU1_RESET_CTRL2, BIT(31) },
> +	[SCU1_RESET_PCIE2RST]	= { false, SCU1_PCIE3_CTRL, BIT(0) },
> +};

...

> +static int aspeed_reset_probe(struct auxiliary_device *adev,
> +			      const struct auxiliary_device_id *id)
> +{
> +	struct aspeed_reset *reset;
> +	struct device *dev = &adev->dev;
> +
> +	reset = devm_kzalloc(dev, sizeof(*reset), GFP_KERNEL);
> +	if (!reset)
> +		return -ENOMEM;
> +
> +	spin_lock_init(&reset->lock);
> +
> +	reset->info	= (struct aspeed_reset_info *)(id->driver_data);
> +	reset->rcdev.owner     = THIS_MODULE;
> +	reset->rcdev.nr_resets = reset->info->nr_resets;
> +	reset->rcdev.ops       = &aspeed_reset_ops;
> +	reset->rcdev.of_node   = dev->parent->of_node;
> +	reset->rcdev.dev	      = dev;
> +	reset->rcdev.of_reset_n_cells = 1;
> +	reset->base            = (void __iomem *)adev->dev.platform_data;

The spaces and tabs look broken for 'info' and 'rcdev.dev'.

> +
> +	if (!reset->base)
> +		return -ENOMEM;
> +
> +	dev_set_drvdata(dev, reset);

Is it needed?
(there is no dev_get_drvdata())

> +
> +	return devm_reset_controller_register(dev, &reset->rcdev);
> +}

...

CJ

RE: [PATCH v3 3/4] reset: aspeed: register AST2700 reset auxiliary bus device

[Ryan Chen]

> Subject: Re: [PATCH v3 3/4] reset: aspeed: register AST2700 reset auxiliary bus
> device
> 
> Le 16/09/2024 à 11:10, Ryan Chen a écrit :
> > The AST2700 reset driver is registered as an auxiliary device due to
> > reset and clock controller share the same register region.
> >
> > Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> 
> Hi,
> 
> ...
> 
> > +static const struct ast2700_reset_signal ast2700_reset0_signals[] = {
> > +	[SCU0_RESET_SDRAM] = { true, SCU0_RESET_CTRL1, BIT(0) },
> > +	[SCU0_RESET_DDRPHY] = { true, SCU0_RESET_CTRL1, BIT(1) },
> > +	[SCU0_RESET_RSA]     = { true, SCU0_RESET_CTRL1, BIT(2) },
> > +	[SCU0_RESET_SHA3]	= { true, SCU0_RESET_CTRL1, BIT(3) },
> > +	[SCU0_RESET_HACE]	= { true, SCU0_RESET_CTRL1, BIT(4) },
> > +	[SCU0_RESET_SOC]	= { true, SCU0_RESET_CTRL1, BIT(5) },
> > +	[SCU0_RESET_VIDEO]	= { true, SCU0_RESET_CTRL1, BIT(6) },
> > +	[SCU0_RESET_2D]	= { true, SCU0_RESET_CTRL1, BIT(7) },
> > +	[SCU0_RESET_PCIS]	= { true, SCU0_RESET_CTRL1, BIT(8) },
> > +	[SCU0_RESET_RVAS0]		= { true, SCU0_RESET_CTRL1, BIT(9) },
> > +	[SCU0_RESET_RVAS1]		= { true, SCU0_RESET_CTRL1, BIT(10) },
> > +	[SCU0_RESET_SM3]		= { true, SCU0_RESET_CTRL1, BIT(11) },
> > +	[SCU0_RESET_SM4]		= { true, SCU0_RESET_CTRL1, BIT(12) },
> > +	[SCU0_RESET_CRT0]	= { true, SCU0_RESET_CTRL1, BIT(13) },
> > +	[SCU0_RESET_ECC]	= { true, SCU0_RESET_CTRL1, BIT(14) },
> > +	[SCU0_RESET_DP_PCI]	= { true, SCU0_RESET_CTRL1, BIT(15) },
> > +	[SCU0_RESET_UFS]	= { true, SCU0_RESET_CTRL1, BIT(16) },
> > +	[SCU0_RESET_EMMC]	= { true, SCU0_RESET_CTRL1, BIT(17) },
> > +	[SCU0_RESET_PCIE1RST]	= { true, SCU0_RESET_CTRL1, BIT(18) },
> > +	[SCU0_RESET_PCIE1RSTOE]	= { true, SCU0_RESET_CTRL1, BIT(19) },
> > +	[SCU0_RESET_PCIE0RST]		= { true, SCU0_RESET_CTRL1, BIT(20) },
> > +	[SCU0_RESET_PCIE0RSTOE]	= { true, SCU0_RESET_CTRL1, BIT(21) },
> > +	[SCU0_RESET_JTAG]	= { true, SCU0_RESET_CTRL1, BIT(22) },
> > +	[SCU0_RESET_MCTP0] = { true, SCU0_RESET_CTRL1, BIT(23) },
> > +	[SCU0_RESET_MCTP1]		= { true, SCU0_RESET_CTRL1, BIT(24) },
> > +	[SCU0_RESET_XDMA0]	= { true, SCU0_RESET_CTRL1, BIT(25) },
> > +	[SCU0_RESET_XDMA1]	= { true, SCU0_RESET_CTRL1, BIT(26) },
> > +	[SCU0_RESET_H2X1]	= { true, SCU0_RESET_CTRL1, BIT(27) },
> > +	[SCU0_RESET_DP]	= { true, SCU0_RESET_CTRL1, BIT(28) },
> > +	[SCU0_RESET_DP_MCU]	= { true, SCU0_RESET_CTRL1, BIT(29) },
> > +	[SCU0_RESET_SSP]	= { true, SCU0_RESET_CTRL1, BIT(30) },
> > +	[SCU0_RESET_H2X0]	= { true, SCU0_RESET_CTRL1, BIT(31) },
> > +	[SCU0_RESET_PORTA_VHUB]	= { true, SCU0_RESET_CTRL2, BIT(0) },
> > +	[SCU0_RESET_PORTA_PHY3]	= { true, SCU0_RESET_CTRL2, BIT(1) },
> > +	[SCU0_RESET_PORTA_XHCI]	= { true, SCU0_RESET_CTRL2, BIT(2) },
> > +	[SCU0_RESET_PORTB_VHUB]	= { true, SCU0_RESET_CTRL2, BIT(3) },
> > +	[SCU0_RESET_PORTB_PHY3]	= { true, SCU0_RESET_CTRL2, BIT(4) },
> > +	[SCU0_RESET_PORTB_XHCI]	= { true, SCU0_RESET_CTRL2, BIT(5) },
> > +	[SCU0_RESET_PORTA_VHUB_EHCI]	= { true, SCU0_RESET_CTRL2,
> BIT(6) },
> > +	[SCU0_RESET_PORTB_VHUB_EHCI]	= { true, SCU0_RESET_CTRL2,
> BIT(7) },
> > +	[SCU0_RESET_UHCI]	= { true, SCU0_RESET_CTRL2, BIT(8) },
> > +	[SCU0_RESET_TSP]	= { true, SCU0_RESET_CTRL2, BIT(9) },
> > +	[SCU0_RESET_E2M0]	= { true, SCU0_RESET_CTRL2, BIT(10) },
> > +	[SCU0_RESET_E2M1]	= { true, SCU0_RESET_CTRL2, BIT(11) },
> > +	[SCU0_RESET_VLINK]	= { true, SCU0_RESET_CTRL2, BIT(12) },
> > +};
> 
> The sapces and tabs in both tables look not consistent.
Will update.

> 
> > +
> > +static const struct ast2700_reset_signal ast2700_reset1_signals[] = {
> > +	[SCU1_RESET_LPC0] = { true, SCU1_RESET_CTRL1, BIT(0) },
> > +	[SCU1_RESET_LPC1] = { true, SCU1_RESET_CTRL1, BIT(1) },
> > +	[SCU1_RESET_MII]     = { true, SCU1_RESET_CTRL1, BIT(2) },
> > +	[SCU1_RESET_PECI]	= { true, SCU1_RESET_CTRL1, BIT(3) },
> > +	[SCU1_RESET_PWM]	= { true, SCU1_RESET_CTRL1, BIT(4) },
> > +	[SCU1_RESET_MAC0]	= { true, SCU1_RESET_CTRL1, BIT(5) },
> > +	[SCU1_RESET_MAC1]	= { true, SCU1_RESET_CTRL1, BIT(6) },
> > +	[SCU1_RESET_MAC2]	= { true, SCU1_RESET_CTRL1, BIT(7) },
> > +	[SCU1_RESET_ADC]	= { true, SCU1_RESET_CTRL1, BIT(8) },
> > +	[SCU1_RESET_SD]		= { true, SCU1_RESET_CTRL1, BIT(9) },
> > +	[SCU1_RESET_ESPI0]		= { true, SCU1_RESET_CTRL1, BIT(10) },
> > +	[SCU1_RESET_ESPI1]		= { true, SCU1_RESET_CTRL1, BIT(11) },
> > +	[SCU1_RESET_JTAG1]		= { true, SCU1_RESET_CTRL1, BIT(12) },
> > +	[SCU1_RESET_SPI0]	= { true, SCU1_RESET_CTRL1, BIT(13) },
> > +	[SCU1_RESET_SPI1]	= { true, SCU1_RESET_CTRL1, BIT(14) },
> > +	[SCU1_RESET_SPI2]	= { true, SCU1_RESET_CTRL1, BIT(15) },
> > +	[SCU1_RESET_I3C0]	= { true, SCU1_RESET_CTRL1, BIT(16) },
> > +	[SCU1_RESET_I3C1]	= { true, SCU1_RESET_CTRL1, BIT(17) },
> > +	[SCU1_RESET_I3C2]	= { true, SCU1_RESET_CTRL1, BIT(18) },
> > +	[SCU1_RESET_I3C3]	= { true, SCU1_RESET_CTRL1, BIT(19) },
> > +	[SCU1_RESET_I3C4]		= { true, SCU1_RESET_CTRL1, BIT(20) },
> > +	[SCU1_RESET_I3C5]	= { true, SCU1_RESET_CTRL1, BIT(21) },
> > +	[SCU1_RESET_I3C6]	= { true, SCU1_RESET_CTRL1, BIT(22) },
> > +	[SCU1_RESET_I3C7] = { true, SCU1_RESET_CTRL1, BIT(23) },
> > +	[SCU1_RESET_I3C8]		= { true, SCU1_RESET_CTRL1, BIT(24) },
> > +	[SCU1_RESET_I3C9]	= { true, SCU1_RESET_CTRL1, BIT(25) },
> > +	[SCU1_RESET_I3C10]	= { true, SCU1_RESET_CTRL1, BIT(26) },
> > +	[SCU1_RESET_I3C11]	= { true, SCU1_RESET_CTRL1, BIT(27) },
> > +	[SCU1_RESET_I3C12]	= { true, SCU1_RESET_CTRL1, BIT(28) },
> > +	[SCU1_RESET_I3C13]	= { true, SCU1_RESET_CTRL1, BIT(29) },
> > +	[SCU1_RESET_I3C14]	= { true, SCU1_RESET_CTRL1, BIT(30) },
> > +	[SCU1_RESET_I3C15]	= { true, SCU1_RESET_CTRL1, BIT(31) },
> > +	[SCU1_RESET_MCU0]	= { true, SCU1_RESET_CTRL2, BIT(0) },
> > +	[SCU1_RESET_MCU1]	= { true, SCU1_RESET_CTRL2, BIT(1) },
> > +	[SCU1_RESET_H2A_SPI1]	= { true, SCU1_RESET_CTRL2, BIT(2) },
> > +	[SCU1_RESET_H2A_SPI2]	= { true, SCU1_RESET_CTRL2, BIT(3) },
> > +	[SCU1_RESET_UART0]	= { true, SCU1_RESET_CTRL2, BIT(4) },
> > +	[SCU1_RESET_UART1]	= { true, SCU1_RESET_CTRL2, BIT(5) },
> > +	[SCU1_RESET_UART2]	= { true, SCU1_RESET_CTRL2, BIT(6) },
> > +	[SCU1_RESET_UART3]	= { true, SCU1_RESET_CTRL2, BIT(7) },
> > +	[SCU1_RESET_I2C_FILTER]	= { true, SCU1_RESET_CTRL2, BIT(8) },
> > +	[SCU1_RESET_CALIPTRA]	= { true, SCU1_RESET_CTRL2, BIT(9) },
> > +	[SCU1_RESET_XDMA]	= { true, SCU1_RESET_CTRL2, BIT(10) },
> > +	[SCU1_RESET_FSI]	= { true, SCU1_RESET_CTRL2, BIT(12) },
> > +	[SCU1_RESET_CAN]	= { true, SCU1_RESET_CTRL2, BIT(13) },
> > +	[SCU1_RESET_MCTP]	= { true, SCU1_RESET_CTRL2, BIT(14) },
> > +	[SCU1_RESET_I2C]	= { true, SCU1_RESET_CTRL2, BIT(15) },
> > +	[SCU1_RESET_UART6]	= { true, SCU1_RESET_CTRL2, BIT(16) },
> > +	[SCU1_RESET_UART7]	= { true, SCU1_RESET_CTRL2, BIT(17) },
> > +	[SCU1_RESET_UART8]	= { true, SCU1_RESET_CTRL2, BIT(18) },
> > +	[SCU1_RESET_UART9]	= { true, SCU1_RESET_CTRL2, BIT(19) },
> > +	[SCU1_RESET_LTPI0]	= { true, SCU1_RESET_CTRL2, BIT(20) },
> > +	[SCU1_RESET_VGAL]	= { true, SCU1_RESET_CTRL2, BIT(21) },
> > +	[SCU1_RESET_LTPI1]	= { true, SCU1_RESET_CTRL2, BIT(22) },
> > +	[SCU1_RESET_ACE]	= { true, SCU1_RESET_CTRL2, BIT(23) },
> > +	[SCU1_RESET_E2M]	= { true, SCU1_RESET_CTRL2, BIT(24) },
> > +	[SCU1_RESET_UHCI]	= { true, SCU1_RESET_CTRL2, BIT(25) },
> > +	[SCU1_RESET_PORTC_USB2UART]	= { true, SCU1_RESET_CTRL2,
> BIT(26) },
> > +	[SCU1_RESET_PORTC_VHUB_EHCI]	= { true, SCU1_RESET_CTRL2,
> BIT(27) },
> > +	[SCU1_RESET_PORTD_USB2UART]	= { true, SCU1_RESET_CTRL2,
> BIT(28) },
> > +	[SCU1_RESET_PORTD_VHUB_EHCI]	= { true, SCU1_RESET_CTRL2,
> BIT(29) },
> > +	[SCU1_RESET_H2X]	= { true, SCU1_RESET_CTRL2, BIT(30) },
> > +	[SCU1_RESET_I3CDMA]	= { true, SCU1_RESET_CTRL2, BIT(31) },
> > +	[SCU1_RESET_PCIE2RST]	= { false, SCU1_PCIE3_CTRL, BIT(0) },
> > +};
> 
> ...
> 
> > +static int aspeed_reset_probe(struct auxiliary_device *adev,
> > +			      const struct auxiliary_device_id *id) {
> > +	struct aspeed_reset *reset;
> > +	struct device *dev = &adev->dev;
> > +
> > +	reset = devm_kzalloc(dev, sizeof(*reset), GFP_KERNEL);
> > +	if (!reset)
> > +		return -ENOMEM;
> > +
> > +	spin_lock_init(&reset->lock);
> > +
> > +	reset->info	= (struct aspeed_reset_info *)(id->driver_data);
> > +	reset->rcdev.owner     = THIS_MODULE;
> > +	reset->rcdev.nr_resets = reset->info->nr_resets;
> > +	reset->rcdev.ops       = &aspeed_reset_ops;
> > +	reset->rcdev.of_node   = dev->parent->of_node;
> > +	reset->rcdev.dev	      = dev;
> > +	reset->rcdev.of_reset_n_cells = 1;
> > +	reset->base            = (void __iomem *)adev->dev.platform_data;
> 
> The spaces and tabs look broken for 'info' and 'rcdev.dev'.
Will update by spaces.
> 
> > +
> > +	if (!reset->base)
> > +		return -ENOMEM;
> > +
> > +	dev_set_drvdata(dev, reset);
> 
> Is it needed?
> (there is no dev_get_drvdata())

No need, will remove.
> 
> > +
> > +	return devm_reset_controller_register(dev, &reset->rcdev); }
> 
> ...
> 
> CJ

[PATCH v3 4/4] clk: aspeed: add AST2700 clock driver.

[Ryan Chen]

Add AST2700 clock controller driver and also use axiliary
device framework register the reset controller driver.
Due to clock and reset using the same register region.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
 drivers/clk/Kconfig       |    8 +
 drivers/clk/Makefile      |    1 +
 drivers/clk/clk-ast2700.c | 1548 +++++++++++++++++++++++++++++++++++++
 3 files changed, 1557 insertions(+)
 create mode 100644 drivers/clk/clk-ast2700.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 983ef4f36d8c..4cc35ecba1c0 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -269,6 +269,14 @@ config COMMON_CLK_ASPEED
 	  The G4 and G5 series, including the ast2400 and ast2500, are supported
 	  by this driver.
 
+config COMMON_CLK_AST2700
+	bool "Clock driver for AST2700 SoC"
+	depends on ARCH_ASPEED || COMPILE_TEST
+	help
+	  This driver provides support for clock on AST2700 SoC.
+	  The driver is responsible for managing the various clocks required
+	  by the peripherals and cores within the AST2700.
+
 config COMMON_CLK_S2MPS11
 	tristate "Clock driver for S2MPS1X/S5M8767 MFD"
 	depends on MFD_SEC_CORE || COMPILE_TEST
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index f793a16cad40..fe95203c3138 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_COMMON_CLK_FSL_SAI)	+= clk-fsl-sai.o
 obj-$(CONFIG_COMMON_CLK_GEMINI)		+= clk-gemini.o
 obj-$(CONFIG_COMMON_CLK_ASPEED)		+= clk-aspeed.o
 obj-$(CONFIG_MACH_ASPEED_G6)		+= clk-ast2600.o
+obj-$(CONFIG_COMMON_CLK_AST2700)	+= clk-ast2700.o
 obj-$(CONFIG_ARCH_HIGHBANK)		+= clk-highbank.o
 obj-$(CONFIG_CLK_HSDK)			+= clk-hsdk-pll.o
 obj-$(CONFIG_COMMON_CLK_K210)		+= clk-k210.o
diff --git a/drivers/clk/clk-ast2700.c b/drivers/clk/clk-ast2700.c
new file mode 100644
index 000000000000..a0bafb87b4ac
--- /dev/null
+++ b/drivers/clk/clk-ast2700.c
@@ -0,0 +1,1548 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 ASPEED Technology Inc.
+ * Author: Ryan Chen <ryan_chen@aspeedtech.com>
+ */
+
+#include <linux/auxiliary_bus.h>
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/clock/aspeed,ast2700-clk.h>
+
+#define SCU_CLK_12MHZ 12000000
+#define SCU_CLK_24MHZ 24000000
+#define SCU_CLK_25MHZ 25000000
+#define SCU_CLK_192MHZ 192000000
+
+/* SOC0 */
+#define SCU0_HWSTRAP1 0x010
+#define SCU0_CLK_STOP 0x240
+#define SCU0_CLK_SEL1 0x280
+#define SCU0_CLK_SEL2 0x284
+#define GET_USB_REFCLK_DIV(x) ((GENMASK(23, 20) & (x)) >> 20)
+#define UART_DIV13_EN BIT(30)
+#define SCU0_HPLL_PARAM 0x300
+#define SCU0_DPLL_PARAM 0x308
+#define SCU0_MPLL_PARAM 0x310
+#define SCU0_D0CLK_PARAM 0x320
+#define SCU0_D1CLK_PARAM 0x330
+#define SCU0_CRT0CLK_PARAM 0x340
+#define SCU0_CRT1CLK_PARAM 0x350
+#define SCU0_MPHYCLK_PARAM 0x360
+
+/* SOC1 */
+#define SCU1_REVISION_ID 0x0
+#define REVISION_ID GENMASK(23, 16)
+#define SCU1_CLK_STOP 0x240
+#define SCU1_CLK_STOP2 0x260
+#define SCU1_CLK_SEL1 0x280
+#define SCU1_CLK_SEL2 0x284
+#define UXCLK_MASK GENMASK(1, 0)
+#define HUXCLK_MASK GENMASK(4, 3)
+#define SCU1_HPLL_PARAM 0x300
+#define SCU1_APLL_PARAM 0x310
+#define SCU1_DPLL_PARAM 0x320
+#define SCU1_UXCLK_CTRL 0x330
+#define SCU1_HUXCLK_CTRL 0x334
+#define SCU1_MAC12_CLK_DLY 0x390
+#define SCU1_MAC12_CLK_DLY_100M 0x394
+#define SCU1_MAC12_CLK_DLY_10M 0x398
+
+enum {
+	CLK_MUX,
+	CLK_PLL,
+	CLK_GATE,
+	CLK_MISC,
+	CLK_FIXED,
+	CLK_DIVIDER,
+	CLK_UART_PLL,
+	CLK_DIV_TABLE,
+	CLK_FIXED_FACTOR,
+};
+
+struct ast2700_clk_info {
+	const char *name;
+	const char * const *parent_names;
+	const struct clk_div_table *div_table;
+	unsigned long fixed_rate;
+	unsigned int mult;
+	unsigned int div;
+	u32 reg;
+	u32 flags;
+	u32 type;
+	u8 clk_idx;
+	u8 bit_shift;
+	u8 bit_width;
+	u8 num_parents;
+};
+
+struct ast2700_clk_data {
+	struct ast2700_clk_info const *clk_info;
+	const char	*reset_name;
+	unsigned int nr_clks;
+};
+
+struct ast2700_clk_ctrl {
+	const struct ast2700_clk_data *clk_data;
+	struct device *dev;
+	void __iomem *base;
+	spinlock_t lock; /* clk lock */
+};
+
+static const struct clk_div_table ast2700_rgmii_div_table[] = {
+	{ 0x0, 4 },
+	{ 0x1, 4 },
+	{ 0x2, 6 },
+	{ 0x3, 8 },
+	{ 0x4, 10 },
+	{ 0x5, 12 },
+	{ 0x6, 14 },
+	{ 0x7, 16 },
+	{ 0 }
+};
+
+static const struct clk_div_table ast2700_rmii_div_table[] = {
+	{ 0x0, 8 },
+	{ 0x1, 8 },
+	{ 0x2, 12 },
+	{ 0x3, 16 },
+	{ 0x4, 20 },
+	{ 0x5, 24 },
+	{ 0x6, 28 },
+	{ 0x7, 32 },
+	{ 0 }
+};
+
+static const struct clk_div_table ast2700_clk_div_table[] = {
+	{ 0x0, 2 },
+	{ 0x1, 2 },
+	{ 0x2, 3 },
+	{ 0x3, 4 },
+	{ 0x4, 5 },
+	{ 0x5, 6 },
+	{ 0x6, 7 },
+	{ 0x7, 8 },
+	{ 0 }
+};
+
+static const struct clk_div_table ast2700_clk_div_table2[] = {
+	{ 0x0, 2 },
+	{ 0x1, 4 },
+	{ 0x2, 6 },
+	{ 0x3, 8 },
+	{ 0x4, 10 },
+	{ 0x5, 12 },
+	{ 0x6, 14 },
+	{ 0x7, 16 },
+	{ 0 }
+};
+
+static const struct clk_div_table ast2700_clk_uart_div_table[] = {
+	{ 0x0, 1 },
+	{ 0x1, 13 },
+	{ 0 }
+};
+
+static const struct ast2700_clk_info ast2700_scu0_clk_info[] __initconst = {
+	[SCU0_CLKIN] = {
+		.type = CLK_FIXED,
+		.name = "soc0-clkin",
+		.fixed_rate = SCU_CLK_25MHZ,
+	},
+	[SCU0_CLK_24M] = {
+		.type = CLK_FIXED,
+		.name = "soc0-clk24Mhz",
+		.fixed_rate = SCU_CLK_24MHZ,
+	},
+	[SCU0_CLK_192M] = {
+		.type = CLK_FIXED,
+		.name = "soc0-clk192Mhz",
+		.fixed_rate = SCU_CLK_192MHZ,
+	},
+	[SCU0_CLK_HPLL] = {
+		.type = CLK_PLL,
+		.name = "soc0-hpll",
+		.parent_names = (const char *[]){ "soc0-clkin", },
+		.reg = SCU0_HPLL_PARAM,
+	},
+	[SCU0_CLK_HPLL_DIV2] = {
+		.type = CLK_FIXED_FACTOR,
+		.name = "soc0-hpll_div2",
+		.parent_names = (const char *[]){ "soc0-hpll", },
+		.mult = 1,
+		.div = 2,
+	},
+	[SCU0_CLK_HPLL_DIV4] = {
+		.type = CLK_FIXED_FACTOR,
+		.name = "soc0-hpll_div4",
+		.parent_names = (const char *[]){ "soc0-hpll", },
+		.mult = 1,
+		.div = 4,
+	},
+	[SCU0_CLK_HPLL_DIV_AHB] = {
+		.type = CLK_DIV_TABLE,
+		.name = "soc0-hpll_div_ahb",
+		.parent_names = (const char *[]){ "soc0-hpll", },
+		.reg = SCU0_HWSTRAP1,
+		.bit_shift = 5,
+		.bit_width = 2,
+		.div_table = ast2700_clk_div_table,
+	},
+	[SCU0_CLK_DPLL] = {
+		.type = CLK_PLL,
+		.name = "dpll",
+		.parent_names = (const char *[]){ "soc0-clkin", },
+		.reg = SCU0_DPLL_PARAM,
+	},
+	[SCU0_CLK_MPLL] = {
+		.type = CLK_PLL,
+		.name = "soc0-mpll",
+		.parent_names = (const char *[]){ "soc0-clkin", },
+		.reg = SCU0_MPLL_PARAM,
+	},
+	[SCU0_CLK_MPLL_DIV2] = {
+		.type = CLK_FIXED_FACTOR,
+		.name = "soc0-mpll_div2",
+		.parent_names = (const char *[]){ "soc0-mpll", },
+		.mult = 1,
+		.div = 2,
+	},
+	[SCU0_CLK_MPLL_DIV4] = {
+		.type = CLK_FIXED_FACTOR,
+		.name = "soc0-mpll_div4",
+		.parent_names = (const char *[]){ "soc0-mpll", },
+		.mult = 1,
+		.div = 4,
+	},
+	[SCU0_CLK_MPLL_DIV8] = {
+		.type = CLK_FIXED_FACTOR,
+		.name = "soc0-mpll_div8",
+		.parent_names = (const char *[]){ "soc0-mpll", },
+		.mult = 1,
+		.div = 8,
+	},
+	[SCU0_CLK_MPLL_DIV_AHB] = {
+		.type = CLK_DIV_TABLE,
+		.name = "soc0-mpll_div_ahb",
+		.parent_names = (const char *[]){ "soc0-mpll", },
+		.reg = SCU0_HWSTRAP1,
+		.bit_shift = 5,
+		.bit_width = 2,
+		.div_table = ast2700_clk_div_table,
+	},
+	[SCU0_CLK_D0] = {
+		.type = CLK_PLL,
+		.name = "d0clk",
+		.parent_names = (const char *[]){ "soc0-clkin", },
+		.reg = SCU0_D0CLK_PARAM,
+	},
+	[SCU0_CLK_D1] = {
+		.type = CLK_PLL,
+		.name = "d1clk",
+		.parent_names = (const char *[]){ "soc0-clkin", },
+		.reg = SCU0_D1CLK_PARAM,
+	},
+	[SCU0_CLK_CRT0] = {
+		.type = CLK_PLL,
+		.name = "crt0clk",
+		.parent_names = (const char *[]){ "soc0-clkin", },
+		.reg = SCU0_CRT0CLK_PARAM,
+	},
+	[SCU0_CLK_CRT1] = {
+		.type = CLK_PLL,
+		.name = "crt1clk",
+		.parent_names = (const char *[]){ "soc0-clkin", },
+		.reg = SCU0_CRT1CLK_PARAM,
+	},
+	[SCU0_CLK_MPHY] = {
+		.type = CLK_MISC,
+		.name = "mphyclk",
+		.parent_names = (const char *[]){ "soc0-hpll", },
+		.reg = SCU0_MPHYCLK_PARAM,
+	},
+	[SCU0_CLK_PSP] = {
+		.type = CLK_MUX,
+		.name = "pspclk",
+		.parent_names = (const char *[]){"soc0-mpll", "soc0-hpll", },
+		.num_parents = 2,
+		.reg = SCU0_HWSTRAP1,
+		.bit_shift = 4,
+		.bit_width = 1,
+	},
+	[SCU0_CLK_AXI0] = {
+		.type = CLK_FIXED_FACTOR,
+		.name = "axi0clk",
+		.parent_names = (const char *[]){"pspclk", },
+		.mult = 1,
+		.div = 2,
+	},
+	[SCU0_CLK_AHB] = {
+		.type = CLK_MUX,
+		.name = "soc0-ahb",
+		.parent_names = (const char *[]){"soc0-mpll_div_ahb", "soc0-hspll_div_ahb", },
+		.num_parents = 2,
+		.reg = SCU0_HWSTRAP1,
+		.bit_shift = 7,
+		.bit_width = 1,
+	},
+	[SCU0_CLK_AXI1] = {
+		.type = CLK_FIXED_FACTOR,
+		.name = "axi1clk",
+		.parent_names = (const char *[]){ "soc0-ahb", },
+		.mult = 1,
+		.div = 2,
+	},
+	[SCU0_CLK_APB] = {
+		.type = CLK_DIV_TABLE,
+		.name = "soc0-apb",
+		.parent_names = (const char *[]){ "axi0clk", },
+		.reg = SCU0_CLK_SEL1,
+		.bit_shift = 23,
+		.bit_width = 3,
+		.div_table = ast2700_clk_div_table2,
+	},
+	[SCU0_CLK_GATE_MCLK] = {
+		.type = CLK_GATE,
+		.name = "mclk",
+		.parent_names = (const char *[]){ "soc0-mpll", },
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 0,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU0_CLK_GATE_ECLK] = {
+		.type = CLK_GATE,
+		.name = "eclk",
+		.parent_names = (const char *[]){  },
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 1,
+	},
+	[SCU0_CLK_GATE_2DCLK] = {
+		.type = CLK_GATE,
+		.name = "gclk",
+		.parent_names = (const char *[]){  },
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 2,
+	},
+	[SCU0_CLK_GATE_VCLK] = {
+		.type = CLK_GATE,
+		.name = "vclk",
+		.parent_names = (const char *[]){  },
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 3,
+	},
+	[SCU0_CLK_GATE_BCLK] = {
+		.type = CLK_GATE,
+		.name = "bclk",
+		.parent_names = (const char *[]){  },
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 4,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU0_CLK_GATE_VGA0CLK] = {
+		.type = CLK_GATE,
+		.name = "d1clk-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 5,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU0_CLK_GATE_REFCLK] = {
+		.type = CLK_GATE,
+		.name = "soc0-refclk-gate",
+		.parent_names = (const char *[]){ "soc0-clkin", },
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 6,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU0_CLK_U2PHY_REFCLK] = {
+		.type = CLK_MISC,
+		.name = "xhci_ref_clk",
+		.parent_names = (const char *[]){ "soc0-mpll_div8", },
+		.reg = SCU0_CLK_SEL2,
+	},
+	[SCU0_CLK_U2PHY_CLK12M] = {
+		.type = CLK_FIXED,
+		.name = "xhci_suspend_clk",
+		.parent_names = (const char *[]){  },
+		.fixed_rate = SCU_CLK_12MHZ,
+	},
+	[SCU0_CLK_GATE_PORTBUSB2CLK] = {
+		.type = CLK_GATE,
+		.name = "portb-usb2clk",
+		.parent_names = (const char *[]){  },
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 7,
+	},
+	[SCU0_CLK_GATE_UHCICLK] = {
+		.type = CLK_GATE,
+		.name = "uhciclk",
+		.parent_names = (const char *[]){  },
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 9,
+	},
+	[SCU0_CLK_GATE_VGA1CLK] = {
+		.type = CLK_GATE,
+		.name = "d2clk-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 10,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU0_CLK_GATE_DDRPHYCLK] = {
+		.type = CLK_GATE,
+		.name = "ddrphy-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 11,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU0_CLK_GATE_E2M0CLK] = {
+		.type = CLK_GATE,
+		.name = "e2m0clk-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 12,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU0_CLK_GATE_HACCLK] = {
+		.type = CLK_GATE,
+		.name = "hac-clk",
+		.parent_names = (const char *[]){  },
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 13,
+	},
+	[SCU0_CLK_GATE_PORTAUSB2CLK] = {
+		.type = CLK_GATE,
+		.name = "porta-usb2clk",
+		.parent_names = (const char *[]){  },
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 14,
+	},
+	[SCU0_CLK_UART] = {
+		.type = CLK_MUX,
+		.name = "soc0-uartclk",
+		.parent_names = (const char *[]){"soc0-clk24Mhz", "soc0-clk192Mhz", },
+		.num_parents = 2,
+		.reg = SCU0_CLK_SEL2,
+		.bit_shift = 14,
+		.bit_width = 1,
+	},
+	[SCU0_CLK_UART4] = {
+		.type = CLK_DIV_TABLE,
+		.name = "uart4clk",
+		.parent_names = (const char *[]){ "soc0-uartclk", },
+		.reg = SCU0_CLK_SEL2,
+		.bit_shift = 30,
+		.bit_width = 1,
+		.div_table = ast2700_clk_uart_div_table,
+	},
+	[SCU0_CLK_GATE_UART4CLK] = {
+		.type = CLK_GATE,
+		.name = "uart4clk-gate",
+		.parent_names = (const char *[]){"uart4clk" },
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 15,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU0_CLK_GATE_SLICLK] = {
+		.type = CLK_GATE,
+		.name = "soc0-sliclk-gate",
+		.parent_names = (const char *[]){	},
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 16,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU0_CLK_GATE_DACCLK] = {
+		.type = CLK_GATE,
+		.name = "dacclk-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 17,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU0_CLK_GATE_DP] = {
+		.type = CLK_GATE,
+		.name = "dpclk-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 18,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU0_CLK_GATE_E2M1CLK] = {
+		.type = CLK_GATE,
+		.name = "e2m1clk-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 19,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU0_CLK_GATE_CRT0CLK] = {
+		.type = CLK_GATE,
+		.name = "crt0clk-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 20,
+	},
+	[SCU0_CLK_GATE_CRT1CLK] = {
+		.type = CLK_GATE,
+		.name = "crt1clk-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 21,
+	},
+	[SCU0_CLK_GATE_ECDSACLK] = {
+		.type = CLK_GATE,
+		.name = "eccclk",
+		.parent_names = (const char *[]){  },
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 23,
+	},
+	[SCU0_CLK_GATE_RSACLK] = {
+		.type = CLK_GATE,
+		.name = "rsaclk",
+		.parent_names = (const char *[]){  },
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 24,
+	},
+	[SCU0_CLK_GATE_RVAS0CLK] = {
+		.type = CLK_GATE,
+		.name = "rvasclk",
+		.parent_names = (const char *[]){  },
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 25,
+	},
+	[SCU0_CLK_GATE_UFSCLK] = {
+		.type = CLK_GATE,
+		.name = "ufsclk",
+		.parent_names = (const char *[]){  },
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 26,
+	},
+	[SCU0_CLK_EMMCMUX] = {
+		.type = CLK_MUX,
+		.name = "emmcsrc-mux",
+		.parent_names = (const char *[]){"soc0-mpll_div4", "soc0-hpll_div4", },
+		.num_parents = 2,
+		.reg = SCU0_CLK_SEL1,
+		.bit_shift = 11,
+		.bit_width = 1,
+	},
+	[SCU0_CLK_EMMC] = {
+		.type = CLK_DIV_TABLE,
+		.name = "emmcclk",
+		.parent_names = (const char *[]){ "emmcsrc-mux", },
+		.reg = SCU0_CLK_SEL1,
+		.bit_shift = 12,
+		.bit_width = 3,
+		.div_table = ast2700_clk_div_table2,
+	},
+	[SCU0_CLK_GATE_EMMCCLK] = {
+		.type = CLK_GATE,
+		.name = "emmcclk-gate",
+		.parent_names = (const char *[]){ "emmcclk", },
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 27,
+	},
+	[SCU0_CLK_GATE_RVAS1CLK] = {
+		.type = CLK_GATE,
+		.name = "rvas2clk",
+		.parent_names = (const char *[]){ "emmcclk", },
+		.reg = SCU0_CLK_STOP,
+		.clk_idx = 28,
+	},
+};
+
+static const struct ast2700_clk_info ast2700_scu1_clk_info[] __initconst = {
+	[SCU1_CLKIN] = {
+		.type = CLK_FIXED,
+		.name = "soc1-clkin",
+		.fixed_rate = SCU_CLK_25MHZ,
+	},
+	[SCU1_CLK_HPLL] = {
+		.type = CLK_PLL,
+		.name = "soc1-hpll",
+		.parent_names = (const char *[]){ "soc1-clkin", },
+		.reg = SCU1_HPLL_PARAM,
+	},
+	[SCU1_CLK_APLL] = {
+		.type = CLK_PLL,
+		.name = "soc1-apll",
+		.parent_names = (const char *[]){ "soc1-clkin", },
+		.reg = SCU1_APLL_PARAM,
+	},
+	[SCU1_CLK_APLL_DIV2] = {
+		.type = CLK_FIXED_FACTOR,
+		.name = "soc1-apll_div2",
+		.parent_names = (const char *[]){ "soc1-apll", },
+		.mult = 1,
+		.div = 2,
+	},
+	[SCU1_CLK_APLL_DIV4] = {
+		.type = CLK_FIXED_FACTOR,
+		.name = "soc1-apll_div4",
+		.parent_names = (const char *[]){ "soc1-apll", },
+		.mult = 1,
+		.div = 4,
+	},
+	[SCU1_CLK_DPLL] = {
+		.type = CLK_PLL,
+		.name = "soc1-dpll",
+		.parent_names = (const char *[]){ "soc1-clkin", },
+		.reg = SCU1_DPLL_PARAM,
+	},
+	[SCU1_CLK_UXCLK] = {
+		.type = CLK_MUX,
+		.name = "uxclk",
+		.parent_names = (const char *[]){ "soc1-apll_div4", "soc1-apll_div2",
+						 "soc1-apll", "soc1-hpll",},
+		.num_parents = 4,
+		.reg = SCU1_CLK_SEL2,
+		.bit_shift = 0,
+		.bit_width = 2,
+	},
+	[SCU1_CLK_UARTX] = {
+		.type = CLK_UART_PLL,
+		.name = "uartxclk",
+		.parent_names = (const char *[]){ "uxclk", },
+		.reg = SCU1_UXCLK_CTRL,
+	},
+	[SCU1_CLK_HUXCLK] = {
+		.type = CLK_MUX,
+		.name = "huxclk",
+		.parent_names = (const char *[]){"soc1-apll_div4", "soc1-apll_div2",
+						 "soc1-apll", "soc1-hpll",},
+		.num_parents = 4,
+		.reg = SCU1_CLK_SEL2,
+		.bit_shift = 3,
+		.bit_width = 2,
+	},
+	[SCU1_CLK_HUARTX] = {
+		.type = CLK_UART_PLL,
+		.name = "huartxclk",
+		.parent_names = (const char *[]){ "huxclk", },
+		.reg = SCU1_HUXCLK_CTRL,
+	},
+	[SCU1_CLK_AHB] = {
+		.type = CLK_DIV_TABLE,
+		.name = "soc1-ahb",
+		.parent_names = (const char *[]){"soc1-hpll", },
+		.reg = SCU1_CLK_SEL2,
+		.bit_shift = 20,
+		.bit_width = 3,
+		.div_table = ast2700_clk_div_table,
+	},
+	[SCU1_CLK_APB] = {
+		.type = CLK_DIV_TABLE,
+		.name = "soc1-apb",
+		.parent_names = (const char *[]){"soc1-hpll", },
+		.reg = SCU1_CLK_SEL1,
+		.bit_shift = 18,
+		.bit_width = 3,
+		.div_table = ast2700_clk_div_table2,
+	},
+	[SCU1_CLK_RMII] = {
+		.type = CLK_DIV_TABLE,
+		.name = "rmii",
+		.parent_names = (const char *[]){"soc1-hpll", },
+		.reg = SCU1_CLK_SEL1,
+		.bit_shift = 21,
+		.bit_width = 3,
+		.div_table = ast2700_rmii_div_table,
+	},
+	[SCU1_CLK_MAC0RCLK] = {
+		.type = CLK_GATE,
+		.name = "mac0rclk",
+		.parent_names = (const char *[]){ "rmii", },
+		.reg = SCU1_MAC12_CLK_DLY,
+		.clk_idx = 29,
+	},
+	[SCU1_CLK_MAC1RCLK] = {
+		.type = CLK_GATE,
+		.name = "mac1rclk",
+		.parent_names = (const char *[]){ "rmii", },
+		.reg = SCU1_MAC12_CLK_DLY,
+		.clk_idx = 30,
+	},
+	[SCU1_CLK_RGMII] = {
+		.type = CLK_DIV_TABLE,
+		.name = "rgmii",
+		.parent_names = (const char *[]){"soc1-hpll", },
+		.reg = SCU1_CLK_SEL1,
+		.bit_shift = 25,
+		.bit_width = 3,
+		.div_table = ast2700_rgmii_div_table,
+	},
+	[SCU1_CLK_MACHCLK] = {
+		.type = CLK_DIV_TABLE,
+		.name = "machclk",
+		.parent_names = (const char *[]){"soc1-hpll", },
+		.reg = SCU1_CLK_SEL1,
+		.bit_shift = 29,
+		.bit_width = 3,
+		.div_table = ast2700_clk_div_table,
+	},
+	[SCU1_CLK_GATE_LCLK0] = {
+		.type = CLK_GATE,
+		.name = "lclk0-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 0,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU1_CLK_GATE_LCLK1] = {
+		.type = CLK_GATE,
+		.name = "lclk1-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 1,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU1_CLK_GATE_ESPI0CLK] = {
+		.type = CLK_GATE,
+		.name = "espi0clk-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 2,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU1_CLK_GATE_ESPI1CLK] = {
+		.type = CLK_GATE,
+		.name = "espi1clk-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 3,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU1_CLK_APLL_DIVN] = {
+		.type = CLK_DIV_TABLE,
+		.name = "soc1-apll_divn",
+		.parent_names = (const char *[]){"soc1-apll", },
+		.reg = SCU1_CLK_SEL2,
+		.bit_shift = 8,
+		.bit_width = 3,
+		.div_table = ast2700_clk_div_table,
+	},
+	[SCU1_CLK_SDMUX] = {
+		.type = CLK_MUX,
+		.name = "sdclk-mux",
+		.parent_names = (const char *[]){ "soc1-hpll", "soc1-apll", },
+		.num_parents = 2,
+		.reg = SCU1_CLK_SEL1,
+		.bit_shift = 13,
+		.bit_width = 1,
+	},
+	[SCU1_CLK_SDCLK] = {
+		.type = CLK_DIV_TABLE,
+		.name = "sdclk",
+		.parent_names = (const char *[]){"sdclk-mux", },
+		.reg = SCU1_CLK_SEL1,
+		.bit_shift = 14,
+		.bit_width = 3,
+		.div_table = ast2700_clk_div_table,
+	},
+	[SCU1_CLK_GATE_SDCLK] = {
+		.type = CLK_GATE,
+		.name = "sdclk-gate",
+		.parent_names = (const char *[]){"sdclk", },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 4,
+	},
+	[SCU1_CLK_GATE_IPEREFCLK] = {
+		.type = CLK_GATE,
+		.name = "soc1-iperefclk-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 5,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU1_CLK_GATE_REFCLK] = {
+		.type = CLK_GATE,
+		.name = "soc1-refclk-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 6,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU1_CLK_GATE_LPCHCLK] = {
+		.type = CLK_GATE,
+		.name = "lpchclk-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 7,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU1_CLK_GATE_MAC0CLK] = {
+		.type = CLK_GATE,
+		.name = "mac0clk-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 8,
+	},
+	[SCU1_CLK_GATE_MAC1CLK] = {
+		.type = CLK_GATE,
+		.name = "mac1clk-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 9,
+	},
+	[SCU1_CLK_GATE_MAC2CLK] = {
+		.type = CLK_GATE,
+		.name = "mac2clk-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 10,
+	},
+	[SCU1_CLK_UART0] = {
+		.type = CLK_MUX,
+		.name = "uart0clk",
+		.parent_names = (const char *[]){"uartxclk", "huartxclk", },
+		.num_parents = 2,
+		.reg = SCU1_CLK_SEL1,
+		.bit_shift = 0,
+		.bit_width = 1,
+	},
+	[SCU1_CLK_GATE_UART0CLK] = {
+		.type = CLK_GATE,
+		.name = "uart0clk-gate",
+		.parent_names = (const char *[]){ "uart0clk", },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 11,
+	},
+	[SCU1_CLK_UART1] = {
+		.type = CLK_MUX,
+		.name = "uart1clk",
+		.parent_names = (const char *[]){"uartxclk", "huartxclk", },
+		.num_parents = 2,
+		.reg = SCU1_CLK_SEL1,
+		.bit_shift = 1,
+		.bit_width = 1,
+	},
+	[SCU1_CLK_GATE_UART1CLK] = {
+		.type = CLK_GATE,
+		.name = "uart1clk-gate",
+		.parent_names = (const char *[]){ "uart1clk", },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 12,
+	},
+	[SCU1_CLK_UART2] = {
+		.type = CLK_MUX,
+		.name = "uart2clk",
+		.parent_names = (const char *[]){"uartxclk", "huartxclk", },
+		.num_parents = 2,
+		.reg = SCU1_CLK_SEL1,
+		.bit_shift = 2,
+		.bit_width = 1,
+	},
+	[SCU1_CLK_GATE_UART2CLK] = {
+		.type = CLK_GATE,
+		.name = "uart2clk-gate",
+		.parent_names = (const char *[]){ "uart2clk", },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 13,
+	},
+	[SCU1_CLK_UART3] = {
+		.type = CLK_MUX,
+		.name = "uart3clk",
+		.parent_names = (const char *[]){"uartxclk", "huartxclk", },
+		.num_parents = 2,
+		.reg = SCU1_CLK_SEL1,
+		.bit_shift = 3,
+		.bit_width = 1,
+	},
+	[SCU1_CLK_GATE_UART3CLK] = {
+		.type = CLK_GATE,
+		.name = "uart3clk-gate",
+		.parent_names = (const char *[]){ "uart3clk", },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 14,
+	},
+	[SCU1_CLK_GATE_I2CCLK] = {
+		.type = CLK_GATE,
+		.name = "i2cclk-gate",
+		.parent_names = (const char *[]){	},
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 15,
+	},
+	[SCU1_CLK_GATE_I3C0CLK] = {
+		.type = CLK_GATE,
+		.name = "i3c0clk-gate",
+		.parent_names = (const char *[]){ "soc1-ahb", },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 16,
+	},
+	[SCU1_CLK_GATE_I3C1CLK] = {
+		.type = CLK_GATE,
+		.name = "i3c1clk-gate",
+		.parent_names = (const char *[]){ "soc1-ahb", },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 17,
+	},
+	[SCU1_CLK_GATE_I3C2CLK] = {
+		.type = CLK_GATE,
+		.name = "i3c2clk-gate",
+		.parent_names = (const char *[]){ "soc1-ahb", },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 18,
+	},
+	[SCU1_CLK_GATE_I3C3CLK] = {
+		.type = CLK_GATE,
+		.name = "i3c3clk-gate",
+		.parent_names = (const char *[]){ "soc1-ahb", },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 19,
+	},
+	[SCU1_CLK_GATE_I3C4CLK] = {
+		.type = CLK_GATE,
+		.name = "i3c4clk-gate",
+		.parent_names = (const char *[]){ "soc1-ahb", },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 20,
+	},
+	[SCU1_CLK_GATE_I3C5CLK] = {
+		.type = CLK_GATE,
+		.name = "i3c5clk-gate",
+		.parent_names = (const char *[]){ "soc1-ahb", },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 21,
+	},
+	[SCU1_CLK_GATE_I3C6CLK] = {
+		.type = CLK_GATE,
+		.name = "i3c6clk-gate",
+		.parent_names = (const char *[]){ "soc1-ahb", },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 22,
+	},
+	[SCU1_CLK_GATE_I3C7CLK] = {
+		.type = CLK_GATE,
+		.name = "i3c7clk-gate",
+		.parent_names = (const char *[]){ "soc1-ahb", },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 23,
+	},
+	[SCU1_CLK_GATE_I3C8CLK] = {
+		.type = CLK_GATE,
+		.name = "i3c8clk-gate",
+		.parent_names = (const char *[]){ "soc1-ahb", },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 24,
+	},
+	[SCU1_CLK_GATE_I3C9CLK] = {
+		.type = CLK_GATE,
+		.name = "i3c9clk-gate",
+		.parent_names = (const char *[]){ "soc1-ahb", },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 25,
+	},
+	[SCU1_CLK_GATE_I3C10CLK] = {
+		.type = CLK_GATE,
+		.name = "i3c10clk-gate",
+		.parent_names = (const char *[]){ "soc1-ahb", },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 26,
+	},
+	[SCU1_CLK_GATE_I3C11CLK] = {
+		.type = CLK_GATE,
+		.name = "i3c11clk-gate",
+		.parent_names = (const char *[]){ "soc1-ahb", },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 27,
+	},
+	[SCU1_CLK_GATE_I3C12CLK] = {
+		.type = CLK_GATE,
+		.name = "i3c12clk-gate",
+		.parent_names = (const char *[]){ "soc1-ahb", },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 28,
+	},
+	[SCU1_CLK_GATE_I3C13CLK] = {
+		.type = CLK_GATE,
+		.name = "i3c13clk-gate",
+		.parent_names = (const char *[]){ "soc1-ahb", },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 29,
+	},
+	[SCU1_CLK_GATE_I3C14CLK] = {
+		.type = CLK_GATE,
+		.name = "i3c14clk-gate",
+		.parent_names = (const char *[]){ "soc1-ahb", },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 30,
+	},
+	[SCU1_CLK_GATE_I3C15CLK] = {
+		.type = CLK_GATE,
+		.name = "i3c15clk-gate",
+		.parent_names = (const char *[]){ "soc1-ahb", },
+		.reg = SCU1_CLK_STOP,
+		.clk_idx = 31,
+	},
+	[SCU1_CLK_UART5] = {
+		.type = CLK_MUX,
+		.name = "uart5clk",
+		.parent_names = (const char *[]){"uartxclk", "huartxclk", },
+		.num_parents = 2,
+		.reg = SCU1_CLK_SEL1,
+		.bit_shift = 5,
+		.bit_width = 1,
+	},
+	[SCU1_CLK_GATE_UART5CLK] = {
+		.type = CLK_GATE,
+		.name = "uart5clk-gate",
+		.parent_names = (const char *[]){ "uart5clk", },
+		.reg = SCU1_CLK_STOP2,
+		.clk_idx = 0,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU1_CLK_UART6] = {
+		.type = CLK_MUX,
+		.name = "uart6clk",
+		.parent_names = (const char *[]){"uartxclk", "huartxclk", },
+		.num_parents = 2,
+		.reg = SCU1_CLK_SEL1,
+		.bit_shift = 6,
+		.bit_width = 1,
+	},
+	[SCU1_CLK_GATE_UART6CLK] = {
+		.type = CLK_GATE,
+		.name = "uart6clk-gate",
+		.parent_names = (const char *[]){ "uart6clk", },
+		.reg = SCU1_CLK_STOP2,
+		.clk_idx = 1,
+	},
+	[SCU1_CLK_UART7] = {
+		.type = CLK_MUX,
+		.name = "uart7clk",
+		.parent_names = (const char *[]){"uartxclk", "huartxclk", },
+		.num_parents = 2,
+		.reg = SCU1_CLK_SEL1,
+		.bit_shift = 7,
+		.bit_width = 1,
+	},
+	[SCU1_CLK_GATE_UART7CLK] = {
+		.type = CLK_GATE,
+		.name = "uart7clk-gate",
+		.parent_names = (const char *[]){ "uart7clk", },
+		.reg = SCU1_CLK_STOP2,
+		.clk_idx = 2,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU1_CLK_UART8] = {
+		.type = CLK_MUX,
+		.name = "uart8clk",
+		.parent_names = (const char *[]){"uartxclk", "huartxclk", },
+		.num_parents = 2,
+		.reg = SCU1_CLK_SEL1,
+		.bit_shift = 8,
+		.bit_width = 1,
+	},
+	[SCU1_CLK_GATE_UART8CLK] = {
+		.type = CLK_GATE,
+		.name = "uart8clk-gate",
+		.parent_names = (const char *[]){ "uart8clk", },
+		.reg = SCU1_CLK_STOP2,
+		.clk_idx = 3,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU1_CLK_UART9] = {
+		.type = CLK_MUX,
+		.name = "uart9clk",
+		.parent_names = (const char *[]){"uartxclk", "huartxclk", },
+		.num_parents = 2,
+		.reg = SCU1_CLK_SEL1,
+		.bit_shift = 9,
+		.bit_width = 1,
+	},
+	[SCU1_CLK_GATE_UART9CLK] = {
+		.type = CLK_GATE,
+		.name = "uart9clk-gate",
+		.parent_names = (const char *[]){ "uart9clk", },
+		.reg = SCU1_CLK_STOP2,
+		.clk_idx = 4,
+	},
+	[SCU1_CLK_UART10] = {
+		.type = CLK_MUX,
+		.name = "uart10clk",
+		.parent_names = (const char *[]){"uartxclk", "huartxclk", },
+		.num_parents = 2,
+		.reg = SCU1_CLK_SEL1,
+		.bit_shift = 10,
+		.bit_width = 1,
+	},
+	[SCU1_CLK_GATE_UART10CLK] = {
+		.type = CLK_GATE,
+		.name = "uart10clk-gate",
+		.parent_names = (const char *[]){ "uart10clk", },
+		.reg = SCU1_CLK_STOP2,
+		.clk_idx = 5,
+	},
+	[SCU1_CLK_UART11] = {
+		.type = CLK_MUX,
+		.name = "uart11clk",
+		.parent_names = (const char *[]){"uartxclk", "huartxclk", },
+		.num_parents = 2,
+		.reg = SCU1_CLK_SEL1,
+		.bit_shift = 11,
+		.bit_width = 1,
+	},
+	[SCU1_CLK_GATE_UART11CLK] = {
+		.type = CLK_GATE,
+		.name = "uart11clk-gate",
+		.parent_names = (const char *[]){ "uart11clk", },
+		.reg = SCU1_CLK_STOP2,
+		.clk_idx = 6,
+	},
+	[SCU1_CLK_UART12] = {
+		.type = CLK_MUX,
+		.name = "uart12clk",
+		.parent_names = (const char *[]){"uartxclk", "huartxclk", },
+		.num_parents = 2,
+		.reg = SCU1_CLK_SEL1,
+		.bit_shift = 12,
+		.bit_width = 1,
+	},
+	[SCU1_CLK_GATE_UART12CLK] = {
+		.type = CLK_GATE,
+		.name = "uart12clk-gate",
+		.parent_names = (const char *[]){ "uart12clk", },
+		.reg = SCU1_CLK_STOP2,
+		.clk_idx = 7,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU1_CLK_UART13] = {
+		.type = CLK_FIXED_FACTOR,
+		.name = "uart13clk",
+		.parent_names = (const char *[]){ "huartxclk", },
+		.mult = 1,
+		.div = 1,
+	},
+	[SCU1_CLK_UART14] = {
+		.type = CLK_FIXED_FACTOR,
+		.name = "uart14clk",
+		.parent_names = (const char *[]){ "huartxclk", },
+		.mult = 1,
+		.div = 1,
+	},
+	[SCU1_CLK_GATE_FSICLK] = {
+		.type = CLK_GATE,
+		.name = "fsiclk-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU1_CLK_STOP2,
+		.clk_idx = 8,
+	},
+	[SCU1_CLK_GATE_LTPIPHYCLK] = {
+		.type = CLK_GATE,
+		.name = "ltpiphyclk-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU1_CLK_STOP2,
+		.clk_idx = 9,
+	},
+	[SCU1_CLK_GATE_LTPICLK] = {
+		.type = CLK_GATE,
+		.name = "ltpiclk-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU1_CLK_STOP2,
+		.clk_idx = 10,
+	},
+	[SCU1_CLK_GATE_VGALCLK] = {
+		.type = CLK_GATE,
+		.name = "vgalclk-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU1_CLK_STOP2,
+		.clk_idx = 11,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU1_CLK_GATE_UHCICLK] = {
+		.type = CLK_GATE,
+		.name = "usbuartclk-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU1_CLK_STOP2,
+		.clk_idx = 12,
+	},
+	[SCU1_CLK_CAN] = {
+		.type = CLK_FIXED_FACTOR,
+		.name = "canclk",
+		.parent_names = (const char *[]){ "soc1-apll", },
+		.mult = 1,
+		.div = 10,
+	},
+	[SCU1_CLK_GATE_CANCLK] = {
+		.type = CLK_GATE,
+		.name = "canclk-gate",
+		.parent_names = (const char *[]){ "canclk", },
+		.reg = SCU1_CLK_STOP2,
+		.clk_idx = 13,
+	},
+	[SCU1_CLK_GATE_PCICLK] = {
+		.type = CLK_GATE,
+		.name = "pciclk-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU1_CLK_STOP2,
+		.clk_idx = 14,
+	},
+	[SCU1_CLK_GATE_SLICLK] = {
+		.type = CLK_GATE,
+		.name = "soc1-sliclk-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU1_CLK_STOP2,
+		.clk_idx = 15,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU1_CLK_GATE_E2MCLK] = {
+		.type = CLK_GATE,
+		.name = "soc1-e2m-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU1_CLK_STOP2,
+		.clk_idx = 16,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU1_CLK_GATE_PORTCUSB2CLK] = {
+		.type = CLK_GATE,
+		.name = "portcusb2-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU1_CLK_STOP2,
+		.clk_idx = 17,
+		.flags = CLK_IS_CRITICAL,
+	},
+	[SCU1_CLK_GATE_PORTDUSB2CLK] = {
+		.type = CLK_GATE,
+		.name = "portdusb2-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU1_CLK_STOP2,
+		.clk_idx = 18,
+	},
+	[SCU1_CLK_GATE_LTPI1TXCLK] = {
+		.type = CLK_GATE,
+		.name = "ltp1tx-gate",
+		.parent_names = (const char *[]){  },
+		.reg = SCU1_CLK_STOP2,
+		.clk_idx = 19,
+	},
+};
+
+static struct clk_hw *ast2700_clk_hw_register_pll(int clk_idx, void __iomem *reg,
+						  const struct ast2700_clk_info *clk,
+						  struct ast2700_clk_ctrl *clk_ctrl)
+{
+	unsigned int mult, div;
+	u32 val;
+
+	if (clk_idx == SCU0_CLK_HPLL) {
+		val = readl(clk_ctrl->base + SCU0_HWSTRAP1);
+		if ((val & GENMASK(3, 2)) != 0) {
+			switch ((val & GENMASK(3, 2)) >> 2) {
+			case 1:
+				return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, "soc0-hpll",
+								       NULL, 0, 1900000000);
+			case 2:
+				return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, "soc0-hpll",
+								       NULL, 0, 1800000000);
+			case 3:
+				return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, "soc0-hpll",
+								       NULL, 0, 1700000000);
+			default:
+				return ERR_PTR(-EINVAL);
+			}
+		}
+	}
+
+	val = readl(reg);
+
+	if (val & BIT(24)) {
+		/* Pass through mode */
+		mult = 1;
+		div = 1;
+	} else {
+		u32 m = val & 0x1fff;
+		u32 n = (val >> 13) & 0x3f;
+		u32 p = (val >> 19) & 0xf;
+
+		if (clk_idx == SCU0_CLK_MPLL) {
+			mult = m / (n + 1);
+			div = (p + 1);
+		} else if ((clk_idx == SCU1_CLK_HPLL) ||
+			   (clk_idx == SCU1_CLK_APLL) ||
+			   (clk_idx == SCU1_CLK_DPLL)) {
+			mult = (m + 1) / (n + 1);
+			div = (p + 1);
+		} else {
+			mult = (m + 1) / (2 * (n + 1));
+			div = (p + 1);
+		}
+	}
+
+	return devm_clk_hw_register_fixed_factor(clk_ctrl->dev, clk->name,
+						 clk->parent_names[0], 0, mult, div);
+}
+
+static struct clk_hw *ast2700_clk_hw_register_uartpll(int clk_idx, void __iomem *reg,
+						      const struct ast2700_clk_info *clk,
+						      struct ast2700_clk_ctrl *clk_ctrl)
+{
+	unsigned int mult, div;
+	u32 val = readl(reg);
+	u32 r = val & 0xff;
+	u32 n = (val >> 8) & 0x3ff;
+
+	mult = r;
+	div = n * 2;
+
+	return devm_clk_hw_register_fixed_factor(clk_ctrl->dev, clk->name,
+						 clk->parent_names[0], 0, mult, div);
+}
+
+static struct clk_hw *ast2700_clk_hw_register_misc(int clk_idx, void __iomem *reg,
+						   const struct ast2700_clk_info *clk,
+						   struct ast2700_clk_ctrl *clk_ctrl)
+{
+	u32 div = 0;
+
+	if (clk_idx == SCU0_CLK_MPHY)
+		div = readl(reg) + 1;
+	else if (clk_idx == SCU0_CLK_U2PHY_REFCLK)
+		div = (GET_USB_REFCLK_DIV(readl(reg)) + 1) << 1;
+	else
+		return ERR_PTR(-EINVAL);
+
+	return devm_clk_hw_register_fixed_factor(clk_ctrl->dev, clk->name,
+						   clk->parent_names[0], clk->flags,
+						   1, div);
+}
+
+static int ast2700_clk_is_enabled(struct clk_hw *hw)
+{
+	struct clk_gate *gate = to_clk_gate(hw);
+	u32 clk = BIT(gate->bit_idx);
+	u32 reg;
+
+	reg = readl(gate->reg);
+
+	return !(reg & clk);
+}
+
+static int ast2700_clk_enable(struct clk_hw *hw)
+{
+	struct clk_gate *gate = to_clk_gate(hw);
+	u32 clk = BIT(gate->bit_idx);
+
+	if (readl(gate->reg) & clk)
+		writel(clk, gate->reg + 0x04);
+
+	return 0;
+}
+
+static void ast2700_clk_disable(struct clk_hw *hw)
+{
+	struct clk_gate *gate = to_clk_gate(hw);
+	u32 clk = BIT(gate->bit_idx);
+
+	/* Clock is set to enable, so use write to set register */
+	writel(clk, gate->reg);
+}
+
+static const struct clk_ops ast2700_clk_gate_ops = {
+	.enable = ast2700_clk_enable,
+	.disable = ast2700_clk_disable,
+	.is_enabled = ast2700_clk_is_enabled,
+};
+
+static struct clk_hw *ast2700_clk_hw_register_gate(struct device *dev, const char *name,
+						   const char *parent_name, unsigned long flags,
+						   void __iomem *reg, u8 clock_idx,
+						   u8 clk_gate_flags, spinlock_t *lock)
+{
+	struct clk_gate *gate;
+	struct clk_hw *hw;
+	struct clk_init_data init;
+	int ret = -EINVAL;
+
+	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+	if (!gate)
+		return ERR_PTR(-ENOMEM);
+
+	init.name = name;
+	init.ops = &ast2700_clk_gate_ops;
+	init.flags = flags;
+	init.parent_names = parent_name ? &parent_name : NULL;
+	init.num_parents = parent_name ? 1 : 0;
+
+	gate->reg = reg;
+	gate->bit_idx = clock_idx;
+	gate->flags = clk_gate_flags;
+	gate->lock = lock;
+	gate->hw.init = &init;
+
+	hw = &gate->hw;
+	ret = clk_hw_register(dev, hw);
+	if (ret) {
+		kfree(gate);
+		hw = ERR_PTR(ret);
+	}
+
+	return hw;
+}
+
+static void aspeed_reset_unregister_adev(void *_adev)
+{
+	struct auxiliary_device *adev = _adev;
+
+	auxiliary_device_delete(adev);
+	auxiliary_device_uninit(adev);
+}
+
+static void aspeed_reset_adev_release(struct device *dev)
+{
+	struct auxiliary_device *adev = to_auxiliary_dev(dev);
+
+	kfree(adev);
+}
+
+static int aspeed_reset_controller_register(struct device *clk_dev,
+					    void __iomem *base, const char *adev_name)
+{
+	struct auxiliary_device *adev;
+	int ret;
+
+	adev = kzalloc(sizeof(*adev), GFP_KERNEL);
+	if (!adev)
+		return -ENOMEM;
+
+	adev->name = adev_name;
+	adev->dev.parent = clk_dev;
+	adev->dev.release = aspeed_reset_adev_release;
+	adev->id = 666u;
+
+	ret = auxiliary_device_init(adev);
+	if (ret) {
+		kfree(adev);
+		return ret;
+	}
+
+	ret = auxiliary_device_add(adev);
+	if (ret) {
+		auxiliary_device_uninit(adev);
+		return ret;
+	}
+
+	adev->dev.platform_data = (__force void *)base;
+
+	return devm_add_action_or_reset(clk_dev, aspeed_reset_unregister_adev, adev);
+}
+
+static int ast2700_soc_clk_probe(struct platform_device *pdev)
+{
+	struct ast2700_clk_data *clk_data;
+	struct ast2700_clk_ctrl *clk_ctrl;
+	struct clk_hw_onecell_data *clk_hw_data;
+	struct device *dev = &pdev->dev;
+	void __iomem *clk_base;
+	struct clk_hw **hws;
+	int ret;
+	int i;
+
+	clk_ctrl = devm_kzalloc(dev, sizeof(*clk_ctrl), GFP_KERNEL);
+	if (!clk_ctrl)
+		return -ENOMEM;
+	clk_ctrl->dev = dev;
+	dev_set_drvdata(&pdev->dev, clk_ctrl);
+
+	spin_lock_init(&clk_ctrl->lock);
+
+	clk_base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(clk_base))
+		return PTR_ERR(clk_base);
+
+	clk_ctrl->base = clk_base;
+
+	clk_data = (struct ast2700_clk_data *)of_device_get_match_data(dev);
+	if (!clk_data)
+		return devm_of_platform_populate(dev);
+
+	clk_ctrl->clk_data = clk_data;
+	clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, clk_data->nr_clks),
+				   GFP_KERNEL);
+	if (!clk_hw_data)
+		return -ENOMEM;
+
+	clk_hw_data->num = clk_data->nr_clks;
+	hws = clk_hw_data->hws;
+
+	for (i = 0; i < clk_data->nr_clks; i++) {
+		const struct ast2700_clk_info *clk = &clk_data->clk_info[i];
+		void __iomem *reg = clk_ctrl->base + clk->reg;
+
+		if (clk->type == CLK_FIXED) {
+			hws[i] = devm_clk_hw_register_fixed_rate(dev, clk->name, NULL,
+								 clk->flags, clk->fixed_rate);
+		} else if (clk->type == CLK_FIXED_FACTOR) {
+			hws[i] = devm_clk_hw_register_fixed_factor(dev, clk->name,
+								   clk->parent_names[0], clk->flags,
+								   clk->mult, clk->div);
+		} else if (clk->type == CLK_PLL) {
+			hws[i] = ast2700_clk_hw_register_pll(i, reg, clk, clk_ctrl);
+		} else if (clk->type == CLK_UART_PLL) {
+			hws[i] = ast2700_clk_hw_register_uartpll(i, reg, clk, clk_ctrl);
+		} else if (clk->type == CLK_MUX) {
+			hws[i] = devm_clk_hw_register_mux(dev, clk->name, clk->parent_names,
+							  clk->num_parents, clk->flags, reg,
+							  clk->bit_shift, clk->bit_width,
+							  0, &clk_ctrl->lock);
+		} else if (clk->type == CLK_MISC) {
+			hws[i] = ast2700_clk_hw_register_misc(i, reg, clk, clk_ctrl);
+		} else if (clk->type == CLK_DIVIDER) {
+			hws[i] = devm_clk_hw_register_divider(dev, clk->name, clk->parent_names[0],
+							      clk->flags, reg, clk->bit_shift,
+							      clk->bit_width, 0,
+							      &clk_ctrl->lock);
+		} else if (clk->type == CLK_DIV_TABLE) {
+			hws[i] = clk_hw_register_divider_table(dev, clk->name, clk->parent_names[0],
+							       clk->flags, reg, clk->bit_shift,
+							       clk->bit_width, 0,
+							       clk->div_table, &clk_ctrl->lock);
+		} else {
+			hws[i] = ast2700_clk_hw_register_gate(dev, clk->name, clk->parent_names[0],
+							      clk->flags, reg, clk->clk_idx,
+							      clk->flags, &clk_ctrl->lock);
+		}
+
+		if (IS_ERR(hws[i]))
+			return PTR_ERR(hws[i]);
+	}
+
+	ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_hw_data);
+	if (ret)
+		return ret;
+	return aspeed_reset_controller_register(dev, clk_base, clk_data->reset_name);
+}
+
+static const struct ast2700_clk_data ast2700_clk0_data = {
+	.reset_name = "reset0",
+	.nr_clks = ARRAY_SIZE(ast2700_scu0_clk_info),
+	.clk_info = ast2700_scu0_clk_info,
+};
+
+static const struct ast2700_clk_data ast2700_clk1_data = {
+	.reset_name = "reset1",
+	.nr_clks = ARRAY_SIZE(ast2700_scu1_clk_info),
+	.clk_info = ast2700_scu1_clk_info,
+};
+
+static const struct of_device_id ast2700_scu_match[] = {
+	{ .compatible = "aspeed,ast2700-scu0", .data = &ast2700_clk0_data },
+	{ .compatible = "aspeed,ast2700-scu1", .data = &ast2700_clk1_data },
+	{ /* sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, ast2700_scu_match);
+
+static struct platform_driver ast2700_scu_driver = {
+	.driver = {
+		.name = "clk-ast2700",
+		.of_match_table = ast2700_scu_match,
+	},
+};
+
+builtin_platform_driver_probe(ast2700_scu_driver, ast2700_soc_clk_probe);
-- 
2.34.1