From: Gatien CHEVALLIER <gatien.chevallier@foss.st.com>
To: Kamlesh Gurudasani <kamlesh@ti.com>,
Olivia Mackall <olivia@selenic.com>,
Herbert Xu <herbert@gondor.apana.org.au>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Lionel Debieve <lionel.debieve@foss.st.com>,
<linux-crypto@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-stm32@st-md-mailman.stormreply.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [EXTERNAL] [PATCH v3 9/9] ARM: dts: stm32: add RNG node for STM32MP13x platforms
Date: Mon, 25 Sep 2023 11:31:49 +0200 [thread overview]
Message-ID: <9b81c8aa-e43d-18db-bc0c-4ae05c4d22bb@foss.st.com> (raw)
In-Reply-To: <8734z6hb5i.fsf@kamlesh.i-did-not-set--mail-host-address--so-tickle-me>
Hi Kamlesh,
On 9/22/23 10:20, Kamlesh Gurudasani wrote:
> Gatien Chevallier <gatien.chevallier@foss.st.com> writes:
>
>> The RNG on STM32MP13 offers upgrades like customization of its
>> configuration and the conditional reset.
>>
>> The hardware RNG should be managed in the secure world for but it
>> is supported on Linux. Therefore, is it not default enabled.
> Just curious, will there be concurrent access? If yes, how do you manage
> the entropy in that case?
>
Any read on the data register leads to its refreshment. There can be
only one access at a time at the bus level. The rest (FIFO is empty
after request, etc...) is managed by the code in this patchset.
> If you allow access to RNG from normal world, can attacker change the
> setting to generate more predicatable numbers leading this to secure
> world as well.
>
> I understand that you're leaving the enablement part to customer but
> you still have to allow RNG access to normal world for that.
>
> -Kamlesh
If RNG is secure, then it should be managed by the secure world and
accessed via some interface. Ours is OP-TEE RNG PTA. The secure level
of the peripheral is managed by the ETZPC, which manages the security
configuration of the board's peripherals.
If the RNG is assigned to the non-secure world, then yes, the non-secure
world can access the RNG configuration. Now, your question is: what
happens to the secure world in such case? The answer is that it should
run on a pseudo-random software RNG seeded at boot by the hardware RNG.
So there's no link anymore if non-secure world deteriorates the
hardware RNG configuration.
Of course, if such choice is made, it's up to the customer to see the
whole picture.
Best regards,
Gatien
next prev parent reply other threads:[~2023-09-25 9:32 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-21 8:02 [PATCH v3 0/9] hwrng: stm32: support STM32MP13x platforms Gatien Chevallier
2023-09-21 8:02 ` [PATCH v3 1/9] dt-bindings: rng: introduce new compatible for STM32MP13x Gatien Chevallier
2023-09-22 20:49 ` Rob Herring
2023-09-21 8:02 ` [PATCH v3 2/9] hwrng: stm32 - use devm_platform_get_and_ioremap_resource() API Gatien Chevallier
2023-09-21 8:02 ` [PATCH v3 3/9] hwrng: stm32 - implement STM32MP13x support Gatien Chevallier
2023-09-21 8:02 ` [PATCH v3 4/9] hwrng: stm32 - implement error concealment Gatien Chevallier
2023-09-21 8:02 ` [PATCH v3 5/9] hwrng: stm32 - rework error handling in stm32_rng_read() Gatien Chevallier
2023-09-21 8:02 ` [PATCH v3 6/9] hwrng: stm32 - restrain RNG noise source clock Gatien Chevallier
2023-09-21 8:02 ` [PATCH v3 7/9] hwrng: stm32 - support RNG configuration locking mechanism Gatien Chevallier
2023-09-21 8:03 ` [PATCH v3 8/9] hwrng: stm32 - rework power management sequences Gatien Chevallier
2023-09-21 8:03 ` [PATCH v3 9/9] ARM: dts: stm32: add RNG node for STM32MP13x platforms Gatien Chevallier
2023-09-22 8:20 ` [EXTERNAL] " Kamlesh Gurudasani
2023-09-25 9:31 ` Gatien CHEVALLIER [this message]
2023-10-01 8:33 ` [PATCH v3 0/9] hwrng: stm32: support " Herbert Xu
2023-10-09 12:02 ` Alexandre TORGUE
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