From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from vps0.lunn.ch (vps0.lunn.ch [156.67.10.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69160403138; Mon, 3 Aug 2026 13:04:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=156.67.10.101 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785762256; cv=none; b=VpLhlLNLszf4OTSitRPpGwIDHqgFl5H+PvRbwczJjcHz+rICvRFKvh76DWIEA9FgElGpD1o9NbUfuf+KQlYHp1UX8gKoiZmy4ULPkMflEcw2sAcGdA0GOLxmwNIGOU2iCmpgOhGTEeecmGbQgdVRRPb//uGcmkOMfXYbxiMoQAg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785762256; c=relaxed/simple; bh=r1xBIWy/MQrn7nEXQkmfV7p4q1IEpi7+k/GEDW9rDac=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=sxuFw+9aI8fiCB9mWEKN66UVIgzbAeN5NkDAsQUVEWbRXxxadkSoQcH4oVgHJM8AIXykytSZAOzege5e1LSuSH7Abwsn0SkVXu2cAm249Vx/JhGhWfKE5QLzEhQSWnd/MmigSIKisCO+/hgxEHKkrwVrCTn+fcxHE+ouHW8hcU4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch; spf=pass smtp.mailfrom=lunn.ch; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b=57DJFhIE; arc=none smtp.client-ip=156.67.10.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=lunn.ch Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="57DJFhIE" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=qYW1GlKfnYGWsKz9hDLBhG+gnWS4Y4jhMNCvwxcvapw=; b=57DJFhIEhQlqIb1DsW9YiXoDyr aUsz3ewgXhLcalGDwEfqhdjJRWdZW/Z55SlW+/l2ZGYqDj7nPdF9h2pnN4MxM1lEPFYy+Fxpy8w3c IKy9NxUY7TmmH20GnrrU5G3mmr3ITPqi7VkmJYDej+H06mjCiX5OnzCScoiUNb12TLqI=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1wqsKj-00Fj1a-Nv; Mon, 03 Aug 2026 15:03:57 +0200 Date: Mon, 3 Aug 2026 15:03:57 +0200 From: Andrew Lunn To: James Hilliard Cc: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andre Przywara , Richard Genoud , Maxime Ripard , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Maxime Chevallier , Maxime Coquelin , Heiner Kallweit , Russell King , Saravana Kannan , Lee Jones , Heiko Stuebner , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, mfd@lists.linux.dev, linux-rockchip@lists.infradead.org Subject: Re: [PATCH 01/21] dt-bindings: net: allwinner: add H616 EMAC1 Message-ID: <9bdee210-cff4-4400-9293-80b7ae1706bc@lunn.ch> References: <20260802-submit-acx00-of-dynamic-v1-v1-0-0a53cd9e21cc@gmail.com> <20260802-submit-acx00-of-dynamic-v1-v1-1-0a53cd9e21cc@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260802-submit-acx00-of-dynamic-v1-v1-1-0a53cd9e21cc@gmail.com> > Constrain the PHY interface mode to RMII, matching the hardware. The > EMAC1 clock register also retains the three-bit TX and five-bit RX delay > chains, so allow the existing Allwinner delay properties for this > compatible. The delay properties are for RGMII, not RMII. What do they actually do when used with RMII? Andrew