From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Jie Gan <jie.gan@oss.qualcomm.com>,
Mike Leach <mike.leach@linaro.org>,
James Clark <james.clark@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Tingwei Zhang <tingwei.zhang@oss.qualcomm.com>,
Jinlong Mao <jinlong.mao@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>
Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v6 6/9] dt-bindings: arm: add an interrupt property for Coresight CTCU
Date: Thu, 4 Dec 2025 09:22:38 +0000 [thread overview]
Message-ID: <9c00516c-6e07-4c57-a1f1-6dfc32ab3a53@arm.com> (raw)
In-Reply-To: <5a0e4abf-9e7f-4ef9-af02-dd6e34f5cfa8@oss.qualcomm.com>
On 04/12/2025 02:53, Jie Gan wrote:
>
>
> On 12/4/2025 2:14 AM, Suzuki K Poulose wrote:
>> On 08/09/2025 03:01, Jie Gan wrote:
>>> Add an interrupt property to CTCU device. The interrupt will be
>>> triggered
>>> when the data size in the ETR buffer exceeds the threshold of the
>>> BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL
>>> register
>>> of CTCU device will enable the interrupt.
>>>
>>> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
>>> ---
>>> .../devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 17 ++++++
>>> + ++++++++++
>>> 1 file changed, 17 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-
>>> ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-
>>> ctcu.yaml
>>> index 843b52eaf872..ea05ad8f3dd3 100644
>>> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
>>> @@ -39,6 +39,16 @@ properties:
>>> items:
>>> - const: apb
>>> + interrupts:
>>> + items:
>>> + - description: Byte cntr interrupt for etr0
>>> + - description: Byte cntr interrupt for etr1
>>> +
>>> + interrupt-names:
>>> + items:
>>> + - const: etr0
>>> + - const: etr1
>>
>
> Hi Suzuki,
>
>> Why are they named "etr0" "etr1" ? That would be confusing, isn't it,
>> especially with the Linux driver naming things randomly for the TMC-ETRs.
>>
>
> Yes, it will cause misunderstandings since the "etr0" here may not the
> right device we are expecting.
>
>>
>> What we want is the "port" number corresponding to the "TMC-ETR" being
>> monitored ?
>>
>> Have you explored other options, "port-0", "port-1" ?
>>
>
> I think it's much better. Will update in next version.
I am not sure if there exists a better scheme for identifying or
numbering the interrupts. Happy to listen to the DT experts.
Rob, Krzysztof, thoughts ?
Suzuki
>
> Thanks,
> Jie
>
>> Suzuki
>>
>>> +
>>> in-ports:
>>> $ref: /schemas/graph.yaml#/properties/ports
>>> @@ -56,6 +66,8 @@ additionalProperties: false
>>> examples:
>>> - |
>>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +
>>> ctcu@1001000 {
>>> compatible = "qcom,sa8775p-ctcu";
>>> reg = <0x1001000 0x1000>;
>>> @@ -63,6 +75,11 @@ examples:
>>> clocks = <&aoss_qmp>;
>>> clock-names = "apb";
>>> + interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
>>> + <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>;
>>> + interrupt-names = "etr0",
>>> + "etr1";
>>> +
>>> in-ports {
>>> #address-cells = <1>;
>>> #size-cells = <0>;
>>>
>>
>>
>
next prev parent reply other threads:[~2025-12-04 9:22 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-08 2:01 [PATCH v6 0/9] coresight: ctcu: Enable byte-cntr function for TMC ETR Jie Gan
2025-09-08 2:01 ` [PATCH v6 1/9] coresight: core: Refactoring ctcu_get_active_port and make it generic Jie Gan
2025-12-03 16:18 ` Suzuki K Poulose
2025-12-04 2:45 ` Jie Gan
2025-09-08 2:01 ` [PATCH v6 2/9] coresight: core: add a new API to retrieve the helper device Jie Gan
2025-12-03 16:15 ` Suzuki K Poulose
2025-12-04 2:47 ` Jie Gan
2025-09-08 2:01 ` [PATCH v6 3/9] coresight: tmc: add etr_buf_list to store allocated etr_buf Jie Gan
2025-12-03 14:24 ` Mike Leach
2025-12-03 16:20 ` Suzuki K Poulose
2025-09-08 2:01 ` [PATCH v6 4/9] coresight: tmc: add create/clean functions for etr_buf_list Jie Gan
2025-12-03 14:26 ` Mike Leach
2025-09-08 2:01 ` [PATCH v6 5/9] coresight: tmc: Introduce sysfs_read_ops to wrap sysfs read operations Jie Gan
2025-09-08 2:01 ` [PATCH v6 6/9] dt-bindings: arm: add an interrupt property for Coresight CTCU Jie Gan
2025-12-03 14:30 ` Mike Leach
2025-12-04 2:49 ` Jie Gan
2025-12-03 18:14 ` Suzuki K Poulose
2025-12-04 2:53 ` Jie Gan
2025-12-04 9:22 ` Suzuki K Poulose [this message]
2025-12-05 1:01 ` Jie Gan
2025-09-08 2:01 ` [PATCH v6 7/9] coresight: ctcu: enable byte-cntr for TMC ETR devices Jie Gan
2025-09-08 2:02 ` [PATCH v6 8/9] coresight: tmc: integrate byte-cntr's read_ops with sysfs file_ops Jie Gan
2025-09-08 2:02 ` [PATCH v6 9/9] arm64: dts: qcom: lemans: Add interrupts to CTCU device Jie Gan
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