[PATCH 0/2] Add support for configuring pin properties on RZ/T2H-N2H SoCs

Prabhakar
2025-10-14T19:11:33Z

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi all,

This patch series adds support for configuring pin properties on the
Renesas RZ/T2H-N2H SoCs. The RZ/T2H allows configuring pin properties
through the DRCTLm (I/O Buffer Function Switching) registers, including:
- Drive strength (low/middle/high/ultra high)
- Pull-up/pull-down/no-bias configuration (3 options: no pull, pull-up,
pull-down)
- Schmitt trigger control (enable/disable)
- Slew rate control (2 options: slow/fast)

Cheers,
Prabhakar

Lad Prabhakar (2):
dt-bindings: pinctrl: renesas,r9a09g077: Document pin configuration
properties
pinctrl: renesas: rzt2h: Add pin configuration support

.../pinctrl/renesas,r9a09g077-pinctrl.yaml | 13 +
drivers/pinctrl/renesas/pinctrl-rzt2h.c | 230 ++++++++++++++++++
2 files changed, 243 insertions(+)

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2.43.0