From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sergei Shtylyov Subject: Re: [PATCH v3 4/8] phy: phy-mt65xx-usb3: move clock from phy node into port nodes Date: Wed, 22 Feb 2017 12:34:56 +0300 Message-ID: <9c4b9e9d-d50c-0941-1712-2715c64b0a0e@cogentembedded.com> References: <1487753705-6745-1-git-send-email-chunfeng.yun@mediatek.com> <1487753705-6745-4-git-send-email-chunfeng.yun@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1487753705-6745-4-git-send-email-chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Chunfeng Yun , Kishon Vijay Abraham I Cc: Matthias Brugger , Felipe Balbi , Rob Herring , Mark Rutland , Ian Campbell , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org Hello! On 2/22/2017 11:55 AM, Chunfeng Yun wrote: > the reference clock of HighSpeed port is 48M which comes from PLL; > the reference clock of SuperSpeed port is 26M which usually comes > from 26M oscillator directly, but some SoCs are not, add it for ... but on some SoCs does not? > compatibility, and put them into port node for flexibility. > > Signed-off-by: Chunfeng Yun [...] MBR, Sergei -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html