From: Atish Patra <atish.patra@linux.dev>
To: Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Conor Dooley <conor@kernel.org>,
devicetree@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-perf-users@vger.kernel.org, Jiri Olsa <jolsa@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Adrian Hunter <adrian.hunter@intel.com>
Subject: Re: [PATCH v5 20/21] tools/perf: Pass the Counter constraint values in the pmu events
Date: Tue, 22 Apr 2025 17:17:56 -0700 [thread overview]
Message-ID: <9d827020-ee6c-40c2-a83d-7eb9a00f8aa8@linux.dev> (raw)
In-Reply-To: <20250327-counter_delegation-v5-20-1ee538468d1b@rivosinc.com>
On 3/27/25 12:36 PM, Atish Patra wrote:
> RISC-V doesn't have any standard event to counter mapping discovery
> mechanism in the ISA. The ISA defines 29 programmable counters and
> platforms can choose to implement any number of them and map any
> events to any counters. Thus, the perf tool need to inform the driver
> about the counter mapping of each events.
>
> The current perf infrastructure only parses the 'Counter' constraints
> in metrics. This patch extends that to pass in the pmu events so that
> any driver can retrieve those values via perf attributes if defined
> accordingly.
>
Hi Ian/Arnaldo/Namhyung,
Any thoughts on this patch ? Please let me know if there are any other
better approaches to pass the counter constraints to the driver ?
The RISC-V pmu driver maps the attr.config2 with counterid_mask value
so that driver can parse the counter restrictions.
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
> tools/perf/pmu-events/jevents.py | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py
> index fdb7ddf093d2..f9f274678a32 100755
> --- a/tools/perf/pmu-events/jevents.py
> +++ b/tools/perf/pmu-events/jevents.py
> @@ -274,6 +274,11 @@ class JsonEvent:
> return fixed[name.lower()]
> return event
>
> + def counter_list_to_bitmask(counterlist):
> + counter_ids = list(map(int, counterlist.split(',')))
> + bitmask = sum(1 << pos for pos in counter_ids)
> + return bitmask
> +
> def unit_to_pmu(unit: str) -> Optional[str]:
> """Convert a JSON Unit to Linux PMU name."""
> if not unit or unit == "core":
> @@ -427,6 +432,10 @@ class JsonEvent:
> else:
> raise argparse.ArgumentTypeError('Cannot find arch std event:', arch_std)
>
> + if self.counters['list']:
> + bitmask = counter_list_to_bitmask(self.counters['list'])
> + event += f',counterid_mask={bitmask:#x}'
> +
> self.event = real_event(self.name, event)
>
> def __repr__(self) -> str:
>
next prev parent reply other threads:[~2025-04-23 0:18 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-27 19:35 [PATCH v5 00/21] Add Counter delegation ISA extension support Atish Patra
2025-03-27 19:35 ` [PATCH v5 01/21] perf pmu-events: Add functions in jevent.py to parse counter and event info for hardware aware grouping Atish Patra
2025-04-23 0:13 ` Atish Patra
2025-03-27 19:35 ` [PATCH v5 02/21] RISC-V: Add Sxcsrind ISA extension CSR definitions Atish Patra
2025-03-27 19:35 ` [PATCH v5 03/21] RISC-V: Add Sxcsrind ISA extension definition and parsing Atish Patra
2025-03-27 19:35 ` [PATCH v5 04/21] dt-bindings: riscv: add Sxcsrind ISA extension description Atish Patra
2025-03-27 19:35 ` [PATCH v5 05/21] RISC-V: Define indirect CSR access helpers Atish Patra
2025-03-27 19:35 ` [PATCH v5 06/21] RISC-V: Add Smcntrpmf extension parsing Atish Patra
2025-03-27 19:35 ` [PATCH v5 07/21] dt-bindings: riscv: add Smcntrpmf ISA extension description Atish Patra
2025-03-27 19:35 ` [PATCH v5 08/21] RISC-V: Add Sscfg extension CSR definition Atish Patra
2025-03-27 19:35 ` [PATCH v5 09/21] RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing Atish Patra
2025-03-27 19:35 ` [PATCH v5 10/21] dt-bindings: riscv: add Counter delegation ISA extensions description Atish Patra
2025-03-31 15:38 ` Conor Dooley
2025-03-27 19:35 ` [PATCH v5 11/21] RISC-V: perf: Restructure the SBI PMU code Atish Patra
2025-04-04 13:49 ` Will Deacon
2025-04-23 0:02 ` Atish Patra
2025-03-27 19:35 ` [PATCH v5 12/21] RISC-V: perf: Modify the counter discovery mechanism Atish Patra
2025-03-27 19:35 ` [PATCH v5 13/21] RISC-V: perf: Add a mechanism to defined legacy event encoding Atish Patra
2025-03-27 19:35 ` [PATCH v5 14/21] RISC-V: perf: Implement supervisor counter delegation support Atish Patra
2025-08-28 9:56 ` [External] " yunhui cui
2025-03-27 19:35 ` [PATCH v5 15/21] RISC-V: perf: Skip PMU SBI extension when not implemented Atish Patra
2025-03-27 19:35 ` [PATCH v5 16/21] RISC-V: perf: Use config2/vendor table for event to counter mapping Atish Patra
2025-03-27 19:35 ` [PATCH v5 17/21] RISC-V: perf: Add legacy event encodings via sysfs Atish Patra
2025-03-27 19:35 ` [PATCH v5 18/21] RISC-V: perf: Add Qemu virt machine events Atish Patra
2025-03-27 19:36 ` [PATCH v5 19/21] tools/perf: Support event code for arch standard events Atish Patra
2025-03-27 19:36 ` [PATCH v5 20/21] tools/perf: Pass the Counter constraint values in the pmu events Atish Patra
2025-04-23 0:17 ` Atish Patra [this message]
2025-03-27 19:36 ` [PATCH v5 21/21] Sync empty-pmu-events.c with autogenerated one Atish Patra
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