From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C178FC43461 for ; Mon, 7 Sep 2020 16:31:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8E5B9207DE for ; Mon, 7 Sep 2020 16:31:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="QMX+0gMo" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729831AbgIGQbp (ORCPT ); Mon, 7 Sep 2020 12:31:45 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:52962 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729690AbgIGOXp (ORCPT ); Mon, 7 Sep 2020 10:23:45 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 087ENTOZ013858; Mon, 7 Sep 2020 09:23:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1599488609; bh=vOt5jgEVI5IP+P9UtdrVL509eExBOW74aWC6FEjb+Ms=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=QMX+0gMoJGX9c4bZFtbLZ12SZeQaaeAqeF04GCGaR8mwLdSYZm38q5QpW0q4vVEJK seryiNxaDCxa2jEHoQJt0Q8Oq2fDDztBwpJzSpOhGVyMUBiP4pc/sJ3nbKy9sDda7h 948s74VICdKZ+x7OsYHdz6JKgHXZgp/JUJOkAOlo= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 087ENT1I053179 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 7 Sep 2020 09:23:29 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 7 Sep 2020 09:23:29 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 7 Sep 2020 09:23:29 -0500 Received: from [10.24.69.20] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 087ENJNp087360; Mon, 7 Sep 2020 09:23:24 -0500 Subject: Re: [PATCH v2 0/4] arm64: Initial support for Texas Instrument's J7200 Platform To: Nishanth Menon CC: Tero Kristo , Rob Herring , Linux ARM Mailing List , Device Tree Mailing List , Sekhar Nori , Suman Anna , Grygorii Strashko References: <20200827065144.17683-1-lokeshvutla@ti.com> <20200907141427.ti6r3h6namv2hezw@akan> From: Lokesh Vutla Message-ID: <9d8d6980-0b22-da45-52af-474c6d96c873@ti.com> Date: Mon, 7 Sep 2020 19:53:19 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <20200907141427.ti6r3h6namv2hezw@akan> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 07/09/20 7:44 pm, Nishanth Menon wrote: > On 17:32-20200907, Lokesh Vutla wrote: >> Hi, >> >> On 27/08/20 12:21 pm, Lokesh Vutla wrote: >>> This series adds initial support for latest new SoC, J7200, from Texas Instruments. >>> >>> The J7200 SoC is a part of the K3 Multicore SoC architecture platform. >>> It is targeted for for automotive gateway, vehicle compute systems, >>> Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications. >>> The SoC aims to meet the complex processing needs of modern embedded products. >>> >>> See J7200 Technical Reference Manual (SPRUIU1, June 2020) >>> for further details: https://www.ti.com/lit/pdf/spruiu1 >>> >>> Changes since v1: >>> - Swapped Patch 1 and 2 as suggested by Nishanth. >>> - Added description for each SoC in yaml bindings. >>> >>> Testing: >>> - ./scripts/checkpatch --strict >>> - Few warningns about Line length exceeding 100 columns. >>> But these are corresponding to comments >>> - v8make dtbs_check >>> - DT_SCHEMA_FLAGS="-u" >>> DT_SCHEMA_FILES="Documentation/devicetree/bindings/arm/ti/k3.yaml" >>> v8make dtbs_check >>> - DT_SCHEMA_FLAGS="-u" >>> DT_SCHEMA_FILES="Documentation/devicetree/bindings/arm/ti/k3.yaml" >>> v8make dt_binding_check >> >> This series has been lying around for soo long with no major comments. It will >> be nice to get this merged. I understand we are waiting for Acks on yaml >> documentation but it would be bad to miss a merge window for a new platform >> because we are waiting for Acks on yaml conversion. > > I do require Rob / DT maintainer to ack the DT yaml conversion and the > j7200 binding addition. > > Besides yaml and compatibility acks, there are a few ancillary > comments to fix up.. Kconfig -> I think we should either stay with > status quo and create a new config option per SoC OR rename the > config to be generic (using j7200 with j721e SoC config is not very Please suggest your preference here. I guess separate defconfig for J7200? > consistent). In addition, around the stuff that is going to next in > parallel, the dts is generating additional warnings as well (DSS hmm..there is no DSS being added in this series. There is one checkpatch warning for PATCH 1: WARNING: DT binding docs and includes should be a separate patch. See: Documentation/devicetree/bindings/submitting-patches.rst This can be ignored. > etc). I think it might be easier if we wait for DT maintainer ack on > bindings prior to giving further cosmetic comments (To allow for any > additional changes to come in to -next). > okay. Thanks and regards, Lokesh