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Tue, 28 Jan 2025 10:50:54 -0800 (PST) Received: from [100.64.0.1] ([165.188.116.9]) by smtp.gmail.com with ESMTPSA id ca18e2360f4ac-8521e035792sm345458739f.40.2025.01.28.10.50.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 28 Jan 2025 10:50:54 -0800 (PST) Message-ID: <9dc005ef-3cba-4f9d-9d99-6a6fa49d9383@sifive.com> Date: Tue, 28 Jan 2025 12:50:52 -0600 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 1/4] dt-bindings: gpio: spacemit: add support for K1 SoC To: Rob Herring , Linus Walleij Cc: devicetree@vger.kernel.org, Conor Dooley , Meng Zhang , Yixun Lan , linux-gpio@vger.kernel.org, Bartosz Golaszewski , linux-kernel@vger.kernel.org, Conor Dooley , Yangyu Chen , Palmer Dabbelt , Jesse Taube , Jisheng Zhang , Paul Walmsley , Olof Johansson , Inochi Amaoto , Krzysztof Kozlowski , linux-riscv@lists.infradead.org References: <20250121-03-k1-gpio-v4-0-4641c95c0194@gentoo.org> <20250121-03-k1-gpio-v4-1-4641c95c0194@gentoo.org> <20250123113042-GYA38135@gentoo> <20250127181726.GA538260-robh@kernel.org> <20250128031712-GYB47737@gentoo> From: Samuel Holland Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 2025-01-28 10:58 AM, Rob Herring wrote: > On Tue, Jan 28, 2025 at 10:03 AM Linus Walleij wrote: >> >> On Tue, Jan 28, 2025 at 4:17 AM Yixun Lan wrote: >> >>> [Rob] >>>> If Linux can't handle 1 node for N gpio_chip's, then that's a Linux >>>> problem. Maybe it can, IDK. >>> >>> I haven't seen somthing like this to register 1 node for multi gpio_chips.. >>> To gpio/pinctrl maintainer (Linus Walleij), do you have suggestion on this? >> >> For Linux we can call bgpio_init() three times and >> devm_gpiochip_add_data() three times on the result and if we use the >> approach with three cells (where the second is instance 0,1,2 and the >> last one the offset 0..31) then it will work all just the same I guess? >> >> foo-gpios <&gpio 2 7 GPIO_ACTIVE_LOW>; >> >> for offset 7 on block 2 for example. >> >> We need a custom xlate function I suppose. >> >> It just has not been done that way before, everybody just did >> 2-cell GPIOs. > > You can do either 3 cells or 2 cells splitting the 1st cell into > . I'm pretty sure we have some cases of the latter. There is also at least one example of 3-cell GPIOs: Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml It supports controllers with varying numbers of pins per bank and banks in each instance. Compared to the design described above, it shares a single gpio_chip across all banks in a controller instance. Regards, Samuel