[PATCH 0/6] Add initial support for QCS615

[PATCH 0/6] Add initial support for QCS615

[Lijuan Gao]

Add initial support for QCS615 SoC and QCS615 RIDE board with basic
description of CPUs, interrupt-controller and cpu idle, which enable
the board boot to shell with dcc console.

Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
Lijuan Gao (6):
      dt-bindings: qcom,pdc: document QCS615 Power Domain Controller
      dt-bindings: arm: qcom: document QCS615 and the reference board
      dt-bindings: arm: qcom,ids: add SoC ID for QCS615
      soc: qcom: socinfo: Add QCS615 SoC ID table entry
      arm64: dts: qcom: add initial support for QCS615 DTSI
      arm64: dts: qcom: add base QCS615 RIDE dts

 Documentation/devicetree/bindings/arm/qcom.yaml    |   6 +
 .../bindings/interrupt-controller/qcom,pdc.yaml    |   1 +
 arch/arm64/boot/dts/qcom/Makefile                  |   1 +
 arch/arm64/boot/dts/qcom/qcs615-ride.dts           |  15 +
 arch/arm64/boot/dts/qcom/qcs615.dtsi               | 449 +++++++++++++++++++++
 drivers/soc/qcom/socinfo.c                         |   1 +
 include/dt-bindings/arm/qcom,ids.h                 |   1 +
 7 files changed, 474 insertions(+)
---
base-commit: 0dec408547d2a9e21ea44eab538a1ca852f0be0d
change-id: 20240827-add_initial_support_for_qcs615-3f3823c3c518

Best regards,
-- 
Lijuan Gao <quic_lijuang@quicinc.com>

[PATCH 1/6] dt-bindings: qcom,pdc: document QCS615 Power Domain Controller

[Lijuan Gao]

Add a compatible for the Power Domain Controller on QCS615 platforms.

Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
index 985fa10abb99..5e234e845cb8 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
@@ -26,6 +26,7 @@ properties:
   compatible:
     items:
       - enum:
+          - qcom,qcs615-pdc
           - qcom,qdu1000-pdc
           - qcom,sa8775p-pdc
           - qcom,sc7180-pdc

-- 
2.46.0

[PATCH 2/6] dt-bindings: arm: qcom: document QCS615 and the reference board

[Lijuan Gao]

Document the QCS615 SoC and its reference board QCS615 RIDE.

Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index c0529486810f..957c3bc91ef2 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -42,6 +42,7 @@ description: |
         msm8996
         msm8998
         qcs404
+        qcs615
         qcs8550
         qcm2290
         qcm6490
@@ -895,6 +896,11 @@ properties:
           - const: qcom,qcs404-evb
           - const: qcom,qcs404
 
+      - items:
+          - enum:
+              - qcom,qcs615-ride
+          - const: qcom,qcs615
+
       - items:
           - enum:
               - qcom,sa8155p-adp

-- 
2.46.0

[PATCH 3/6] dt-bindings: arm: qcom,ids: add SoC ID for QCS615

[Lijuan Gao]

Add the ID for the Qualcomm QCS615 SoC.

Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 include/dt-bindings/arm/qcom,ids.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h
index 8332f8d82f96..73a69fc535f6 100644
--- a/include/dt-bindings/arm/qcom,ids.h
+++ b/include/dt-bindings/arm/qcom,ids.h
@@ -278,6 +278,7 @@
 #define QCOM_ID_IPQ5321			650
 #define QCOM_ID_QCS8300			674
 #define QCOM_ID_QCS8275			675
+#define QCOM_ID_QCS615			680
 
 /*
  * The board type and revision information, used by Qualcomm bootloaders and

-- 
2.46.0

[PATCH 4/6] soc: qcom: socinfo: Add QCS615 SoC ID table entry

[Lijuan Gao]

Add SoC Info support for the QCS615 platform.

Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 drivers/soc/qcom/socinfo.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c
index 24c3971f2ef1..aed430f10eec 100644
--- a/drivers/soc/qcom/socinfo.c
+++ b/drivers/soc/qcom/socinfo.c
@@ -445,6 +445,7 @@ static const struct soc_id soc_id[] = {
 	{ qcom_board_id(IPQ5321) },
 	{ qcom_board_id(QCS8300) },
 	{ qcom_board_id(QCS8275) },
+	{ qcom_board_id(QCS615) },
 };
 
 static const char *socinfo_machine(struct device *dev, unsigned int id)

-- 
2.46.0

[PATCH 5/6] arm64: dts: qcom: add initial support for QCS615 DTSI

[Lijuan Gao]

Add initial DTSI for QCS615 SoC. It includes base description
of CPUs, interrupt-controller and cpu idle on Qualcomm QCS615
platform.

Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615.dtsi | 449 +++++++++++++++++++++++++++++++++++
 1 file changed, 449 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
new file mode 100644
index 000000000000..cf7aaa7f6131
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -0,0 +1,449 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen { };
+
+	clocks {
+		xo_board: xo-board {
+			compatible = "fixed-clock";
+			clock-frequency = <38400000>;
+			#clock-cells = <0>;
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+			#clock-cells = <0>;
+		};
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			power-domains = <&CPU_PD0>;
+			power-domain-names = "psci";
+			next-level-cache = <&L2_0>;
+			#cooling-cells = <2>;
+
+			L2_0: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      cache-unified;
+			      next-level-cache = <&L3_0>;
+
+				L3_0: l3-cache {
+				      compatible = "cache";
+				      cache-level = <3>;
+				      cache-unified;
+				};
+			};
+		};
+
+		CPU1: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			power-domains = <&CPU_PD1>;
+			power-domain-names = "psci";
+			next-level-cache = <&L2_100>;
+
+			L2_100: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      cache-unified;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU2: cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x200>;
+			enable-method = "psci";
+			power-domains = <&CPU_PD2>;
+			power-domain-names = "psci";
+			next-level-cache = <&L2_200>;
+
+			L2_200: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      cache-unified;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU3: cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x300>;
+			enable-method = "psci";
+			power-domains = <&CPU_PD3>;
+			power-domain-names = "psci";
+			next-level-cache = <&L2_300>;
+
+			L2_300: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      cache-unified;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU4: cpu@400 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x400>;
+			enable-method = "psci";
+			power-domains = <&CPU_PD4>;
+			power-domain-names = "psci";
+			next-level-cache = <&L2_400>;
+
+			L2_400: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      cache-unified;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU5: cpu@500 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x500>;
+			enable-method = "psci";
+			power-domains = <&CPU_PD5>;
+			power-domain-names = "psci";
+			next-level-cache = <&L2_500>;
+
+			L2_500: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      cache-unified;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU6: cpu@600 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a76";
+			reg = <0x0 0x600>;
+			enable-method = "psci";
+			power-domains = <&CPU_PD6>;
+			power-domain-names = "psci";
+			next-level-cache = <&L2_600>;
+			#cooling-cells = <2>;
+
+			L2_600: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      cache-unified;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU7: cpu@700 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a76";
+			reg = <0x0 0x700>;
+			enable-method = "psci";
+			power-domains = <&CPU_PD7>;
+			power-domain-names = "psci";
+			next-level-cache = <&L2_700>;
+
+			L2_700: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      cache-unified;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+
+				core1 {
+					cpu = <&CPU1>;
+				};
+
+				core2 {
+					cpu = <&CPU2>;
+				};
+
+				core3 {
+					cpu = <&CPU3>;
+				};
+
+				core4 {
+					cpu = <&CPU4>;
+				};
+
+				core5 {
+					cpu = <&CPU5>;
+				};
+
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&CPU6>;
+				};
+
+				core1 {
+					cpu = <&CPU7>;
+				};
+			};
+		};
+	};
+
+	idle-states {
+		LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
+			compatible = "arm,idle-state";
+			idle-state-name = "silver-power-collapse";
+			arm,psci-suspend-param = <0x40000003>;
+			entry-latency-us = <549>;
+			exit-latency-us = <901>;
+			min-residency-us = <1774>;
+			local-timer-stop;
+		};
+
+		LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
+			compatible = "arm,idle-state";
+			idle-state-name = "silver-rail-power-collapse";
+			arm,psci-suspend-param = <0x40000004>;
+			entry-latency-us = <702>;
+			exit-latency-us = <915>;
+			min-residency-us = <4001>;
+			local-timer-stop;
+		};
+
+		BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
+			compatible = "arm,idle-state";
+			idle-state-name = "gold-power-collapse";
+			arm,psci-suspend-param = <0x40000003>;
+			entry-latency-us = <523>;
+			exit-latency-us = <1244>;
+			min-residency-us = <2207>;
+			local-timer-stop;
+		};
+
+		BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
+			compatible = "arm,idle-state";
+			idle-state-name = "gold-rail-power-collapse";
+			arm,psci-suspend-param = <0x40000004>;
+			entry-latency-us = <526>;
+			exit-latency-us = <1854>;
+			min-residency-us = <5555>;
+			local-timer-stop;
+		};
+	};
+
+	domain-idle-states {
+		CLUSTER_SLEEP_0: cluster-sleep-0 {
+			compatible = "domain-idle-state";
+			arm,psci-suspend-param = <0x41000044>;
+			entry-latency-us = <2752>;
+			exit-latency-us = <3048>;
+			min-residency-us = <6118>;
+		};
+
+		CLUSTER_SLEEP_1: cluster-sleep-1 {
+			compatible = "domain-idle-state";
+			arm,psci-suspend-param = <0x41001344>;
+			entry-latency-us = <3263>;
+			exit-latency-us = <4562>;
+			min-residency-us = <8467>;
+		};
+
+		SYSTEM_SLEEP: domain-sleep {
+			compatible = "domain-idle-state";
+			arm,psci-suspend-param = <0x4100b344>;
+			entry-latency-us = <3638>;
+			exit-latency-us = <6562>;
+			min-residency-us = <9826>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the size */
+		reg = <0 0x80000000 0 0>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+
+		CPU_PD0: power-domain-cpu0 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
+		};
+
+		CPU_PD1: power-domain-cpu1 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
+		};
+
+		CPU_PD2: power-domain-cpu2 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
+		};
+
+		CPU_PD3: power-domain-cpu3 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
+		};
+
+		CPU_PD4: power-domain-cpu4 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
+		};
+
+		CPU_PD5: power-domain-cpu5 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
+		};
+
+		CPU_PD6: power-domain-cpu6 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
+		};
+
+		CPU_PD7: power-domain-cpu7 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
+		};
+
+		CLUSTER_PD: power-domain-cluster {
+			#power-domain-cells = <0>;
+			domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1 &SYSTEM_SLEEP>;
+		};
+	};
+
+	soc: soc@0 {
+		compatible = "simple-bus";
+		ranges = <0 0 0 0 0x10 0>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		tcsr_mutex: hwlock@1f40000 {
+			compatible = "qcom,tcsr-mutex";
+			reg = <0x0 0x01f40000 0x0 0x20000>;
+			#hwlock-cells = <1>;
+		};
+
+		pdc: interrupt-controller@b220000 {
+			compatible = "qcom,qcs615-pdc", "qcom,pdc";
+			reg = <0x0 0xb220000 0x0 0x30000>,
+			      <0x0 0x17c000f0 0x0 0x64>;
+			qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
+			interrupt-parent = <&intc>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
+		intc: interrupt-controller@17a00000 {
+			compatible = "arm,gic-v3";
+			reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
+			      <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			#redistributor-regions = <1>;
+			redistributor-stride = <0x0 0x20000>;
+		};
+
+		timer@17c20000 {
+			compatible = "arm,armv7-timer-mem";
+			reg = <0x0 0x17c20000 0x0 0x1000>;
+			ranges = <0 0 0 0x20000000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			frame@17c21000 {
+				reg = <0x17c21000 0x1000>,
+				      <0x17c22000 0x1000>;
+				frame-number = <0>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			frame@17c23000 {
+				reg = <0x17c23000 0x1000>;
+				frame-number = <1>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17c25000 {
+				reg = <0x17c25000 0x1000>;
+				frame-number = <2>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17c27000 {
+				reg = <0x17c27000 0x1000>;
+				frame-number = <3>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17c29000 {
+				reg = <0x17c29000 0x1000>;
+				frame-number = <4>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17c2b000 {
+				reg = <0x17c2b000 0x1000>;
+				frame-number = <5>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17c2d000 {
+				reg = <0x17c2d000 0x1000>;
+				frame-number = <6>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+		};
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+};

-- 
2.46.0

[PATCH 6/6] arm64: dts: qcom: add base QCS615 RIDE dts

[Lijuan Gao]

Add initial support for Qualcomm QCS615 RIDE board and enable
the QCS615 RIDE board to shell with dcc console.

Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 arch/arm64/boot/dts/qcom/Makefile        |  1 +
 arch/arm64/boot/dts/qcom/qcs615-ride.dts | 15 +++++++++++++++
 2 files changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 197ab325c0b9..c5503f189847 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -110,6 +110,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= qcm6490-idp.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qcm6490-shift-otter.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs404-evb-1000.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs404-evb-4000.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= qcs615-ride.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs6490-rb3gen2.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs8550-aim300-aiot.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qdu1000-idp.dtb
diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
new file mode 100644
index 000000000000..31d32ad951b5
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+/dts-v1/;
+
+#include "qcs615.dtsi"
+/ {
+	model = "Qualcomm Technologies, Inc. QCS615 Ride";
+	compatible = "qcom,qcs615-ride", "qcom,qcs615";
+
+	chosen {
+		bootargs = "console=hvc0";
+	};
+};

-- 
2.46.0

Re: [PATCH 1/6] dt-bindings: qcom,pdc: document QCS615 Power Domain Controller

[Krzysztof Kozlowski]

On Wed, Aug 28, 2024 at 10:02:11AM +0800, Lijuan Gao wrote:
> Add a compatible for the Power Domain Controller on QCS615 platforms.
> 
> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
> ---
>  Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 4/6] soc: qcom: socinfo: Add QCS615 SoC ID table entry

[Krzysztof Kozlowski]

On Wed, Aug 28, 2024 at 10:02:14AM +0800, Lijuan Gao wrote:
> Add SoC Info support for the QCS615 platform.
> 
> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
> ---
>  drivers/soc/qcom/socinfo.c | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 3/6] dt-bindings: arm: qcom,ids: add SoC ID for QCS615

[Krzysztof Kozlowski]

On Wed, Aug 28, 2024 at 10:02:13AM +0800, Lijuan Gao wrote:
> Add the ID for the Qualcomm QCS615 SoC.
> 
> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
> ---
>  include/dt-bindings/arm/qcom,ids.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h
> index 8332f8d82f96..73a69fc535f6 100644
> --- a/include/dt-bindings/arm/qcom,ids.h
> +++ b/include/dt-bindings/arm/qcom,ids.h
> @@ -278,6 +278,7 @@
>  #define QCOM_ID_IPQ5321			650
>  #define QCOM_ID_QCS8300			674
>  #define QCOM_ID_QCS8275			675
> +#define QCOM_ID_QCS615			680

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 2/6] dt-bindings: arm: qcom: document QCS615 and the reference board

[Krzysztof Kozlowski]

On Wed, Aug 28, 2024 at 10:02:12AM +0800, Lijuan Gao wrote:
> Document the QCS615 SoC and its reference board QCS615 RIDE.
> 
> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
> ---
>  Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 5/6] arm64: dts: qcom: add initial support for QCS615 DTSI

[Krzysztof Kozlowski]

On Wed, Aug 28, 2024 at 10:02:15AM +0800, Lijuan Gao wrote:
> Add initial DTSI for QCS615 SoC. It includes base description
> of CPUs, interrupt-controller and cpu idle on Qualcomm QCS615
> platform.
> 
> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs615.dtsi | 449 +++++++++++++++++++++++++++++++++++
>  1 file changed, 449 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> new file mode 100644
> index 000000000000..cf7aaa7f6131
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -0,0 +1,449 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	interrupt-parent = <&intc>;
> +

No need for blank line.

> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	chosen { };

Drop, redundant.

> +
> +	clocks {
> +		xo_board: xo-board {

xo-clk? xo-board-clk?

But if board, this does not sound like part of SoC. See other files how
they do it.


> +			compatible = "fixed-clock";
> +			clock-frequency = <38400000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		sleep_clk: sleep-clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <32000>;
> +			#clock-cells = <0>;
> +		};
> +	};
> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		CPU0: cpu@0 {

labels are lowercase.

> +			device_type = "cpu";
> +			compatible = "arm,cortex-a55";
> +			reg = <0x0 0x0>;
> +			enable-method = "psci";
> +			power-domains = <&CPU_PD0>;
> +			power-domain-names = "psci";
> +			next-level-cache = <&L2_0>;
> +			#cooling-cells = <2>;
> +
> +			L2_0: l2-cache {

lowercase

> +			      compatible = "cache";
> +			      cache-level = <2>;
> +			      cache-unified;
> +			      next-level-cache = <&L3_0>;

Best regards,
Krzysztof

Re: [PATCH 6/6] arm64: dts: qcom: add base QCS615 RIDE dts

[Krzysztof Kozlowski]

On Wed, Aug 28, 2024 at 10:02:16AM +0800, Lijuan Gao wrote:
> Add initial support for Qualcomm QCS615 RIDE board and enable
> the QCS615 RIDE board to shell with dcc console.
> 
> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/Makefile        |  1 +
>  arch/arm64/boot/dts/qcom/qcs615-ride.dts | 15 +++++++++++++++
>  2 files changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 197ab325c0b9..c5503f189847 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -110,6 +110,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= qcm6490-idp.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= qcm6490-shift-otter.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= qcs404-evb-1000.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= qcs404-evb-4000.dtb
> +dtb-$(CONFIG_ARCH_QCOM)	+= qcs615-ride.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= qcs6490-rb3gen2.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= qcs8550-aim300-aiot.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= qdu1000-idp.dtb
> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> new file mode 100644
> index 000000000000..31d32ad951b5
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> @@ -0,0 +1,15 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +/dts-v1/;
> +
> +#include "qcs615.dtsi"
> +/ {
> +	model = "Qualcomm Technologies, Inc. QCS615 Ride";
> +	compatible = "qcom,qcs615-ride", "qcom,qcs615";
> +
> +	chosen {
> +		bootargs = "console=hvc0";

Noooo, last time I agreed on this, you told me later it is different.

Best regards,
Krzysztof

Re: [PATCH 5/6] arm64: dts: qcom: add initial support for QCS615 DTSI

[Lijuan Gao]

在 8/28/2024 2:23 PM, Krzysztof Kozlowski 写道:
> On Wed, Aug 28, 2024 at 10:02:15AM +0800, Lijuan Gao wrote:
>> Add initial DTSI for QCS615 SoC. It includes base description
>> of CPUs, interrupt-controller and cpu idle on Qualcomm QCS615
>> platform.
>>
>> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/qcs615.dtsi | 449 +++++++++++++++++++++++++++++++++++
>>   1 file changed, 449 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> new file mode 100644
>> index 000000000000..cf7aaa7f6131
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> @@ -0,0 +1,449 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +/ {
>> +	interrupt-parent = <&intc>;
>> +
> 
> No need for blank line.
Well noted. Will update in the next patch.
> 
>> +	#address-cells = <2>;
>> +	#size-cells = <2>;
>> +
>> +	chosen { };
> 
> Drop, redundant.
Well noted. Will update in the next patch.
> 
>> +
>> +	clocks {
>> +		xo_board: xo-board {
> 
> xo-clk? xo-board-clk?
> 
> But if board, this does not sound like part of SoC. See other files how
> they do it.
> 
Other files also added ‘xo_board’. The ‘xo_board’ is the clock that will 
be used by other SoC nodes, such as rpmhcc. Currently, the node can be 
deleted as no one is using it.
> 
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <38400000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		sleep_clk: sleep-clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <32000>;
>> +			#clock-cells = <0>;
>> +		};
>> +	};
>> +
>> +	cpus {
>> +		#address-cells = <2>;
>> +		#size-cells = <0>;
>> +
>> +		CPU0: cpu@0 {
> 
> labels are lowercase.
Well noted. Will update in the next patch.
> 
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a55";
>> +			reg = <0x0 0x0>;
>> +			enable-method = "psci";
>> +			power-domains = <&CPU_PD0>;
>> +			power-domain-names = "psci";
>> +			next-level-cache = <&L2_0>;
>> +			#cooling-cells = <2>;
>> +
>> +			L2_0: l2-cache {
> 
> lowercase
Well noted. Will update in the next patch.
> 
>> +			      compatible = "cache";
>> +			      cache-level = <2>;
>> +			      cache-unified;
>> +			      next-level-cache = <&L3_0>;
> 
> Best regards,
> Krzysztof
> 
> 

-- 
Thx and BRs
Lijuan Gao

Re: [PATCH 6/6] arm64: dts: qcom: add base QCS615 RIDE dts

[Lijuan Gao]

在 8/28/2024 2:25 PM, Krzysztof Kozlowski 写道:
> On Wed, Aug 28, 2024 at 10:02:16AM +0800, Lijuan Gao wrote:
>> Add initial support for Qualcomm QCS615 RIDE board and enable
>> the QCS615 RIDE board to shell with dcc console.
>>
>> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/Makefile        |  1 +
>>   arch/arm64/boot/dts/qcom/qcs615-ride.dts | 15 +++++++++++++++
>>   2 files changed, 16 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index 197ab325c0b9..c5503f189847 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -110,6 +110,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= qcm6490-idp.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= qcm6490-shift-otter.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= qcs404-evb-1000.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= qcs404-evb-4000.dtb
>> +dtb-$(CONFIG_ARCH_QCOM)	+= qcs615-ride.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= qcs6490-rb3gen2.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= qcs8550-aim300-aiot.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= qdu1000-idp.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
>> new file mode 100644
>> index 000000000000..31d32ad951b5
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
>> @@ -0,0 +1,15 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +/dts-v1/;
>> +
>> +#include "qcs615.dtsi"
>> +/ {
>> +	model = "Qualcomm Technologies, Inc. QCS615 Ride";
>> +	compatible = "qcom,qcs615-ride", "qcom,qcs615";
>> +
>> +	chosen {
>> +		bootargs = "console=hvc0";
> 
> Noooo, last time I agreed on this, you told me later it is different.
> 
In the early stages, enabling HVC is to more easily verify clock and 
PMIC related functions, as it’s difficult to debug without the console 
log. After the clock and PMIC are ready, we will enable the UART console.
> Best regards,
> Krzysztof
> 
> 

-- 
Thx and BRs
Lijuan Gao

Re: [PATCH 5/6] arm64: dts: qcom: add initial support for QCS615 DTSI

[Krzysztof Kozlowski]

On 28/08/2024 09:42, Lijuan Gao wrote:
> 
> 
> 在 8/28/2024 2:23 PM, Krzysztof Kozlowski 写道:
>> On Wed, Aug 28, 2024 at 10:02:15AM +0800, Lijuan Gao wrote:
>>> Add initial DTSI for QCS615 SoC. It includes base description
>>> of CPUs, interrupt-controller and cpu idle on Qualcomm QCS615
>>> platform.
>>>
>>> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
>>> ---
>>>   arch/arm64/boot/dts/qcom/qcs615.dtsi | 449 +++++++++++++++++++++++++++++++++++
>>>   1 file changed, 449 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>> new file mode 100644
>>> index 000000000000..cf7aaa7f6131
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>> @@ -0,0 +1,449 @@
>>> +// SPDX-License-Identifier: BSD-3-Clause
>>> +/*
>>> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
>>> + */
>>> +
>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +
>>> +/ {
>>> +	interrupt-parent = <&intc>;
>>> +
>>
>> No need for blank line.
> Well noted. Will update in the next patch.
>>
>>> +	#address-cells = <2>;
>>> +	#size-cells = <2>;
>>> +
>>> +	chosen { };
>>
>> Drop, redundant.
> Well noted. Will update in the next patch.
>>
>>> +
>>> +	clocks {
>>> +		xo_board: xo-board {
>>
>> xo-clk? xo-board-clk?
>>
>> But if board, this does not sound like part of SoC. See other files how
>> they do it.
>>
> Other files also added ‘xo_board’. The ‘xo_board’ is the clock that will 

No. Don't use 10yo code as example.

> be used by other SoC nodes, such as rpmhcc. Currently, the node can be 
> deleted as no one is using it.

I don't think you understood the problem. This is not the property of
SoC. We talked about this many times. DTS coding style has even explicit
guideline for this. Your own go/upstream (which is quite well written
and complete) probably as well. Did you check it? If there is no such,
extend it.


Best regards,
Krzysztof

Re: [PATCH 6/6] arm64: dts: qcom: add base QCS615 RIDE dts

[Krzysztof Kozlowski]

On 28/08/2024 09:54, Lijuan Gao wrote:
> 
> 
> 在 8/28/2024 2:25 PM, Krzysztof Kozlowski 写道:
>> On Wed, Aug 28, 2024 at 10:02:16AM +0800, Lijuan Gao wrote:
>>> Add initial support for Qualcomm QCS615 RIDE board and enable
>>> the QCS615 RIDE board to shell with dcc console.
>>>
>>> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
>>> ---
>>>   arch/arm64/boot/dts/qcom/Makefile        |  1 +
>>>   arch/arm64/boot/dts/qcom/qcs615-ride.dts | 15 +++++++++++++++
>>>   2 files changed, 16 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>>> index 197ab325c0b9..c5503f189847 100644
>>> --- a/arch/arm64/boot/dts/qcom/Makefile
>>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>>> @@ -110,6 +110,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= qcm6490-idp.dtb
>>>   dtb-$(CONFIG_ARCH_QCOM)	+= qcm6490-shift-otter.dtb
>>>   dtb-$(CONFIG_ARCH_QCOM)	+= qcs404-evb-1000.dtb
>>>   dtb-$(CONFIG_ARCH_QCOM)	+= qcs404-evb-4000.dtb
>>> +dtb-$(CONFIG_ARCH_QCOM)	+= qcs615-ride.dtb
>>>   dtb-$(CONFIG_ARCH_QCOM)	+= qcs6490-rb3gen2.dtb
>>>   dtb-$(CONFIG_ARCH_QCOM)	+= qcs8550-aim300-aiot.dtb
>>>   dtb-$(CONFIG_ARCH_QCOM)	+= qdu1000-idp.dtb
>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
>>> new file mode 100644
>>> index 000000000000..31d32ad951b5
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
>>> @@ -0,0 +1,15 @@
>>> +// SPDX-License-Identifier: BSD-3-Clause
>>> +/*
>>> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
>>> + */
>>> +/dts-v1/;
>>> +
>>> +#include "qcs615.dtsi"
>>> +/ {
>>> +	model = "Qualcomm Technologies, Inc. QCS615 Ride";
>>> +	compatible = "qcom,qcs615-ride", "qcom,qcs615";
>>> +
>>> +	chosen {
>>> +		bootargs = "console=hvc0";
>>
>> Noooo, last time I agreed on this, you told me later it is different.
>>
> In the early stages, enabling HVC is to more easily verify clock and 
> PMIC related functions, as it’s difficult to debug without the console 
> log. After the clock and PMIC are ready, we will enable the UART console.

Working serial is supposed to be part of the early submission.

Best regards,
Krzysztof

Re: [PATCH 5/6] arm64: dts: qcom: add initial support for QCS615 DTSI

[Lijuan Gao]

在 8/28/2024 3:57 PM, Krzysztof Kozlowski 写道:
> On 28/08/2024 09:42, Lijuan Gao wrote:
>>
>>
>> 在 8/28/2024 2:23 PM, Krzysztof Kozlowski 写道:
>>> On Wed, Aug 28, 2024 at 10:02:15AM +0800, Lijuan Gao wrote:
>>>> Add initial DTSI for QCS615 SoC. It includes base description
>>>> of CPUs, interrupt-controller and cpu idle on Qualcomm QCS615
>>>> platform.
>>>>
>>>> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
>>>> ---
>>>>    arch/arm64/boot/dts/qcom/qcs615.dtsi | 449 +++++++++++++++++++++++++++++++++++
>>>>    1 file changed, 449 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>>> new file mode 100644
>>>> index 000000000000..cf7aaa7f6131
>>>> --- /dev/null
>>>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>>> @@ -0,0 +1,449 @@
>>>> +// SPDX-License-Identifier: BSD-3-Clause
>>>> +/*
>>>> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
>>>> + */
>>>> +
>>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>>> +
>>>> +/ {
>>>> +	interrupt-parent = <&intc>;
>>>> +
>>>
>>> No need for blank line.
>> Well noted. Will update in the next patch.
>>>
>>>> +	#address-cells = <2>;
>>>> +	#size-cells = <2>;
>>>> +
>>>> +	chosen { };
>>>
>>> Drop, redundant.
>> Well noted. Will update in the next patch.
>>>
>>>> +
>>>> +	clocks {
>>>> +		xo_board: xo-board {
>>>
>>> xo-clk? xo-board-clk?
>>>
>>> But if board, this does not sound like part of SoC. See other files how
>>> they do it.
>>>
>> Other files also added ‘xo_board’. The ‘xo_board’ is the clock that will
> 
> No. Don't use 10yo code as example.
> 
>> be used by other SoC nodes, such as rpmhcc. Currently, the node can be
>> deleted as no one is using it.
> 
> I don't think you understood the problem. This is not the property of
> SoC. We talked about this many times. DTS coding style has even explicit
> guideline for this. Your own go/upstream (which is quite well written
> and complete) probably as well. Did you check it? If there is no such,
> extend it.
>
Got it, I will move it to the board DTS.
> 
> Best regards,
> Krzysztof
> 
> 

-- 
Thx and BRs
Lijuan Gao

Re: [PATCH 6/6] arm64: dts: qcom: add base QCS615 RIDE dts

[Lijuan Gao]

在 8/28/2024 5:11 PM, Krzysztof Kozlowski 写道:
> On 28/08/2024 09:54, Lijuan Gao wrote:
>>
>>
>> 在 8/28/2024 2:25 PM, Krzysztof Kozlowski 写道:
>>> On Wed, Aug 28, 2024 at 10:02:16AM +0800, Lijuan Gao wrote:
>>>> Add initial support for Qualcomm QCS615 RIDE board and enable
>>>> the QCS615 RIDE board to shell with dcc console.
>>>>
>>>> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
>>>> ---
>>>>    arch/arm64/boot/dts/qcom/Makefile        |  1 +
>>>>    arch/arm64/boot/dts/qcom/qcs615-ride.dts | 15 +++++++++++++++
>>>>    2 files changed, 16 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>>>> index 197ab325c0b9..c5503f189847 100644
>>>> --- a/arch/arm64/boot/dts/qcom/Makefile
>>>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>>>> @@ -110,6 +110,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= qcm6490-idp.dtb
>>>>    dtb-$(CONFIG_ARCH_QCOM)	+= qcm6490-shift-otter.dtb
>>>>    dtb-$(CONFIG_ARCH_QCOM)	+= qcs404-evb-1000.dtb
>>>>    dtb-$(CONFIG_ARCH_QCOM)	+= qcs404-evb-4000.dtb
>>>> +dtb-$(CONFIG_ARCH_QCOM)	+= qcs615-ride.dtb
>>>>    dtb-$(CONFIG_ARCH_QCOM)	+= qcs6490-rb3gen2.dtb
>>>>    dtb-$(CONFIG_ARCH_QCOM)	+= qcs8550-aim300-aiot.dtb
>>>>    dtb-$(CONFIG_ARCH_QCOM)	+= qdu1000-idp.dtb
>>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
>>>> new file mode 100644
>>>> index 000000000000..31d32ad951b5
>>>> --- /dev/null
>>>> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
>>>> @@ -0,0 +1,15 @@
>>>> +// SPDX-License-Identifier: BSD-3-Clause
>>>> +/*
>>>> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
>>>> + */
>>>> +/dts-v1/;
>>>> +
>>>> +#include "qcs615.dtsi"
>>>> +/ {
>>>> +	model = "Qualcomm Technologies, Inc. QCS615 Ride";
>>>> +	compatible = "qcom,qcs615-ride", "qcom,qcs615";
>>>> +
>>>> +	chosen {
>>>> +		bootargs = "console=hvc0";
>>>
>>> Noooo, last time I agreed on this, you told me later it is different.
>>>
>> In the early stages, enabling HVC is to more easily verify clock and
>> PMIC related functions, as it’s difficult to debug without the console
>> log. After the clock and PMIC are ready, we will enable the UART console.
> 
> Working serial is supposed to be part of the early submission.
> 
Okay, I will remove it in the next patch.
> Best regards,
> Krzysztof
> 
> 

-- 
Thx and BRs
Lijuan Gao

Re: [PATCH 6/6] arm64: dts: qcom: add base QCS615 RIDE dts

[Krzysztof Kozlowski]

On 28/08/2024 11:31, Lijuan Gao wrote:
>>>>> +/ {
>>>>> +	model = "Qualcomm Technologies, Inc. QCS615 Ride";
>>>>> +	compatible = "qcom,qcs615-ride", "qcom,qcs615";
>>>>> +
>>>>> +	chosen {
>>>>> +		bootargs = "console=hvc0";
>>>>
>>>> Noooo, last time I agreed on this, you told me later it is different.
>>>>
>>> In the early stages, enabling HVC is to more easily verify clock and
>>> PMIC related functions, as it’s difficult to debug without the console
>>> log. After the clock and PMIC are ready, we will enable the UART console.
>>
>> Working serial is supposed to be part of the early submission.
>>
> Okay, I will remove it in the next patch.

Can you post next version with proper serial device?

Best regards,
Krzysztof

Re: [PATCH 6/6] arm64: dts: qcom: add base QCS615 RIDE dts

[Lijuan Gao]

在 8/28/2024 5:34 PM, Krzysztof Kozlowski 写道:
> On 28/08/2024 11:31, Lijuan Gao wrote:
>>>>>> +/ {
>>>>>> +	model = "Qualcomm Technologies, Inc. QCS615 Ride";
>>>>>> +	compatible = "qcom,qcs615-ride", "qcom,qcs615";
>>>>>> +
>>>>>> +	chosen {
>>>>>> +		bootargs = "console=hvc0";
>>>>>
>>>>> Noooo, last time I agreed on this, you told me later it is different.
>>>>>
>>>> In the early stages, enabling HVC is to more easily verify clock and
>>>> PMIC related functions, as it’s difficult to debug without the console
>>>> log. After the clock and PMIC are ready, we will enable the UART console.
>>>
>>> Working serial is supposed to be part of the early submission.
>>>
>> Okay, I will remove it in the next patch.
> 
> Can you post next version with proper serial device?
Well noted, will update in the next version.
> 
> Best regards,
> Krzysztof
> 

-- 
Thx and BRs
Lijuan Gao

Re: [PATCH 6/6] arm64: dts: qcom: add base QCS615 RIDE dts

[Konrad Dybcio]

On 28.08.2024 4:02 AM, Lijuan Gao wrote:
> Add initial support for Qualcomm QCS615 RIDE board and enable
> the QCS615 RIDE board to shell with dcc console.
> 
> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/Makefile        |  1 +
>  arch/arm64/boot/dts/qcom/qcs615-ride.dts | 15 +++++++++++++++
>  2 files changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 197ab325c0b9..c5503f189847 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -110,6 +110,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= qcm6490-idp.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= qcm6490-shift-otter.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= qcs404-evb-1000.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= qcs404-evb-4000.dtb
> +dtb-$(CONFIG_ARCH_QCOM)	+= qcs615-ride.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= qcs6490-rb3gen2.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= qcs8550-aim300-aiot.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= qdu1000-idp.dtb
> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> new file mode 100644
> index 000000000000..31d32ad951b5
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> @@ -0,0 +1,15 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +/dts-v1/;
> +
> +#include "qcs615.dtsi"
> +/ {
> +	model = "Qualcomm Technologies, Inc. QCS615 Ride";
> +	compatible = "qcom,qcs615-ride", "qcom,qcs615";

Missing chassis-type (probably = "embedded")

Konrad

Re: [PATCH 6/6] arm64: dts: qcom: add base QCS615 RIDE dts

[Lijuan Gao]

在 8/28/2024 5:34 PM, Krzysztof Kozlowski 写道:
> On 28/08/2024 11:31, Lijuan Gao wrote:
>>>>>> +/ {
>>>>>> +	model = "Qualcomm Technologies, Inc. QCS615 Ride";
>>>>>> +	compatible = "qcom,qcs615-ride", "qcom,qcs615";
>>>>>> +
>>>>>> +	chosen {
>>>>>> +		bootargs = "console=hvc0";
>>>>>
>>>>> Noooo, last time I agreed on this, you told me later it is different.
>>>>>
>>>> In the early stages, enabling HVC is to more easily verify clock and
>>>> PMIC related functions, as it’s difficult to debug without the console
>>>> log. After the clock and PMIC are ready, we will enable the UART console.
>>>
>>> Working serial is supposed to be part of the early submission.
>>>
>> Okay, I will remove it in the next patch.
> 
> Can you post next version with proper serial device?
> 
> Best regards,
> Krzysztof
> 
Hi Krzysztof,

Can we use the dts without console enabled as the first version? When 
the clock is ready, we will submit new changes to enable the UART console.

-- 
Thx and BRs
Lijuan Gao

Re: [PATCH 6/6] arm64: dts: qcom: add base QCS615 RIDE dts

[Krzysztof Kozlowski]

On 04/09/2024 10:35, Lijuan Gao wrote:
> 
> 
> 在 8/28/2024 5:34 PM, Krzysztof Kozlowski 写道:
>> On 28/08/2024 11:31, Lijuan Gao wrote:
>>>>>>> +/ {
>>>>>>> +	model = "Qualcomm Technologies, Inc. QCS615 Ride";
>>>>>>> +	compatible = "qcom,qcs615-ride", "qcom,qcs615";
>>>>>>> +
>>>>>>> +	chosen {
>>>>>>> +		bootargs = "console=hvc0";
>>>>>>
>>>>>> Noooo, last time I agreed on this, you told me later it is different.
>>>>>>
>>>>> In the early stages, enabling HVC is to more easily verify clock and
>>>>> PMIC related functions, as it’s difficult to debug without the console
>>>>> log. After the clock and PMIC are ready, we will enable the UART console.
>>>>
>>>> Working serial is supposed to be part of the early submission.
>>>>
>>> Okay, I will remove it in the next patch.
>>
>> Can you post next version with proper serial device?
>>
>> Best regards,
>> Krzysztof
>>
> Hi Krzysztof,
> 
> Can we use the dts without console enabled as the first version? When 
> the clock is ready, we will submit new changes to enable the UART console.

It is very surprising not to have console available in the first, early
submission, but it is not a blocker for me.

Best regards,
Krzysztof

Re: [PATCH 6/6] arm64: dts: qcom: add base QCS615 RIDE dts

[Konrad Dybcio]

On 4.09.2024 11:32 AM, Krzysztof Kozlowski wrote:
> On 04/09/2024 10:35, Lijuan Gao wrote:
>>
>>
>> 在 8/28/2024 5:34 PM, Krzysztof Kozlowski 写道:
>>> On 28/08/2024 11:31, Lijuan Gao wrote:
>>>>>>>> +/ {
>>>>>>>> +	model = "Qualcomm Technologies, Inc. QCS615 Ride";
>>>>>>>> +	compatible = "qcom,qcs615-ride", "qcom,qcs615";
>>>>>>>> +
>>>>>>>> +	chosen {
>>>>>>>> +		bootargs = "console=hvc0";
>>>>>>>
>>>>>>> Noooo, last time I agreed on this, you told me later it is different.
>>>>>>>
>>>>>> In the early stages, enabling HVC is to more easily verify clock and
>>>>>> PMIC related functions, as it’s difficult to debug without the console
>>>>>> log. After the clock and PMIC are ready, we will enable the UART console.
>>>>>
>>>>> Working serial is supposed to be part of the early submission.
>>>>>
>>>> Okay, I will remove it in the next patch.
>>>
>>> Can you post next version with proper serial device?
>>>
>>> Best regards,
>>> Krzysztof
>>>
>> Hi Krzysztof,
>>
>> Can we use the dts without console enabled as the first version? When 
>> the clock is ready, we will submit new changes to enable the UART console.
> 
> It is very surprising not to have console available in the first, early
> submission, but it is not a blocker for me.

Lijuan,

I see that the initial submission is very slim. GCC+UART+TLMM is
usually the smallest we tend to accept.

While hooking up these drivers may take some time, please consider
at least describing a subset of the clocks and the QUP UART, as
everything non-SoC-specific is already in place.

Konrad

Re: [PATCH 6/6] arm64: dts: qcom: add base QCS615 RIDE dts

[Aiqun Yu (Maria)]

On 9/4/2024 6:23 PM, Konrad Dybcio wrote:
> On 4.09.2024 11:32 AM, Krzysztof Kozlowski wrote:
>> On 04/09/2024 10:35, Lijuan Gao wrote:
>>>
>>>
>>> 在 8/28/2024 5:34 PM, Krzysztof Kozlowski 写道:
>>>> On 28/08/2024 11:31, Lijuan Gao wrote:
>>>>>>>>> +/ {
>>>>>>>>> +	model = "Qualcomm Technologies, Inc. QCS615 Ride";
>>>>>>>>> +	compatible = "qcom,qcs615-ride", "qcom,qcs615";
>>>>>>>>> +
>>>>>>>>> +	chosen {
>>>>>>>>> +		bootargs = "console=hvc0";
>>>>>>>>
>>>>>>>> Noooo, last time I agreed on this, you told me later it is different.
>>>>>>>>
>>>>>>> In the early stages, enabling HVC is to more easily verify clock and
>>>>>>> PMIC related functions, as it’s difficult to debug without the console
>>>>>>> log. After the clock and PMIC are ready, we will enable the UART console.
>>>>>>
>>>>>> Working serial is supposed to be part of the early submission.
>>>>>>
>>>>> Okay, I will remove it in the next patch.
>>>>
>>>> Can you post next version with proper serial device?
>>>>
>>>> Best regards,
>>>> Krzysztof
>>>>
>>> Hi Krzysztof,
>>>
>>> Can we use the dts without console enabled as the first version? When 
>>> the clock is ready, we will submit new changes to enable the UART console.
>>
>> It is very surprising not to have console available in the first, early
>> submission, but it is not a blocker for me.
> 
> Lijuan,
> 
> I see that the initial submission is very slim. GCC+UART+TLMM is
> usually the smallest we tend to accept.

We are exploring various ways to improve the efficiency of the upstream
change merge process. In the current QCS615 project, we are
experimenting with a slim "HVC console" verified base device tree to
minimize dependencies and enhance parallel work efficiency.

Currently, different developers are working on the same QCS615 project.
One developer is focusing on clock support for QCS615, another is
working on interconnect support, and a third is handling TLMM pinctrl
support. Additionally, the QUP UART validation depends on above soc
specific GCC clock/TLMM support.

Here is the proposed process chart for reference, Clock/TLMM, even other
functionality like LLCC can be validated apart from current Base support
with HVC console enabled:
                               +---------------+

                               | Clock         |

                               |               |

                               +---------------+

+---------------------+

|    Base support:    |        +---------------+       +-----+

| HVC console enabled |------> | TLMM          | ----->| UART|

+---------------------+        +---------------+       +-----+



                               +---------------+

                               | Interconnect  |

                               +---------------+


It is suggested to have process like this:
1. Have hvc console enabled base device tree support.
2. TLMM/GCC/Interconnect/LLCC/etc drivers can be pushed along with the
needful dt changes.
3. QUP uart support change after TLMM/GCC dependency uploaded.

Here is an original example of qcs8300 project that the base device tree
wait until have all qup uart enabled support for reference:
1. The first soc support[1] pushed at 08/14.
2. TLMM support[2] pushed at 08/19.
3. GCC clock support[3] pushed at 08/20.
4. Interconnect support[4] pushed at 08/27.
5. LLCC support[5] pushed at 09/03.
6. Initial device tree support[6] pushed at 09/04. And it have 5
co-developer in the initial device tree support.


[1]https://lore.kernel.org/all/20240814072806.4107079-1-quic_jingyw@quicinc.com/
[2]https://lore.kernel.org/all/20240819064933.1778204-1-quic_jingyw@quicinc.com/
[3]https://lore.kernel.org/all/20240820-qcs8300-gcc-v1-0-d81720517a82@quicinc.com/
[4]https://lore.kernel.org/all/20240827151622.305-1-quic_rlaggysh@quicinc.com/
[5]https://lore.kernel.org/all/20240903-qcs8300_llcc_driver-v1-0-228659bdf067@quicinc.com/
> 
> While hooking up these drivers may take some time, please consider
> at least describing a subset of the clocks and the QUP UART, as
> everything non-SoC-specific is already in place.

To be more specific, are you suggesting like adding the base device tree
describing with current nodes subset which only have non-soc-specific
info, like:
1. "apps_rsc" nodes without info of
"qcom,qcs615-rpmh-clk","qcom,qcs615-gcc"?
2."qcom,geni-debug-uart" nodes description without the clock properties?

> 
> Konrad

-- 
Thx and BRs,
Aiqun(Maria) Yu

Re: [PATCH 6/6] arm64: dts: qcom: add base QCS615 RIDE dts

[Konrad Dybcio]

On 5.09.2024 7:29 AM, Aiqun Yu (Maria) wrote:
> 
> 
> On 9/4/2024 6:23 PM, Konrad Dybcio wrote:
>> On 4.09.2024 11:32 AM, Krzysztof Kozlowski wrote:
>>> On 04/09/2024 10:35, Lijuan Gao wrote:
>>>>
>>>>
>>>> 在 8/28/2024 5:34 PM, Krzysztof Kozlowski 写道:
>>>>> On 28/08/2024 11:31, Lijuan Gao wrote:
>>>>>>>>>> +/ {
>>>>>>>>>> +	model = "Qualcomm Technologies, Inc. QCS615 Ride";
>>>>>>>>>> +	compatible = "qcom,qcs615-ride", "qcom,qcs615";
>>>>>>>>>> +
>>>>>>>>>> +	chosen {
>>>>>>>>>> +		bootargs = "console=hvc0";
>>>>>>>>>
>>>>>>>>> Noooo, last time I agreed on this, you told me later it is different.
>>>>>>>>>
>>>>>>>> In the early stages, enabling HVC is to more easily verify clock and
>>>>>>>> PMIC related functions, as it’s difficult to debug without the console
>>>>>>>> log. After the clock and PMIC are ready, we will enable the UART console.
>>>>>>>
>>>>>>> Working serial is supposed to be part of the early submission.
>>>>>>>
>>>>>> Okay, I will remove it in the next patch.
>>>>>
>>>>> Can you post next version with proper serial device?
>>>>>
>>>>> Best regards,
>>>>> Krzysztof
>>>>>
>>>> Hi Krzysztof,
>>>>
>>>> Can we use the dts without console enabled as the first version? When 
>>>> the clock is ready, we will submit new changes to enable the UART console.
>>>
>>> It is very surprising not to have console available in the first, early
>>> submission, but it is not a blocker for me.
>>
>> Lijuan,
>>
>> I see that the initial submission is very slim. GCC+UART+TLMM is
>> usually the smallest we tend to accept.
> 
> We are exploring various ways to improve the efficiency of the upstream
> change merge process. In the current QCS615 project, we are
> experimenting with a slim "HVC console" verified base device tree to
> minimize dependencies and enhance parallel work efficiency.
> 
> Currently, different developers are working on the same QCS615 project.
> One developer is focusing on clock support for QCS615, another is
> working on interconnect support, and a third is handling TLMM pinctrl
> support. Additionally, the QUP UART validation depends on above soc
> specific GCC clock/TLMM support.
> 
> Here is the proposed process chart for reference, Clock/TLMM, even other
> functionality like LLCC can be validated apart from current Base support
> with HVC console enabled:
>                                +---------------+
> 
>                                | Clock         |
> 
>                                |               |
> 
>                                +---------------+
> 
> +---------------------+
> 
> |    Base support:    |        +---------------+       +-----+
> 
> | HVC console enabled |------> | TLMM          | ----->| UART|
> 
> +---------------------+        +---------------+       +-----+
> 
> 
> 
>                                +---------------+
> 
>                                | Interconnect  |
> 
>                                +---------------+
> 
> 
> It is suggested to have process like this:
> 1. Have hvc console enabled base device tree support.
> 2. TLMM/GCC/Interconnect/LLCC/etc drivers can be pushed along with the
> needful dt changes.
> 3. QUP uart support change after TLMM/GCC dependency uploaded.
> 
> Here is an original example of qcs8300 project that the base device tree
> wait until have all qup uart enabled support for reference:
> 1. The first soc support[1] pushed at 08/14.
> 2. TLMM support[2] pushed at 08/19.
> 3. GCC clock support[3] pushed at 08/20.
> 4. Interconnect support[4] pushed at 08/27.
> 5. LLCC support[5] pushed at 09/03.
> 6. Initial device tree support[6] pushed at 09/04. And it have 5
> co-developer in the initial device tree support.

Right, plumbing up all of the UART dependencies properly on these
platforms is very much not straightforward.

> 
> 
> [1]https://lore.kernel.org/all/20240814072806.4107079-1-quic_jingyw@quicinc.com/
> [2]https://lore.kernel.org/all/20240819064933.1778204-1-quic_jingyw@quicinc.com/
> [3]https://lore.kernel.org/all/20240820-qcs8300-gcc-v1-0-d81720517a82@quicinc.com/
> [4]https://lore.kernel.org/all/20240827151622.305-1-quic_rlaggysh@quicinc.com/
> [5]https://lore.kernel.org/all/20240903-qcs8300_llcc_driver-v1-0-228659bdf067@quicinc.com/
>>
>> While hooking up these drivers may take some time, please consider
>> at least describing a subset of the clocks and the QUP UART, as
>> everything non-SoC-specific is already in place.
> 
> To be more specific, are you suggesting like adding the base device tree
> describing with current nodes subset which only have non-soc-specific
> info, like:
> 1. "apps_rsc" nodes without info of
> "qcom,qcs615-rpmh-clk","qcom,qcs615-gcc"?
> 2."qcom,geni-debug-uart" nodes description without the clock properties?

When writing that email, I thought about sending a small version of the
GCC driver with just enough to turn on the UART clocks, but thinking
about it again, that sounds like a really bad idea..

I think it's best if we stick to what you did in this patch, and validate
things with `earlycon=qcom_geni,0xaddress` in cmdline. This way, we can
take advantage of the bootloader setting it up for us.

You could then include the base address of the serial engine in the
commit message to let others reproduce it easily.

Krzysztof, would you agree ^?

Konrad