From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5665420C001; Tue, 12 Aug 2025 06:37:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754980630; cv=none; b=mlSGMCRYpa8HvJTGp3zcKpVQW2ey8E62r/Rxt5vNyju+1mBdBub8fIZLOjhOuO2NQzpx0GX05PW1mU9BYP2mxYKmHAwSBOF62dQX2oDzIg0FGuxuaWWK7mWkmeXeIcKeHaaKTgcYhOEC7iaraEDecuwatBMM1HDscxXPPkf8+Gs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754980630; c=relaxed/simple; bh=DN6AGEd04LkeapvqxKCW4A0HOrkg6SVHzX1aPEHJMg4=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=eY+ZmlY+v+hMUd3jl0lko7QuyrOCSWk6ZdqAzncyGxytQB9q7NIBNWaahfxvZqorHmPm1cpfdXL035y4h0h9K79TiEdW8rq9lCYhlKEImbiPEHa9ZwCYCUXZDYLJumOPa8Y3FKAjkJox29OdKqxJpnjIfjldUjrBykmLCxecNwU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Gph698/U; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Gph698/U" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2CD51C4CEF6; Tue, 12 Aug 2025 06:37:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754980629; bh=DN6AGEd04LkeapvqxKCW4A0HOrkg6SVHzX1aPEHJMg4=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=Gph698/U/m7daZax4mS3+51vt1C9rQ9Mamx5EA5uZCz7i4FjgS1W1yAHXO1f+DUuY lKd09pCOkuV2Zq6yb34rbDJhqrgcf6I8RibJK2BTg6HBI5X88G6OU2zYsa9F6FBOE+ Fgu9YgiZ5HAJP7uxJHA/6GS05BOfQSPxH5Gs6kD1ChExQ0yZzn3TVgT2Zpw2cGLj+5 C+//TlTmtstVLyEDsnGy/R5CSouGaRTFONYT99GkQHp9PFRbXQCD0cCOUotpnqN2xA GAF0a6YIMfZZCdULb05B6MYayw25wL4sQ6KO/iY+is0j5tOT7kAw0pl+O0xgmFbC5M BoCkxKBH/IMgw== Message-ID: <9e065582-9349-4f39-88b5-048d333ab8d7@kernel.org> Date: Tue, 12 Aug 2025 08:37:02 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 07/12] dt-bindings: PCI: Add support for Tesla FSD SoC To: Shradha Todi , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, pankaj.dubey@samsung.com References: <20250811154638.95732-1-shradha.t@samsung.com> <20250811154638.95732-8-shradha.t@samsung.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 11/08/2025 17:46, Shradha Todi wrote: > + > + clocks: > + maxItems: 4 > + > + clock-names: > + items: > + - const: aux > + - const: dbi > + - const: mstr > + - const: slv > + > + num-lanes: > + maximum: 4 > + > + phys: > + maxItems: 1 > + > + samsung,syscon-pcie: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: phandle for system control registers, used to > + control signals at system level What is "system level"? and what are these "signals" being controlled? > + > +required: > + - compatible > + - reg > + - reg-names > + - clocks > + - clock-names > + - num-lanes > + - phys > + - samsung,syscon-pcie > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include > + #include > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + pcieep0: pcie-ep@16a00000 { > + compatible = "tesla,fsd-pcie-ep"; > + reg = <0x0 0x168b0000 0x0 0x1000>, > + <0x0 0x16a00000 0x0 0x2000>, > + <0x0 0x16a01000 0x0 0x80>, > + <0x0 0x17000000 0x0 0xff0000>; > + reg-names = "elbi", "dbi", "dbi2", "addr_space"; > + clocks = <&clock_fsys1 PCIE_LINK0_IPCLKPORT_AUX_ACLK>, > + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_DBI_ACLK>, > + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_MSTR_ACLK>, > + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_SLV_ACLK>; > + clock-names = "aux", "dbi", "mstr", "slv"; > + num-lanes = <4>; > + phys = <&pciephy1>; > + samsung,syscon-pcie = <&sysreg_fsys1 0x50c>; > + }; > + }; > +... > diff --git a/Documentation/devicetree/bindings/pci/tesla,fsd-pcie.yaml b/Documentation/devicetree/bindings/pci/tesla,fsd-pcie.yaml > new file mode 100644 > index 000000000000..533870ab1d73 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/tesla,fsd-pcie.yaml > @@ -0,0 +1,77 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/tesla,fsd-pcie.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Tesla FSD SoC series PCIe Host Controller > + > +maintainers: > + - Shradha Todi > + > +description: > + Tesla FSD SoCs PCIe host controller inherits all the common > + properties defined in samsung,exynos-pcie.yaml > + > +allOf: > + - $ref: /schemas/pci/samsung,exynos-pcie.yaml# > + > +properties: > + compatible: > + const: tesla,fsd-pcie > + > + clocks: > + maxItems: 4 > + > + clock-names: > + items: > + - const: aux > + - const: dbi > + - const: mstr > + - const: slv > + > + num-lanes: > + maximum: 4 > + > + samsung,syscon-pcie: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: phandle for system control registers, used to > + control signals at system level > + > +required: > + - samsung,syscon-pcie clocks are required, compatible as well. Missing supplies, both as properties and required. PCI devices do not work without power. > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include > + #include > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pcierc1: pcie@16b00000 { > + compatible = "tesla,fsd-pcie"; > + reg = <0x0 0x16b00000 0x0 0x2000>, > + <0x0 0x168c0000 0x0 0x1000>, > + <0x0 0x18000000 0x0 0x1000>; > + reg-names = "dbi", "elbi", "config"; > + ranges = <0x82000000 0x0 0x18001000 0x0 0x18001000 0x0 0xffefff>; Misaligned. Follow closely DTS coding style. > + clocks = <&clock_fsys1 PCIE_LINK1_IPCLKPORT_AUX_ACLK>, > + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_DBI_ACLK>, > + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_MSTR_ACLK>, > + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_SLV_ACLK>; > + clock-names = "aux", "dbi", "mstr", "slv"; > + #address-cells = <3>; > + #size-cells = <2>; > + dma-coherent; > + device_type = "pci"; > + interrupts = ; > + num-lanes = <4>; > + phys = <&pciephy1>; > + samsung,syscon-pcie = <&sysreg_fsys1 0x510>; Incomplete, missing supplies. > + }; > + }; > +... Best regards, Krzysztof