[PATCH 0/3] Add APSS clock driver support for IPQ5018

[PATCH 0/3] Add APSS clock driver support for IPQ5018

[Gokul Sriram Palanisamy]

This series adds support for the APSS clock to bump the CPU frequency
above 800MHz. APSS PLL found in the IPQ5018 is of type Stromer. 

- The first patch in the series adds the required a53pll compatible.

- The second patch adds Stormer PLL offsets, its configuration values and
regmap and modify probe to reuse clk_stromer_pll_configure() for Stormer
which was added for Stormer Plus.

- The third patch adds dts nodes to enable the pll along with the cpu
operating frequency table.

Gokul Sriram Palanisamy (3):
  dt-bindings: clock: qcom,a53pll: add IPQ5018 compatible
  clk: qcom: apss-ipq-pll: add support for IPQ5018
  arm64: dts: qcom: ipq5018: enable the CPUFreq support

 .../bindings/clock/qcom,a53pll.yaml           |  1 +
 arch/arm64/boot/dts/qcom/ipq5018.dtsi         | 34 ++++++++++++
 drivers/clk/qcom/apss-ipq-pll.c               | 52 ++++++++++++++++++-
 3 files changed, 86 insertions(+), 1 deletion(-)

-- 
2.34.1

[PATCH 1/3] dt-bindings: clock: qcom,a53pll: add IPQ5018 compatible

[Gokul Sriram Palanisamy]

Add IPQ5018 compatible to A53 PLL bindings.

Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
---
 Documentation/devicetree/bindings/clock/qcom,a53pll.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
index 9436266828af..5ca927a8b1d5 100644
--- a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
@@ -16,6 +16,7 @@ description:
 properties:
   compatible:
     enum:
+      - qcom,ipq5018-a53pll
       - qcom,ipq5332-a53pll
       - qcom,ipq6018-a53pll
       - qcom,ipq8074-a53pll
-- 
2.34.1

[PATCH 2/3] clk: qcom: apss-ipq-pll: add support for IPQ5018

[Gokul Sriram Palanisamy]

IPQ5018 APSS PLL is of type Stromer. Add support for Stromer PLL,
configuration values and the compatible.

Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
---
 drivers/clk/qcom/apss-ipq-pll.c | 52 ++++++++++++++++++++++++++++++++-
 1 file changed, 51 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
index e170331858cc..bbc25d5eb70d 100644
--- a/drivers/clk/qcom/apss-ipq-pll.c
+++ b/drivers/clk/qcom/apss-ipq-pll.c
@@ -24,6 +24,17 @@ static const u8 ipq_pll_offsets[][PLL_OFF_MAX_REGS] = {
 		[PLL_OFF_TEST_CTL] = 0x30,
 		[PLL_OFF_TEST_CTL_U] = 0x34,
 	},
+	[CLK_ALPHA_PLL_TYPE_STROMER] = {
+		[PLL_OFF_L_VAL] = 0x08,
+		[PLL_OFF_ALPHA_VAL] = 0x10,
+		[PLL_OFF_ALPHA_VAL_U] = 0x14,
+		[PLL_OFF_USER_CTL] = 0x18,
+		[PLL_OFF_USER_CTL_U] = 0x1c,
+		[PLL_OFF_CONFIG_CTL] = 0x20,
+		[PLL_OFF_STATUS] = 0x28,
+		[PLL_OFF_TEST_CTL] = 0x30,
+		[PLL_OFF_TEST_CTL_U] = 0x34,
+	},
 	[CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {
 		[PLL_OFF_L_VAL] = 0x08,
 		[PLL_OFF_ALPHA_VAL] = 0x10,
@@ -73,6 +84,38 @@ static struct clk_alpha_pll ipq_pll_stromer_plus = {
 	},
 };
 
+static struct clk_alpha_pll ipq_pll_stromer = {
+	.offset = 0x0,
+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER],
+	.flags = SUPPORTS_DYNAMIC_UPDATE,
+	.clkr = {
+		.enable_reg = 0x0,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "a53pll",
+			.parent_data = &(const struct clk_parent_data) {
+				.fw_name = "xo",
+			},
+			.num_parents = 1,
+			.ops = &clk_alpha_pll_stromer_ops,
+		},
+	},
+};
+
+static const struct alpha_pll_config ipq5018_pll_config = {
+	.l = 0x32,
+	.config_ctl_val = 0x4001075b,
+	.config_ctl_hi_val = 0x304,
+	.main_output_mask = BIT(0),
+	.aux_output_mask = BIT(1),
+	.early_output_mask = BIT(3),
+	.alpha_en_mask = BIT(24),
+	.status_val = 0x3,
+	.status_mask = GENMASK(10, 8),
+	.lock_det = BIT(2),
+	.test_ctl_hi_val = 0x00400003,
+};
+
 static const struct alpha_pll_config ipq5332_pll_config = {
 	.l = 0x3e,
 	.config_ctl_val = 0x4001075b,
@@ -129,6 +172,12 @@ struct apss_pll_data {
 	const struct alpha_pll_config *pll_config;
 };
 
+static struct apss_pll_data ipq5018_pll_data = {
+	.pll_type = CLK_ALPHA_PLL_TYPE_STROMER,
+	.pll = &ipq_pll_stromer,
+	.pll_config = &ipq5018_pll_config,
+};
+
 static struct apss_pll_data ipq5332_pll_data = {
 	.pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
 	.pll = &ipq_pll_stromer_plus,
@@ -183,7 +232,7 @@ static int apss_ipq_pll_probe(struct platform_device *pdev)
 
 	if (data->pll_type == CLK_ALPHA_PLL_TYPE_HUAYRA)
 		clk_alpha_pll_configure(data->pll, regmap, data->pll_config);
-	else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS)
+	else
 		clk_stromer_pll_configure(data->pll, regmap, data->pll_config);
 
 	ret = devm_clk_register_regmap(dev, &data->pll->clkr);
@@ -195,6 +244,7 @@ static int apss_ipq_pll_probe(struct platform_device *pdev)
 }
 
 static const struct of_device_id apss_ipq_pll_match_table[] = {
+	{ .compatible = "qcom,ipq5018-a53pll", .data = &ipq5018_pll_data },
 	{ .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data },
 	{ .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data },
 	{ .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data },
-- 
2.34.1

[PATCH 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support

[Gokul Sriram Palanisamy]

Add the APCS, A53 PLL, cpu-opp-table nodes to set
the CPU frequency at optimal range.

Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
---
 arch/arm64/boot/dts/qcom/ipq5018.dtsi | 34 +++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index 9f13d2dcdfd5..05843517312c 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
 #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
+#include <dt-bindings/clock/qcom,apss-ipq.h>
 
 / {
 	interrupt-parent = <&intc>;
@@ -36,6 +37,8 @@ CPU0: cpu@0 {
 			reg = <0x0>;
 			enable-method = "psci";
 			next-level-cache = <&L2_0>;
+			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+			operating-points-v2 = <&cpu_opp_table>;
 		};
 
 		CPU1: cpu@1 {
@@ -44,6 +47,8 @@ CPU1: cpu@1 {
 			reg = <0x1>;
 			enable-method = "psci";
 			next-level-cache = <&L2_0>;
+			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+			operating-points-v2 = <&cpu_opp_table>;
 		};
 
 		L2_0: l2-cache {
@@ -54,6 +59,17 @@ L2_0: l2-cache {
 		};
 	};
 
+	cpu_opp_table: opp-table-cpu {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-1008000000 {
+			opp-hz = /bits/ 64 <1008000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <200000>;
+		};
+	};
+
 	firmware {
 		scm {
 			compatible = "qcom,scm-ipq5018", "qcom,scm";
@@ -181,6 +197,24 @@ v2m1: v2m@1000 {
 			};
 		};
 
+		a53pll: clock@b116000 {
+			compatible = "qcom,ipq5018-a53pll";
+			reg = <0x0b116000 0x40>;
+			#clock-cells = <0>;
+			clocks = <&xo_board_clk>;
+			clock-names = "xo";
+		};
+
+		apcs_glb: mailbox@b111000 {
+			compatible = "qcom,ipq5018-apcs-apps-global",
+				     "qcom,ipq6018-apcs-apps-global";
+			reg = <0x0b111000 0x1000>;
+			#clock-cells = <1>;
+			clocks = <&a53pll>, <&xo_board_clk>;
+			clock-names = "pll", "xo";
+			#mbox-cells = <1>;
+		};
+
 		timer@b120000 {
 			compatible = "arm,armv7-timer-mem";
 			reg = <0x0b120000 0x1000>;
-- 
2.34.1

Re: [PATCH 1/3] dt-bindings: clock: qcom,a53pll: add IPQ5018 compatible

[Krzysztof Kozlowski]

On 29/08/2023 11:54, Gokul Sriram Palanisamy wrote:
> Add IPQ5018 compatible to A53 PLL bindings.
> 
> Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>

Knowing that this patch could not come from downstream (it's some old
kernel without this file), I really wonder why two people were involved
in developing trivial one line change.

> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support

[Krzysztof Kozlowski]

On 29/08/2023 11:54, Gokul Sriram Palanisamy wrote:
> Add the APCS, A53 PLL, cpu-opp-table nodes to set
> the CPU frequency at optimal range.
> 
> Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/ipq5018.dtsi | 34 +++++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> index 9f13d2dcdfd5..05843517312c 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> @@ -8,6 +8,7 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
>  #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
> +#include <dt-bindings/clock/qcom,apss-ipq.h>

c is before r.

>  
>  / {
>  	interrupt-parent = <&intc>;
> @@ -36,6 +37,8 @@ CPU0: cpu@0 {
>  			reg = <0x0>;
>  			enable-method = "psci";
>  			next-level-cache = <&L2_0>;
> +			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> +			operating-points-v2 = <&cpu_opp_table>;
>  		};
>  
>  		CPU1: cpu@1 {
> @@ -44,6 +47,8 @@ CPU1: cpu@1 {
>  			reg = <0x1>;
>  			enable-method = "psci";
>  			next-level-cache = <&L2_0>;
> +			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> +			operating-points-v2 = <&cpu_opp_table>;
>  		};
>  
>  		L2_0: l2-cache {
> @@ -54,6 +59,17 @@ L2_0: l2-cache {
>  		};
>  	};
>  
> +	cpu_opp_table: opp-table-cpu {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp-1008000000 {
> +			opp-hz = /bits/ 64 <1008000000>;
> +			opp-microvolt = <1100000>;
> +			clock-latency-ns = <200000>;

And the rest of OPPs?

> +		};
> +	};
> +
>  	firmware {
>  		scm {
>  			compatible = "qcom,scm-ipq5018", "qcom,scm";
> @@ -181,6 +197,24 @@ v2m1: v2m@1000 {
>  			};
>  		};
>  
> +		a53pll: clock@b116000 {
> +			compatible = "qcom,ipq5018-a53pll";
> +			reg = <0x0b116000 0x40>;
> +			#clock-cells = <0>;
> +			clocks = <&xo_board_clk>;
> +			clock-names = "xo";
> +		};
> +
> +		apcs_glb: mailbox@b111000 {

0xb111000 looks lower than 0x116000.

> +			compatible = "qcom,ipq5018-apcs-apps-global",
> +				     "qcom,ipq6018-apcs-apps-global";
> +			reg = <0x0b111000 0x1000>;

Best regards,
Krzysztof

Re: [PATCH 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support

[Robert Marko]

On 29. 08. 2023. 12:12, Krzysztof Kozlowski wrote:
> On 29/08/2023 11:54, Gokul Sriram Palanisamy wrote:
>> Add the APCS, A53 PLL, cpu-opp-table nodes to set
>> the CPU frequency at optimal range.
>>
>> Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/ipq5018.dtsi | 34 +++++++++++++++++++++++++++
>>   1 file changed, 34 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> index 9f13d2dcdfd5..05843517312c 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> @@ -8,6 +8,7 @@
>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>>   #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
>>   #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
>> +#include <dt-bindings/clock/qcom,apss-ipq.h>
> c is before r.
>
>>   
>>   / {
>>   	interrupt-parent = <&intc>;
>> @@ -36,6 +37,8 @@ CPU0: cpu@0 {
>>   			reg = <0x0>;
>>   			enable-method = "psci";
>>   			next-level-cache = <&L2_0>;
>> +			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>> +			operating-points-v2 = <&cpu_opp_table>;
>>   		};
>>   
>>   		CPU1: cpu@1 {
>> @@ -44,6 +47,8 @@ CPU1: cpu@1 {
>>   			reg = <0x1>;
>>   			enable-method = "psci";
>>   			next-level-cache = <&L2_0>;
>> +			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>> +			operating-points-v2 = <&cpu_opp_table>;
>>   		};
>>   
>>   		L2_0: l2-cache {
>> @@ -54,6 +59,17 @@ L2_0: l2-cache {
>>   		};
>>   	};
>>   
>> +	cpu_opp_table: opp-table-cpu {
>> +		compatible = "operating-points-v2";
>> +		opp-shared;
>> +
>> +		opp-1008000000 {
>> +			opp-hz = /bits/ 64 <1008000000>;
>> +			opp-microvolt = <1100000>;
>> +			clock-latency-ns = <200000>;
> And the rest of OPPs?
Hi Krzysztof,
IPQ5018 only supports running at 1.1GHz, but its running at 800MHz
by default from the bootloader so there is only one OPP.

I am glad to see more SoC-s gaining CPUFreq support.

Regards,
Robert
>
>> +		};
>> +	};
>> +
>>   	firmware {
>>   		scm {
>>   			compatible = "qcom,scm-ipq5018", "qcom,scm";
>> @@ -181,6 +197,24 @@ v2m1: v2m@1000 {
>>   			};
>>   		};
>>   
>> +		a53pll: clock@b116000 {
>> +			compatible = "qcom,ipq5018-a53pll";
>> +			reg = <0x0b116000 0x40>;
>> +			#clock-cells = <0>;
>> +			clocks = <&xo_board_clk>;
>> +			clock-names = "xo";
>> +		};
>> +
>> +		apcs_glb: mailbox@b111000 {
> 0xb111000 looks lower than 0x116000.
>
>> +			compatible = "qcom,ipq5018-apcs-apps-global",
>> +				     "qcom,ipq6018-apcs-apps-global";
>> +			reg = <0x0b111000 0x1000>;
> Best regards,
> Krzysztof
>
>
>

Re: [PATCH 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support

[Dmitry Baryshkov]

On Tue, 29 Aug 2023 at 13:59, Robert Marko <robimarko@gmail.com> wrote:
>
>
> On 29. 08. 2023. 12:12, Krzysztof Kozlowski wrote:
> > On 29/08/2023 11:54, Gokul Sriram Palanisamy wrote:
> >> Add the APCS, A53 PLL, cpu-opp-table nodes to set
> >> the CPU frequency at optimal range.
> >>
> >> Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> >> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> >> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
> >> ---
> >>   arch/arm64/boot/dts/qcom/ipq5018.dtsi | 34 +++++++++++++++++++++++++++
> >>   1 file changed, 34 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> >> index 9f13d2dcdfd5..05843517312c 100644
> >> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> >> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> >> @@ -8,6 +8,7 @@
> >>   #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>   #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
> >>   #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
> >> +#include <dt-bindings/clock/qcom,apss-ipq.h>
> > c is before r.
> >
> >>
> >>   / {
> >>      interrupt-parent = <&intc>;
> >> @@ -36,6 +37,8 @@ CPU0: cpu@0 {
> >>                      reg = <0x0>;
> >>                      enable-method = "psci";
> >>                      next-level-cache = <&L2_0>;
> >> +                    clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> >> +                    operating-points-v2 = <&cpu_opp_table>;
> >>              };
> >>
> >>              CPU1: cpu@1 {
> >> @@ -44,6 +47,8 @@ CPU1: cpu@1 {
> >>                      reg = <0x1>;
> >>                      enable-method = "psci";
> >>                      next-level-cache = <&L2_0>;
> >> +                    clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> >> +                    operating-points-v2 = <&cpu_opp_table>;
> >>              };
> >>
> >>              L2_0: l2-cache {
> >> @@ -54,6 +59,17 @@ L2_0: l2-cache {
> >>              };
> >>      };
> >>
> >> +    cpu_opp_table: opp-table-cpu {
> >> +            compatible = "operating-points-v2";
> >> +            opp-shared;
> >> +
> >> +            opp-1008000000 {
> >> +                    opp-hz = /bits/ 64 <1008000000>;
> >> +                    opp-microvolt = <1100000>;
> >> +                    clock-latency-ns = <200000>;
> > And the rest of OPPs?
> Hi Krzysztof,
> IPQ5018 only supports running at 1.1GHz, but its running at 800MHz
> by default from the bootloader so there is only one OPP.

If the bootloader sets it to 800 MHz, then this frequency is also
somehow 'supported', isn't it?

> I am glad to see more SoC-s gaining CPUFreq support.

Definitely.

>
> Regards,
> Robert
> >
> >> +            };
> >> +    };
> >> +
> >>      firmware {
> >>              scm {
> >>                      compatible = "qcom,scm-ipq5018", "qcom,scm";
> >> @@ -181,6 +197,24 @@ v2m1: v2m@1000 {
> >>                      };
> >>              };
> >>
> >> +            a53pll: clock@b116000 {
> >> +                    compatible = "qcom,ipq5018-a53pll";
> >> +                    reg = <0x0b116000 0x40>;
> >> +                    #clock-cells = <0>;
> >> +                    clocks = <&xo_board_clk>;
> >> +                    clock-names = "xo";
> >> +            };
> >> +
> >> +            apcs_glb: mailbox@b111000 {
> > 0xb111000 looks lower than 0x116000.
> >
> >> +                    compatible = "qcom,ipq5018-apcs-apps-global",
> >> +                                 "qcom,ipq6018-apcs-apps-global";
> >> +                    reg = <0x0b111000 0x1000>;
> > Best regards,
> > Krzysztof
> >
> >
> >



-- 
With best wishes
Dmitry

Re: [PATCH 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support

[Krzysztof Kozlowski]

On 29/08/2023 12:56, Robert Marko wrote:
> 
> On 29. 08. 2023. 12:12, Krzysztof Kozlowski wrote:
>> On 29/08/2023 11:54, Gokul Sriram Palanisamy wrote:
>>> Add the APCS, A53 PLL, cpu-opp-table nodes to set
>>> the CPU frequency at optimal range.
>>>
>>> Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>>> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
>>> ---
>>>   arch/arm64/boot/dts/qcom/ipq5018.dtsi | 34 +++++++++++++++++++++++++++
>>>   1 file changed, 34 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>>> index 9f13d2dcdfd5..05843517312c 100644
>>> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>>> @@ -8,6 +8,7 @@
>>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>   #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
>>>   #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
>>> +#include <dt-bindings/clock/qcom,apss-ipq.h>
>> c is before r.
>>
>>>   
>>>   / {
>>>   	interrupt-parent = <&intc>;
>>> @@ -36,6 +37,8 @@ CPU0: cpu@0 {
>>>   			reg = <0x0>;
>>>   			enable-method = "psci";
>>>   			next-level-cache = <&L2_0>;
>>> +			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>>> +			operating-points-v2 = <&cpu_opp_table>;
>>>   		};
>>>   
>>>   		CPU1: cpu@1 {
>>> @@ -44,6 +47,8 @@ CPU1: cpu@1 {
>>>   			reg = <0x1>;
>>>   			enable-method = "psci";
>>>   			next-level-cache = <&L2_0>;
>>> +			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>>> +			operating-points-v2 = <&cpu_opp_table>;
>>>   		};
>>>   
>>>   		L2_0: l2-cache {
>>> @@ -54,6 +59,17 @@ L2_0: l2-cache {
>>>   		};
>>>   	};
>>>   
>>> +	cpu_opp_table: opp-table-cpu {
>>> +		compatible = "operating-points-v2";
>>> +		opp-shared;
>>> +
>>> +		opp-1008000000 {
>>> +			opp-hz = /bits/ 64 <1008000000>;
>>> +			opp-microvolt = <1100000>;
>>> +			clock-latency-ns = <200000>;
>> And the rest of OPPs?
> Hi Krzysztof,
> IPQ5018 only supports running at 1.1GHz, but its running at 800MHz
> by default from the bootloader so there is only one OPP.

Isn't this contradictory? If it is running at 800 initially, then it
supports running at 800...


Best regards,
Krzysztof

Re: [PATCH 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support

[Robert Marko]

On Tue, 29 Aug 2023 at 13:10, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 29/08/2023 12:56, Robert Marko wrote:
> >
> > On 29. 08. 2023. 12:12, Krzysztof Kozlowski wrote:
> >> On 29/08/2023 11:54, Gokul Sriram Palanisamy wrote:
> >>> Add the APCS, A53 PLL, cpu-opp-table nodes to set
> >>> the CPU frequency at optimal range.
> >>>
> >>> Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> >>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> >>> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
> >>> ---
> >>>   arch/arm64/boot/dts/qcom/ipq5018.dtsi | 34 +++++++++++++++++++++++++++
> >>>   1 file changed, 34 insertions(+)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> >>> index 9f13d2dcdfd5..05843517312c 100644
> >>> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> >>> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> >>> @@ -8,6 +8,7 @@
> >>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>>   #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
> >>>   #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
> >>> +#include <dt-bindings/clock/qcom,apss-ipq.h>
> >> c is before r.
> >>
> >>>
> >>>   / {
> >>>     interrupt-parent = <&intc>;
> >>> @@ -36,6 +37,8 @@ CPU0: cpu@0 {
> >>>                     reg = <0x0>;
> >>>                     enable-method = "psci";
> >>>                     next-level-cache = <&L2_0>;
> >>> +                   clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> >>> +                   operating-points-v2 = <&cpu_opp_table>;
> >>>             };
> >>>
> >>>             CPU1: cpu@1 {
> >>> @@ -44,6 +47,8 @@ CPU1: cpu@1 {
> >>>                     reg = <0x1>;
> >>>                     enable-method = "psci";
> >>>                     next-level-cache = <&L2_0>;
> >>> +                   clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> >>> +                   operating-points-v2 = <&cpu_opp_table>;
> >>>             };
> >>>
> >>>             L2_0: l2-cache {
> >>> @@ -54,6 +59,17 @@ L2_0: l2-cache {
> >>>             };
> >>>     };
> >>>
> >>> +   cpu_opp_table: opp-table-cpu {
> >>> +           compatible = "operating-points-v2";
> >>> +           opp-shared;
> >>> +
> >>> +           opp-1008000000 {
> >>> +                   opp-hz = /bits/ 64 <1008000000>;
> >>> +                   opp-microvolt = <1100000>;
> >>> +                   clock-latency-ns = <200000>;
> >> And the rest of OPPs?
> > Hi Krzysztof,
> > IPQ5018 only supports running at 1.1GHz, but its running at 800MHz
> > by default from the bootloader so there is only one OPP.
>
> Isn't this contradictory? If it is running at 800 initially, then it
> supports running at 800...

I can only guess that it's not validated at 800MHz.

Regards,
Robert
>
>
> Best regards,
> Krzysztof
>

Re: [PATCH 2/3] clk: qcom: apss-ipq-pll: add support for IPQ5018

[Stephen Boyd]

Quoting Gokul Sriram Palanisamy (2023-08-29 02:54:22)
> diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
> index e170331858cc..bbc25d5eb70d 100644
> --- a/drivers/clk/qcom/apss-ipq-pll.c
> +++ b/drivers/clk/qcom/apss-ipq-pll.c
> @@ -24,6 +24,17 @@ static const u8 ipq_pll_offsets[][PLL_OFF_MAX_REGS] = {
>                 [PLL_OFF_TEST_CTL] = 0x30,
>                 [PLL_OFF_TEST_CTL_U] = 0x34,
>         },
> +       [CLK_ALPHA_PLL_TYPE_STROMER] = {
> +               [PLL_OFF_L_VAL] = 0x08,
> +               [PLL_OFF_ALPHA_VAL] = 0x10,
> +               [PLL_OFF_ALPHA_VAL_U] = 0x14,
> +               [PLL_OFF_USER_CTL] = 0x18,
> +               [PLL_OFF_USER_CTL_U] = 0x1c,
> +               [PLL_OFF_CONFIG_CTL] = 0x20,
> +               [PLL_OFF_STATUS] = 0x28,
> +               [PLL_OFF_TEST_CTL] = 0x30,
> +               [PLL_OFF_TEST_CTL_U] = 0x34,
> +       },

Is anything different from STROMER_PLUS?

>         [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {
>                 [PLL_OFF_L_VAL] = 0x08,
>                 [PLL_OFF_ALPHA_VAL] = 0x10,
> @@ -73,6 +84,38 @@ static struct clk_alpha_pll ipq_pll_stromer_plus = {
>         },
>  };
>  
> +static struct clk_alpha_pll ipq_pll_stromer = {
> +       .offset = 0x0,
> +       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER],
> +       .flags = SUPPORTS_DYNAMIC_UPDATE,
> +       .clkr = {
> +               .enable_reg = 0x0,
> +               .enable_mask = BIT(0),
> +               .hw.init = &(struct clk_init_data){

const?

> +                       .name = "a53pll",
> +                       .parent_data = &(const struct clk_parent_data) {
> +                               .fw_name = "xo",
> +                       },
> +                       .num_parents = 1,
> +                       .ops = &clk_alpha_pll_stromer_ops,
> +               },
> +       },
> +};
> +
> +static const struct alpha_pll_config ipq5018_pll_config = {
> +       .l = 0x32,
> +       .config_ctl_val = 0x4001075b,
> +       .config_ctl_hi_val = 0x304,
> +       .main_output_mask = BIT(0),
> +       .aux_output_mask = BIT(1),
> +       .early_output_mask = BIT(3),
> +       .alpha_en_mask = BIT(24),
> +       .status_val = 0x3,
> +       .status_mask = GENMASK(10, 8),
> +       .lock_det = BIT(2),
> +       .test_ctl_hi_val = 0x00400003,
> +};
> +
>  static const struct alpha_pll_config ipq5332_pll_config = {
>         .l = 0x3e,
>         .config_ctl_val = 0x4001075b,
> @@ -129,6 +172,12 @@ struct apss_pll_data {
>         const struct alpha_pll_config *pll_config;
>  };
>  
> +static struct apss_pll_data ipq5018_pll_data = {

const?

> +       .pll_type = CLK_ALPHA_PLL_TYPE_STROMER,
> +       .pll = &ipq_pll_stromer,
> +       .pll_config = &ipq5018_pll_config,
> +};
> +
>  static struct apss_pll_data ipq5332_pll_data = {
>         .pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
>         .pll = &ipq_pll_stromer_plus,
> @@ -183,7 +232,7 @@ static int apss_ipq_pll_probe(struct platform_device *pdev)
>  
>         if (data->pll_type == CLK_ALPHA_PLL_TYPE_HUAYRA)
>                 clk_alpha_pll_configure(data->pll, regmap, data->pll_config);
> -       else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS)
> +       else

Just add both STROMER and STROMER_PLUS. Or make STROMER the same as
STROMER_PLUS locally in this file?

>                 clk_stromer_pll_configure(data->pll, regmap, data->pll_config);
>  
>         ret = devm_clk_register_regmap(dev, &data->pll->clkr);

Re: [PATCH 2/3] clk: qcom: apss-ipq-pll: add support for IPQ5018

[Gokul Sriram P]

On 8/30/2023 4:04 AM, Stephen Boyd wrote:
> Quoting Gokul Sriram Palanisamy (2023-08-29 02:54:22)
>> diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
>> index e170331858cc..bbc25d5eb70d 100644
>> --- a/drivers/clk/qcom/apss-ipq-pll.c
>> +++ b/drivers/clk/qcom/apss-ipq-pll.c
>> @@ -24,6 +24,17 @@ static const u8 ipq_pll_offsets[][PLL_OFF_MAX_REGS] = {
>>                  [PLL_OFF_TEST_CTL] = 0x30,
>>                  [PLL_OFF_TEST_CTL_U] = 0x34,
>>          },
>> +       [CLK_ALPHA_PLL_TYPE_STROMER] = {
>> +               [PLL_OFF_L_VAL] = 0x08,
>> +               [PLL_OFF_ALPHA_VAL] = 0x10,
>> +               [PLL_OFF_ALPHA_VAL_U] = 0x14,
>> +               [PLL_OFF_USER_CTL] = 0x18,
>> +               [PLL_OFF_USER_CTL_U] = 0x1c,
>> +               [PLL_OFF_CONFIG_CTL] = 0x20,
>> +               [PLL_OFF_STATUS] = 0x28,
>> +               [PLL_OFF_TEST_CTL] = 0x30,
>> +               [PLL_OFF_TEST_CTL_U] = 0x34,
>> +       },
> Is anything different from STROMER_PLUS?
  No, here both both STROMER and STROMER  PLUS has the same offsets.
   Will update to reuse STORMER PLUS config.
>>          [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {
>>                  [PLL_OFF_L_VAL] = 0x08,
>>                  [PLL_OFF_ALPHA_VAL] = 0x10,
>> @@ -73,6 +84,38 @@ static struct clk_alpha_pll ipq_pll_stromer_plus = {
>>          },
>>   };
>>   
>> +static struct clk_alpha_pll ipq_pll_stromer = {
>> +       .offset = 0x0,
>> +       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER],
>> +       .flags = SUPPORTS_DYNAMIC_UPDATE,
>> +       .clkr = {
>> +               .enable_reg = 0x0,
>> +               .enable_mask = BIT(0),
>> +               .hw.init = &(struct clk_init_data){
> const?
  sure, will update.
>> +                       .name = "a53pll",
>> +                       .parent_data = &(const struct clk_parent_data) {
>> +                               .fw_name = "xo",
>> +                       },
>> +                       .num_parents = 1,
>> +                       .ops = &clk_alpha_pll_stromer_ops,
>> +               },
>> +       },
>> +};
>> +
>> +static const struct alpha_pll_config ipq5018_pll_config = {
>> +       .l = 0x32,
>> +       .config_ctl_val = 0x4001075b,
>> +       .config_ctl_hi_val = 0x304,
>> +       .main_output_mask = BIT(0),
>> +       .aux_output_mask = BIT(1),
>> +       .early_output_mask = BIT(3),
>> +       .alpha_en_mask = BIT(24),
>> +       .status_val = 0x3,
>> +       .status_mask = GENMASK(10, 8),
>> +       .lock_det = BIT(2),
>> +       .test_ctl_hi_val = 0x00400003,
>> +};
>> +
>>   static const struct alpha_pll_config ipq5332_pll_config = {
>>          .l = 0x3e,
>>          .config_ctl_val = 0x4001075b,
>> @@ -129,6 +172,12 @@ struct apss_pll_data {
>>          const struct alpha_pll_config *pll_config;
>>   };
>>   
>> +static struct apss_pll_data ipq5018_pll_data = {
> const?
  sure, will update.
>> +       .pll_type = CLK_ALPHA_PLL_TYPE_STROMER,
>> +       .pll = &ipq_pll_stromer,
>> +       .pll_config = &ipq5018_pll_config,
>> +};
>> +
>>   static struct apss_pll_data ipq5332_pll_data = {
>>          .pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
>>          .pll = &ipq_pll_stromer_plus,
>> @@ -183,7 +232,7 @@ static int apss_ipq_pll_probe(struct platform_device *pdev)
>>   
>>          if (data->pll_type == CLK_ALPHA_PLL_TYPE_HUAYRA)
>>                  clk_alpha_pll_configure(data->pll, regmap, data->pll_config);
>> -       else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS)
>> +       else
> Just add both STROMER and STROMER_PLUS. Or make STROMER the same as
> STROMER_PLUS locally in this file?

sure, with the first comment addressed, this change will not be needed.

Regards,
Gokul

Re: [PATCH 1/3] dt-bindings: clock: qcom,a53pll: add IPQ5018 compatible

[Gokul Sriram P]

On 8/29/2023 3:39 PM, Krzysztof Kozlowski wrote:
> On 29/08/2023 11:54, Gokul Sriram Palanisamy wrote:
>> Add IPQ5018 compatible to A53 PLL bindings.
>>
>> Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> Knowing that this patch could not come from downstream (it's some old
> kernel without this file), I really wonder why two people were involved
> in developing trivial one line change.
Sure, I had kept this co-developed-by for this whole series of patches. 
will remove co-developed-by for this patch.

Regards,
Gokul

Re: [PATCH 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support

[Gokul Sriram P]

>>>>>    #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>>>    #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
>>>>>    #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
>>>>> +#include <dt-bindings/clock/qcom,apss-ipq.h>
>>>> c is before r.
  Sure, will update.

[...]
>>>>
>>>>> +   cpu_opp_table: opp-table-cpu {
>>>>> +           compatible = "operating-points-v2";
>>>>> +           opp-shared;
>>>>> +
>>>>> +           opp-1008000000 {
>>>>> +                   opp-hz = /bits/ 64 <1008000000>;
>>>>> +                   opp-microvolt = <1100000>;
>>>>> +                   clock-latency-ns = <200000>;
>>>> And the rest of OPPs?
>>> Hi Krzysztof,
>>> IPQ5018 only supports running at 1.1GHz, but its running at 800MHz
>>> by default from the bootloader so there is only one OPP.
>> Isn't this contradictory? If it is running at 800 initially, then it
>> supports running at 800...
> I can only guess that it's not validated at 800MHz.
As per the h/w design team, there is negligible power or thermal benefit 
by lowering to 800MHz clock.
Hence, 800MHz opp wasn't included here.
>
> Regards,
> Robert
>>
>> Best regards,
>> Krzysztof
>>

Re: [PATCH 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support

[Gokul Sriram P]

[...]
>>>   +        a53pll: clock@b116000 {
>>> +            compatible = "qcom,ipq5018-a53pll";
>>> +            reg = <0x0b116000 0x40>;
>>> +            #clock-cells = <0>;
>>> +            clocks = <&xo_board_clk>;
>>> +            clock-names = "xo";
>>> +        };
>>> +
>>> +        apcs_glb: mailbox@b111000 {
>> 0xb111000 looks lower than 0x116000.
Sure, will update.

Regards,
Gokul

Re: [PATCH 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support

[Dmitry Baryshkov]

On Wed, 30 Aug 2023 at 21:32, Gokul Sriram P <quic_gokulsri@quicinc.com> wrote:
>
>
> >>>>>    #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>>>>    #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
> >>>>>    #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
> >>>>> +#include <dt-bindings/clock/qcom,apss-ipq.h>
> >>>> c is before r.
>   Sure, will update.
>
> [...]
> >>>>
> >>>>> +   cpu_opp_table: opp-table-cpu {
> >>>>> +           compatible = "operating-points-v2";
> >>>>> +           opp-shared;
> >>>>> +
> >>>>> +           opp-1008000000 {
> >>>>> +                   opp-hz = /bits/ 64 <1008000000>;
> >>>>> +                   opp-microvolt = <1100000>;
> >>>>> +                   clock-latency-ns = <200000>;
> >>>> And the rest of OPPs?
> >>> Hi Krzysztof,
> >>> IPQ5018 only supports running at 1.1GHz, but its running at 800MHz
> >>> by default from the bootloader so there is only one OPP.
> >> Isn't this contradictory? If it is running at 800 initially, then it
> >> supports running at 800...
> > I can only guess that it's not validated at 800MHz.
> As per the h/w design team, there is negligible power or thermal benefit
> by lowering to 800MHz clock.
> Hence, 800MHz opp wasn't included here.

Just my 2c. If 800 MHz is supported, it should be included. Even if
just to prevent the kernel from throwing a warning about the CPU
running at the unsupported frequency. Then one can use scheduler
tunings to prevent the CPU from going to 800 MHz state.


-- 
With best wishes
Dmitry

Re: [PATCH 1/3] dt-bindings: clock: qcom,a53pll: add IPQ5018 compatible

[Dmitry Baryshkov]

On Wed, 30 Aug 2023 at 21:31, Gokul Sriram P <quic_gokulsri@quicinc.com> wrote:
>
>
> On 8/29/2023 3:39 PM, Krzysztof Kozlowski wrote:
> > On 29/08/2023 11:54, Gokul Sriram Palanisamy wrote:
> >> Add IPQ5018 compatible to A53 PLL bindings.
> >>
> >> Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> >> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> > Knowing that this patch could not come from downstream (it's some old
> > kernel without this file), I really wonder why two people were involved
> > in developing trivial one line change.
> Sure, I had kept this co-developed-by for this whole series of patches.
> will remove co-developed-by for this patch.

Each patch is individual, even if they form a series. Different
patches might be developed by different parties or a combination of
them.


-- 
With best wishes
Dmitry

Re: [PATCH 1/3] dt-bindings: clock: qcom,a53pll: add IPQ5018 compatible

[Gokul Sriram P]

On 8/31/2023 1:17 AM, Dmitry Baryshkov wrote:
> Each patch is individual, even if they form a series. Different
> patches might be developed by different parties or a combination of
> them.

I get it Dmitry. Thanks. Will update.

Regards,
Gokul

Re: [PATCH 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support

[Gokul Sriram P]

On 8/31/2023 1:12 AM, Dmitry Baryshkov wrote:
> On Wed, 30 Aug 2023 at 21:32, Gokul Sriram P <quic_gokulsri@quicinc.com> wrote:
>>
>>>>>>>     #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>>>>>     #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
>>>>>>>     #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
>>>>>>> +#include <dt-bindings/clock/qcom,apss-ipq.h>
>>>>>> c is before r.
>>    Sure, will update.
>>
>> [...]
>>>>>>> +   cpu_opp_table: opp-table-cpu {
>>>>>>> +           compatible = "operating-points-v2";
>>>>>>> +           opp-shared;
>>>>>>> +
>>>>>>> +           opp-1008000000 {
>>>>>>> +                   opp-hz = /bits/ 64 <1008000000>;
>>>>>>> +                   opp-microvolt = <1100000>;
>>>>>>> +                   clock-latency-ns = <200000>;
>>>>>> And the rest of OPPs?
>>>>> Hi Krzysztof,
>>>>> IPQ5018 only supports running at 1.1GHz, but its running at 800MHz
>>>>> by default from the bootloader so there is only one OPP.
>>>> Isn't this contradictory? If it is running at 800 initially, then it
>>>> supports running at 800...
>>> I can only guess that it's not validated at 800MHz.
>> As per the h/w design team, there is negligible power or thermal benefit
>> by lowering to 800MHz clock.
>> Hence, 800MHz opp wasn't included here.
> Just my 2c. If 800 MHz is supported, it should be included. Even if
> just to prevent the kernel from throwing a warning about the CPU
> running at the unsupported frequency. Then one can use scheduler
> tunings to prevent the CPU from going to 800 MHz state.

sure, understood. Will add opp at 800MHz. Thanks.

Regards,
Gokul