From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38AAE4502A; Sun, 31 Aug 2025 01:40:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756604448; cv=none; b=MAHCGRfI7kCafgAj7NIakBBZgm3HJ6E669CG1OxtqZoQa/lZnSfgIVT9b4aEWhMQAC69P6wgDgY2BQ+adtZQKQ4DSJhgQ6JXKlznpPB+mC7eMX0TwBcxjTaUuPRKpCjpWd1IZjfdqj3QVuvuvWG3m5WarkkhGrj25f0nR3lJGYg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756604448; c=relaxed/simple; bh=878wiNWTsy/MqUwMdILYoZjCi3hb/V76DP4rIsFWyc4=; h=Message-ID:Date:MIME-Version:Subject:To:References:From: In-Reply-To:Content-Type; b=iNIw/WF4BmYac8JDEvCoSHtGQZAQLAyD5l57cMmi2XKierXxjDAYmYrI39HQZGgKVOCjURZ59W7S9tv1F0gD0MHRjZv5YwfdDpgiA7Abo5fDggir1wqAE+FB252QKBGiRy/9GwkeIyuo+nw3CFS4MXFJ1oUZZr9VINA3aAkmJC4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 38036C4CEEB; Sun, 31 Aug 2025 01:40:47 +0000 (UTC) Message-ID: <9e56d3e2-b9c4-41ee-aab2-220733fbd658@kernel.og> Date: Sat, 30 Aug 2025 20:40:45 -0500 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/4] arm64: dts: socfpga: n5x: Add 4-bit SPI bus width To: yankei.fong@altera.com, Dinh Nguyen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , open list , Matthew Gerlach References: Content-Language: en-US From: Dinh Nguyen In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 6/24/25 01:52, yankei.fong@altera.com wrote: > From: "Fong, Yan Kei" > > Add spi-tx-bus-width and spi-rx-bus-width properties with > value 4 to the n5x device tree. > This update configures the SPI controller to use a 4-bit > bus width for both transmission and reception, > potentially improving SPI throughput and > matching the hardware capabilities more closely. Please use 80 columns for your commit message! Like this: Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the n5x device tree. This update configures the SPI controller to use a 4-bit bus width for both transmission and reception, potentially improving SPI throughput and matching the hardware capabilities more closely. Doesn't the above make it much easier to read? Please do this fall your patches from now on! Dinh