From: Jie Luo <quic_luoj@quicinc.com>
To: Conor Dooley <conor@kernel.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
<agross@kernel.org>, <andersson@kernel.org>,
<konrad.dybcio@linaro.org>, <davem@davemloft.net>,
<edumazet@google.com>, <kuba@kernel.org>, <pabeni@redhat.com>,
<robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<conor+dt@kernel.org>, <andrew@lunn.ch>, <hkallweit1@gmail.com>,
<linux@armlinux.org.uk>, <robert.marko@sartura.hr>,
<linux-arm-msm@vger.kernel.org>, <netdev@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<quic_srichara@quicinc.com>
Subject: Re: [PATCH v2 5/5] dt-bindings: net: ipq4019-mdio: Document ipq5332 platform
Date: Sat, 16 Dec 2023 21:16:49 +0800 [thread overview]
Message-ID: <9eab958e-d91f-4f3c-aadd-6b34eaed2cef@quicinc.com> (raw)
In-Reply-To: <20231215-gauze-sprinkled-172729f22b6c@spud>
On 12/15/2023 9:41 PM, Conor Dooley wrote:
> On Fri, Dec 15, 2023 at 08:40:20PM +0800, Jie Luo wrote:
>>
>>
>> On 12/15/2023 8:19 PM, Krzysztof Kozlowski wrote:
>>> On 15/12/2023 12:42, Jie Luo wrote:
>>>>>>>>>>> Which clocks are these mentioned in the property? From where do they come?
>>>>>>>>>>>
>>>>>>>>>>> Anyway, property is in existing form is not correct - this is not a
>>>>>>>>>>> generic property.
>>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> This property cmn-reference-clock is just the hardware register
>>>>>>>>>> configuration, since the different IPQ platform needs to select
>>>>>>>>>> the different reference clock source for the CMN PLL block that
>>>>>>>>>> provides the various clock outputs to the all kinds of Ethernet
>>>>>>>>>> devices, which is not from GCC provider.
>>>>>>>>>
>>>>>>>>> AGAIN: where do the clocks come from? Which device generates them?
>>>>>>>>
>>>>>>>> Oh, OK, the reference clock is from wifi that provides 48MHZ to
>>>>>>>> Ethernet block.
>>>>>>>
>>>>>>> Then WiFi should be providing you the clock and this device should be
>>>>>>> clock consumer, right?
>>>>>>
>>>>>> Yes, wifi provides 48MHz clock to CMM PLL block, there is no GCC
>>>>>> for this 48MHZ clock output, it is the hardware PIN connection.
>>>>>
>>>>> All clocks are some hardware pin connections.
>>>>>
>>>>> Best regards,
>>>>> Krzysztof
>>>>>
>>>>
>>>> Yes, all reference clocks here are from hardware pin connection.
>>>
>>> You keep answering with short sentences without touching the root of the
>>> problem. I don't know exactly why, but I feel this discussion leads
>>> nowhere. After long discussion you finally admitted that clocks came
>>> from another device - Wifi. It took us like 6 emails?
>>>
>>> So last statement: if you have clock provider and clock consumer, you
>>> must represent it in the bindings or provide rationale why it should not
>>> or must not be represented in the bindings. So far I do not see any of
>>> such arguments.
>>>
>>> If you use arguments like:
>>> "My driver....": sorry, bindings are not about drivers
>>> "I don't have clock driver for WiFi": sorry, it does not matter if you
>>> can write one, right?
>>>
>>> Please reach internally your colleagues to solve these problems and make
>>> review process smoother.
>
>> These reference clocks source do not need the hardware configuration,
>> that is the reason why the clock provider is not needed, some reference
>> clock source are even from external crystal.
>
> I fail to understand how that makes this clock different to the clocks
> on any other platform. Clocks from external crystals are present in many
> many systems. See for example fixed-clock.yaml.
Hi Conor,
The reference clock rate has no meaning to the CMN PLL block, since the
software can't control the behavior of CMN PLL, and various output
clocks of CMN PLL block are fixed, adding this custom property is just
for selecting the different reference clock source, since different
IPQ platform needs to be configured the different reference clock source
for the CMN PLL block.
let's say if we register 48MHZ reference clock as the fix clock, we
can't distinguish it is internal 48MHZ or external 48MHZ, for these
two reference clock sources, there are different hardware configuration
of CMN PLL block, and this reference clock selection is not applicable
for the IPQ4019 platform.
>
>> There is also no enable control for the reference clocks since it is
>> inputted by the hardware PIN connection, i will update these description
>> in the DT to make it more clear.
>
> Again, this does not justify having custom properties for this clock,
> as it is no different to other platforms. As far as I can tell, the only
> thing that a standard "clocks" property cannot convey here is the
> internal reference. I would suggest that since there is only one
> internal clock frequency, the absence of this particular clock in the
> "clocks" property can be used to determine that the reference is the
> internal one.
>
> Thanks,
> Conor.
Yes, we can get the clock rate of the clocks property if we register
these as the fix clock to distinguish the different clock source.
Since the reference clock rate value has no matter with the CMN clock
configuration, it is just the reference clock source selection, so
i did not use the fix clock for this.
Thanks for this suggestion, i will verify the fix clock register solution.
next prev parent reply other threads:[~2023-12-16 13:17 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-12 11:51 [PATCH v2 0/5] support ipq5332 platform Luo Jie
2023-12-12 11:51 ` [PATCH v2 1/5] net: mdio: ipq4019: move eth_ldo_rdy before MDIO bus register Luo Jie
2023-12-12 12:50 ` Maxime Chevallier
2023-12-12 19:11 ` Russell King (Oracle)
2023-12-13 10:07 ` Maxime Chevallier
2023-12-12 11:51 ` [PATCH v2 2/5] net: mdio: ipq4019: enable the SoC uniphy clocks for ipq5332 platform Luo Jie
2023-12-12 12:46 ` Maxime Chevallier
2023-12-13 8:05 ` Jie Luo
2023-12-12 11:51 ` [PATCH v2 3/5] net: mdio: ipq4019: configure CMN PLL clock for ipq5332 Luo Jie
2023-12-12 12:54 ` Maxime Chevallier
2023-12-12 19:12 ` Russell King (Oracle)
2023-12-13 8:09 ` Jie Luo
2023-12-13 10:08 ` Maxime Chevallier
2023-12-12 11:51 ` [PATCH v2 4/5] net: mdio: ipq4019: support MDIO clock frequency divider Luo Jie
2023-12-12 11:51 ` [PATCH v2 5/5] dt-bindings: net: ipq4019-mdio: Document ipq5332 platform Luo Jie
2023-12-12 13:24 ` Rob Herring
2023-12-12 16:06 ` Conor Dooley
2023-12-13 8:26 ` Jie Luo
2023-12-14 17:12 ` Conor Dooley
2023-12-15 6:46 ` Jie Luo
2023-12-15 7:29 ` Krzysztof Kozlowski
2023-12-15 9:49 ` Jie Luo
2023-12-15 10:19 ` Krzysztof Kozlowski
2023-12-15 10:33 ` Jie Luo
2023-12-15 10:37 ` Krzysztof Kozlowski
2023-12-15 10:40 ` Jie Luo
2023-12-15 10:53 ` Krzysztof Kozlowski
2023-12-15 11:42 ` Jie Luo
2023-12-15 12:19 ` Krzysztof Kozlowski
2023-12-15 12:40 ` Jie Luo
2023-12-15 13:39 ` Andrew Lunn
2023-12-16 13:31 ` Jie Luo
2023-12-15 13:41 ` Conor Dooley
2023-12-16 13:16 ` Jie Luo [this message]
2023-12-16 14:16 ` Conor Dooley
2023-12-16 15:37 ` Jie Luo
2023-12-19 15:47 ` Conor Dooley
2023-12-20 10:07 ` Jie Luo
2023-12-20 7:28 ` Krzysztof Kozlowski
2023-12-20 10:11 ` Jie Luo
2023-12-15 10:42 ` Conor Dooley
2023-12-15 11:42 ` Jie Luo
2023-12-12 20:06 ` Rob Herring
2023-12-13 8:42 ` Jie Luo
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