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[2001:14bb:ac:e5a8:ef73:73ed:75b3:8ed5]) by smtp.gmail.com with ESMTPSA id v15-20020ac2560f000000b0048af4dc964asm610445lfd.73.2022.08.19.04.37.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Aug 2022 04:37:38 -0700 (PDT) Message-ID: <9ec575ba-784d-74f7-8861-da2f62fe0773@linaro.org> Date: Fri, 19 Aug 2022 14:37:36 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.12.0 Subject: Re: [PATCH net-next 1/2] dt-bindings: net: tja11xx: add nxp,refclk_in property Content-Language: en-US To: Wei Fang , "davem@davemloft.net" , "edumazet@google.com" , "kuba@kernel.org" , "pabeni@redhat.com" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "andrew@lunn.ch" , "f.fainelli@gmail.com" , "hkallweit1@gmail.com" , "linux@armlinux.org.uk" Cc: "netdev@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" References: <20220819074729.1496088-1-wei.fang@nxp.com> <20220819074729.1496088-2-wei.fang@nxp.com> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 19/08/2022 12:37, Wei Fang wrote: >> >>> + in RMII mode. This clock signal is provided by the PHY and is >>> + typically derived from an external 25MHz crystal. Alternatively, >>> + a 50MHz clock signal generated by an external oscillator can be >>> + connected to pin REF_CLK. A third option is to connect a 25MHz >>> + clock to pin CLK_IN_OUT. So, the REF_CLK should be configured >>> + as input or output according to the actual circuit connection. >>> + If present, indicates that the REF_CLK will be configured as >>> + interface reference clock input when RMII mode enabled. >>> + If not present, the REF_CLK will be configured as interface >>> + reference clock output when RMII mode enabled. >>> + Only supported on TJA1100 and TJA1101. >> >> Then disallow it on other variants. >> >> Shouldn't this be just "clocks" property? >> >> > This property is to configure the pin REF_CLK of PHY as a input pin through phy register, > indicates that the REF_CLK signal is provided by an external oscillator. so I don't think it's a > "clock" property. clocks, not clock. You just repeated pieces of description as an counter-argument, so this does not explain anything. If it is external oscillator shouldn't it be represented in DTS and then obtained by driver (clk_get + clk_prepare_enable)? Otherwise how are you sure that clock is actually enabled? And the lack of presence of the external clock means it is derived from PHY? Best regards, Krzysztof