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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: akJ9iYaRIW4Wly7ZtMgOCLSMS86HdWKlmivYmebIM46yB9mfSchTyJt4FQew9ieyz/FDoCA6hz5tnFYAUqkSPiglsHA7NOvwnhG2H4r8wcz4Fba4Yhdi8FsMxbM8MuzX218dINf4cMwsMmq7bs4d1e2BTBiX7sZxUvm/zWs2d/X6ScGHRVQHrubDKEijbqHhU3A9tR7Wzfg7FD3WlknizrGV2tQ7yzOcqPC6GttIZDVPJpOe7UO0MptpDk75gzYLaMiPmfYGPfF6tc8E9k6LbHeKKKK53IaGyDv0f84y2M79a/q6Y7YYQIUa1r322JV+kGEFeCK87l6fYhlkzY+l0FsH1SG8osf3CtsYuiHitXYR1ymFymhlfiXXlnFNnyDTq8M3jHAOAmkDnhsStTOO3AQBbGT7QuIetAf141QTOhYiyCTfHC3VGHIhsLgYOPuj X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2026 09:40:33.6408 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5beff81d-7bb6-441f-4e9c-08df2aa05c0e X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509EE.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS4PR08MB8242 On 15/10/2026 09:20, Lorenzo Pieralisi wrote: > The GICv5 architecture allows IRSes to be designed as standalone, ie with > no CPU connection, to support system topologies where the IRS is separated > from CPUs. > > Current OF code fails the IRS probe if "cpus" and "arm,iaffids" properties, > that define IRS<->CPU connections, are missing (which goes against the > current schema because they are "required"), which is not correct for > the aforementioned reasons. > > DT schema for GICv5 must be updated in that "cpus" and "arm,iaffids" > properties are currently defined as "required" which is not correct > (unless there is a way to keep them "required" and empty) and must > be relaxed. > > I do not think it is possible to keep "cpus" and "arm,iaffids" as > "required" and allow them to be empty lists - I would need DT > maintainers feedback on that to see what is best. > > I did not mark patches for stable kernels because I would like to get > feedback on the DT binding changes first before sending any change that > is potentially ABI changing back to stable kernels (strictly speaking > I do not think the DT changes can actually break anything - the only > potential issue is DT files that do declare "cpus" and "arm,iaffids" as > empty list against the schema - if they do that they are already broken > and this patchset changes nothing in that respect). > > Signed-off-by: Lorenzo Pieralisi Thanks for fixing this issue, Lorenzo. It would be a shame if we couldn't describe all possible topologies! These changes look good to me: Reviewed-by: Sascha Bischoff Thanks, Sascha > --- > Lorenzo Pieralisi (2): > dt-bindings: interrupt-controller: gicv5: Relax IRS properties constraints > irqchip/gic-v5: Fix standalone IRSes OF probe > > .../devicetree/bindings/interrupt-controller/arm,gic-v5.yaml | 9 ++++++--- > drivers/irqchip/irq-gic-v5-irs.c | 4 ++++ > 2 files changed, 10 insertions(+), 3 deletions(-) > --- > base-commit: cee9395acd8043be0644b25c34bfa86623f2b935 > change-id: 20261014-gicv5-irs-no-cpus-8c5fba3f9940 > > Best regards, > -- > Lorenzo Pieralisi