From: Michal Simek <michal.simek@amd.com>
To: <linux-kernel@vger.kernel.org>, <monstr@monstr.eu>,
<michal.simek@xilinx.com>, <git@xilinx.com>
Cc: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>,
Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
Parth Gajjar <parth.gajjar@amd.com>,
"Rob Herring" <robh+dt@kernel.org>,
Vishal Sagar <vishal.sagar@amd.com>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Subject: [PATCH 01/23] arm64: zynqmp: Describe TI phy as ethernet-phy-id
Date: Tue, 2 May 2023 15:35:29 +0200 [thread overview]
Message-ID: <9eefc40c727928e0c7b794a3a2e061ecf6ea230c.1683034376.git.michal.simek@amd.com> (raw)
In-Reply-To: <cover.1683034376.git.michal.simek@amd.com>
TI DP83867 is using strapping based on MIO pins. Tristate setup can influce
PHY address. That's why switch description with ethernet-phy-id compatible
string which enable calling reset. PHY itself setups phy address after
power up or reset.
Phy reset is done via gpio.
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
Checkpatch is reporting issue
warning: DT compatible string "ethernet-phy-id2000.a231" appears un-documented
but it should be fully aligned with
Documentation/devicetree/bindings/net/ethernet-phy.yaml
---
.../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 23 +++++++++++------
.../boot/dts/xilinx/zynqmp-zcu102-revB.dts | 25 +++++++++++--------
.../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 22 ++++++++++------
.../boot/dts/xilinx/zynqmp-zcu104-revC.dts | 22 ++++++++++------
.../boot/dts/xilinx/zynqmp-zcu106-revA.dts | 22 ++++++++++------
.../boot/dts/xilinx/zynqmp-zcu111-revA.dts | 22 ++++++++++------
6 files changed, 90 insertions(+), 46 deletions(-)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
index 13c43324f1d2..c193579400cf 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
@@ -2,7 +2,8 @@
/*
* dts file for Xilinx ZynqMP ZCU102 RevA
*
- * (C) Copyright 2015 - 2021, Xilinx, Inc.
+ * (C) Copyright 2015 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@@ -200,13 +201,19 @@ &gem3 {
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
- phy0: ethernet-phy@21 {
- reg = <21>;
- ti,rx-internal-delay = <0x8>;
- ti,tx-internal-delay = <0xa>;
- ti,fifo-depth = <0x1>;
- ti,dp83867-rxctrl-strap-quirk;
- /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@21 {
+ #phy-cells = <1>;
+ compatible = "ethernet-phy-id2000.a231";
+ reg = <21>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ ti,dp83867-rxctrl-strap-quirk;
+ reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+ };
};
};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
index f7d718ff116b..00b930f20718 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
@@ -2,7 +2,8 @@
/*
* dts file for Xilinx ZynqMP ZCU102 RevB
*
- * (C) Copyright 2016 - 2021, Xilinx, Inc.
+ * (C) Copyright 2016 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@@ -16,16 +17,20 @@ / {
&gem3 {
phy-handle = <&phyc>;
- phyc: ethernet-phy@c {
- reg = <0xc>;
- ti,rx-internal-delay = <0x8>;
- ti,tx-internal-delay = <0xa>;
- ti,fifo-depth = <0x1>;
- ti,dp83867-rxctrl-strap-quirk;
- /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
+ mdio: mdio {
+ phyc: ethernet-phy@c {
+ #phy-cells = <0x1>;
+ compatible = "ethernet-phy-id2000.a231";
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ ti,dp83867-rxctrl-strap-quirk;
+ reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+ };
+ /* Cleanup from RevA */
+ /delete-node/ ethernet-phy@21;
};
- /* Cleanup from RevA */
- /delete-node/ ethernet-phy@21;
};
/* Fix collision with u61 */
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
index 485585c491f4..11c1eaef9f53 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
@@ -2,7 +2,8 @@
/*
* dts file for Xilinx ZynqMP ZCU104
*
- * (C) Copyright 2017 - 2021, Xilinx, Inc.
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@@ -109,12 +110,19 @@ &gem3 {
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
- phy0: ethernet-phy@c {
- reg = <0xc>;
- ti,rx-internal-delay = <0x8>;
- ti,tx-internal-delay = <0xa>;
- ti,fifo-depth = <0x1>;
- ti,dp83867-rxctrl-strap-quirk;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@c {
+ #phy-cells = <1>;
+ compatible = "ethernet-phy-id2000.a231";
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ ti,dp83867-rxctrl-strap-quirk;
+ reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+ };
};
};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
index 44ec9edd2452..c06c138fa3e5 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
@@ -2,7 +2,8 @@
/*
* dts file for Xilinx ZynqMP ZCU104
*
- * (C) Copyright 2017 - 2021, Xilinx, Inc.
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@@ -114,12 +115,19 @@ &gem3 {
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
- phy0: ethernet-phy@c {
- reg = <0xc>;
- ti,rx-internal-delay = <0x8>;
- ti,tx-internal-delay = <0xa>;
- ti,fifo-depth = <0x1>;
- ti,dp83867-rxctrl-strap-quirk;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@c {
+ #phy-cells = <1>;
+ compatible = "ethernet-phy-id2000.a231";
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ ti,dp83867-rxctrl-strap-quirk;
+ reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+ };
};
};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
index 09773b7200f8..52cdec33f190 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
@@ -2,7 +2,8 @@
/*
* dts file for Xilinx ZynqMP ZCU106
*
- * (C) Copyright 2016 - 2021, Xilinx, Inc.
+ * (C) Copyright 2016 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@@ -212,12 +213,19 @@ &gem3 {
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
- phy0: ethernet-phy@c {
- reg = <0xc>;
- ti,rx-internal-delay = <0x8>;
- ti,tx-internal-delay = <0xa>;
- ti,fifo-depth = <0x1>;
- ti,dp83867-rxctrl-strap-quirk;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@c {
+ #phy-cells = <1>;
+ reg = <0xc>;
+ compatible = "ethernet-phy-id2000.a231";
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ ti,dp83867-rxctrl-strap-quirk;
+ reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+ };
};
};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
index e0305dcbb010..699cc9ce7898 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
@@ -2,7 +2,8 @@
/*
* dts file for Xilinx ZynqMP ZCU111
*
- * (C) Copyright 2017 - 2021, Xilinx, Inc.
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@@ -172,12 +173,19 @@ &gem3 {
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
- phy0: ethernet-phy@c {
- reg = <0xc>;
- ti,rx-internal-delay = <0x8>;
- ti,tx-internal-delay = <0xa>;
- ti,fifo-depth = <0x1>;
- ti,dp83867-rxctrl-strap-quirk;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@c {
+ #phy-cells = <1>;
+ compatible = "ethernet-phy-id2000.a231";
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ ti,dp83867-rxctrl-strap-quirk;
+ reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>;
+ };
};
};
--
2.36.1
next prev parent reply other threads:[~2023-05-02 13:36 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-02 13:35 [PATCH 00/23] arm64: zynqmp: Misc zynqmp changes Michal Simek
2023-05-02 13:35 ` Michal Simek [this message]
2023-05-10 6:52 ` [PATCH 01/23] arm64: zynqmp: Describe TI phy as ethernet-phy-id Laurent Pinchart
2023-05-10 7:11 ` Michal Simek
2023-05-02 13:35 ` [PATCH 02/23] arm64: zynqmp: Fix usb node drive strength and slew rate Michal Simek
2023-05-10 6:54 ` Laurent Pinchart
2023-05-16 13:30 ` Michal Simek
2023-05-02 13:35 ` [PATCH 03/23] arm64: zynqmp: Set qspi tx-buswidth to 4 Michal Simek
2023-05-10 6:56 ` Laurent Pinchart
2023-05-02 13:35 ` [PATCH 04/23] arm64: zynqmp: Fix usb reset over bootmode pins on zcu100 Michal Simek
2023-05-16 11:05 ` Michal Simek
2023-05-02 13:35 ` [PATCH 05/23] arm64: zynqmp: Add L2 cache nodes Michal Simek
2023-05-10 6:57 ` Laurent Pinchart
2023-05-10 7:15 ` Michal Simek
2023-05-10 11:34 ` Laurent Pinchart
2023-05-02 13:35 ` [PATCH 06/23] arm64: zynqmp: Sync node name address with reg (mailbox) Michal Simek
2023-05-10 6:58 ` Laurent Pinchart
2023-05-16 10:57 ` Michal Simek
2023-05-02 13:35 ` [PATCH 07/23] arm64: zynqmp: Add pmu interrupt-affinity Michal Simek
2023-05-10 7:00 ` Laurent Pinchart
2023-05-16 11:05 ` Michal Simek
2023-05-16 12:49 ` Michal Simek
2023-05-02 13:35 ` [PATCH 08/23] arm64: zynqmp: Add resets property to sdhci nodes Michal Simek
2023-05-10 7:02 ` Laurent Pinchart
2023-05-16 10:56 ` Michal Simek
2023-05-02 13:35 ` [PATCH 09/23] arm64: zynqmp: Add dmas, dp, rtc, watchdogs and opp nodes for SOM Michal Simek
2023-05-16 11:06 ` Michal Simek
2023-05-02 13:35 ` [PATCH 10/23] arm64: zynqmp: Add linux,code for gpio button Michal Simek
2023-05-16 11:07 ` Michal Simek
2023-05-02 13:35 ` [PATCH 11/23] arm64: zynqmp: Use assigned-clock-rates for setting up SD clock in SOM Michal Simek
2023-05-16 11:07 ` Michal Simek
2023-05-02 13:35 ` [PATCH 12/23] arm64: zynqmp: Add mtd partition for secure OS storage area Michal Simek
2023-05-16 11:07 ` Michal Simek
2023-05-02 13:35 ` [PATCH 13/23] arm64: zynqmp: Used fixed-partitions for QSPI in k26 Michal Simek
2023-05-02 13:35 ` [PATCH 14/23] arm64: zynqmp: Add gpio labels for modepin gpio Michal Simek
2023-05-16 11:08 ` Michal Simek
2023-05-02 13:35 ` [PATCH 15/23] arm64: zynqmp: Add pinctrl emmc description to SM-K26 Michal Simek
2023-05-16 11:08 ` Michal Simek
2023-05-02 13:35 ` [PATCH 16/23] arm64: zynqmp: Disable USB3.0 for zc1751-xm016-dc2 Michal Simek
2023-05-16 11:08 ` Michal Simek
2023-05-02 13:35 ` [PATCH 17/23] arm64: zynqmp: Switch to ethernet-phy-id in kv260 Michal Simek
2023-05-16 11:09 ` Michal Simek
2023-05-02 13:35 ` [PATCH 18/23] arm64: zynqmp: Setup clock for DP and DPDMA Michal Simek
2023-05-16 11:09 ` Michal Simek
2023-05-02 13:35 ` [PATCH 19/23] arm64: zynqmp: Enable DP driver for SOMs Michal Simek
2023-05-16 11:09 ` Michal Simek
2023-05-02 13:35 ` [PATCH 20/23] arm64: zynqmp: Rename ams_ps/pl node names Michal Simek
2023-05-10 8:32 ` Laurent Pinchart
2023-05-16 10:56 ` Michal Simek
2023-05-02 13:35 ` [PATCH 21/23] arm64: zynqmp: Enable AMS on SOM and other zcu10x boards Michal Simek
2023-05-16 11:10 ` Michal Simek
2023-05-02 13:35 ` [PATCH 22/23] arm64: zynqmp: Describe bus-width for SD card on KV260 Michal Simek
2023-05-16 11:10 ` Michal Simek
2023-05-02 13:35 ` [PATCH 23/23] arm64: zynqmp: Add phase tags marking Michal Simek
2023-05-16 11:10 ` Michal Simek
2023-05-16 11:11 ` [PATCH 00/23] arm64: zynqmp: Misc zynqmp changes Michal Simek
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