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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id w2-20020a170907270200b006f3ef214da6sm4582540ejk.12.2022.05.03.04.16.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 May 2022 04:16:15 -0700 (PDT) Message-ID: <9f71aebf-d30d-9ecd-0e24-3f504bbaa705@linaro.org> Date: Tue, 3 May 2022 13:16:14 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH v2 02/12] dt-bindings: clock: add Exynos Auto v9 SoC CMU bindings Content-Language: en-US To: Chanho Park , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski Cc: Sam Protsenko , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org References: <20220503105914.117625-1-chanho61.park@samsung.com> <20220503105914.117625-3-chanho61.park@samsung.com> From: Krzysztof Kozlowski In-Reply-To: <20220503105914.117625-3-chanho61.park@samsung.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 03/05/2022 12:59, Chanho Park wrote: > Add dt-schema for Exynos Auto v9 SoC clock controller. > > Signed-off-by: Chanho Park > --- > .../clock/samsung,exynosautov9-clock.yaml | 219 ++++++++++++++++++ > 1 file changed, 219 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml > > diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml > new file mode 100644 > index 000000000000..9f9cd8606728 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml > @@ -0,0 +1,219 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/samsung,exynosautov9-clock.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Samsung Exynos Auto v9 SoC clock controller > + > +maintainers: > + - Chanho Park > + - Chanwoo Choi > + - Krzysztof Kozlowski > + - Sylwester Nawrocki > + - Tomasz Figa > + > +description: | > + Exynos Auto v9 clock controller is comprised of several CMU units, generating > + clocks for different domains. Those CMU units are modeled as separate device > + tree nodes, and might depend on each other. Root clocks in that clock tree are > + two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz). > + Those external clocks must be defined as fixed-rate clocks in dts. > + > + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and > + dividers; all other clocks of function blocks (other CMUs) are usually > + derived from CMU_TOP. > + > + Each clock is assigned an identifier and client nodes can use this identifier > + to specify the clock which they consume. All clocks available for usage > + in clock consumer nodes are defined as preprocessor macros in > + 'dt-bindings/clock/exynosautov9.h' header. The path is still wrong (and not full). Best regards, Krzysztof