From: Amit Singh Tomar <amitsinght@marvell.com>
To: Pablo Sun <pablo.sun@mediatek.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org
Subject: [PATCH 2/5] clk: mediatek: clk-mt8188-topckgen: Remove univpll from parents of mfg_core_tmp
Date: Mon, 23 Sep 2024 02:39:15 +0530 [thread overview]
Message-ID: <9f8d4e5e-963e-4717-9a28-9181ea662024@marvell.com> (raw)
In-Reply-To: <20240920134111.19744-3-pablo.sun@mediatek.com>
Hi,
> Same as MT8195, MT8188 GPU clock is primarly supplied by the dedicated
> mfgpll. The clock "mfg_core_tmp" is only used as an alt clock when
> setting mfgpll clock rate.
>
> If we keep the univpll parents from mfg_core_tmp, when setting
> GPU frequency to 390000000, the common clock framework would switch
> the parent to univpll, instead of setting mfgpll to 390000000:
>
> mfgpll 0 0 0 949999756
> univpll 2 2 0 2340000000
> univpll_d6 1 1 0 390000000
> top_mfg_core_tmp 1 1 0 390000000
> mfg_ck_fast_ref 1 1 0 390000000
> mfgcfg_bg3d 1 1 0 390000000
>
> This results in failures when subsequent devfreq operations need to
> switch to other frequencies. So remove univpll from the parent list.
>
> This solution is taken from commit 72d38ed720e9 ("clk: mediatek:
> clk-mt8195-topckgen: Drop univplls from mfg mux parents")
>
> Signed-off-by: Pablo Sun <pablo.sun@mediatek.com>
> ---
> drivers/clk/mediatek/clk-mt8188-topckgen.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-mt8188-topckgen.c b/drivers/clk/mediatek/clk-mt8188-topckgen.c
> index 2ccc8a1c98f9..74ee692ac613 100644
> --- a/drivers/clk/mediatek/clk-mt8188-topckgen.c
> +++ b/drivers/clk/mediatek/clk-mt8188-topckgen.c
> @@ -342,11 +342,14 @@ static const char * const dsp7_parents[] = {
> "univpll_d3"
> };
>
> +/*
> + * MFG can be also parented to "univpll_d6" and "univpll_d7":
> + * these have been removed from the parents list to let us
> + * achieve GPU DVFS without any special clock handlers.
> + */
> static const char * const mfg_core_tmp_parents[] = {
> "clk26m",
> "mainpll_d5_d2",
nit: Comma at the end of mainpll_d5_d2 is unnecessary.
> - "univpll_d6",
> - "univpll_d7"
> };
>
> static const char * const camtg_parents[] = {
> --
> 2.45.2
>
>
next prev parent reply other threads:[~2024-09-22 21:09 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-20 13:41 [PATCH 0/5] Enable Mali GPU on MediaTek Genio 700 EVK Pablo Sun
2024-09-20 13:41 ` [PATCH 1/5] arm64: dts: mediatek: mt8188: Fix wrong clock provider in MFG1 power domain Pablo Sun
2024-09-23 8:39 ` AngeloGioacchino Del Regno
2024-09-20 13:41 ` [PATCH 2/5] clk: mediatek: clk-mt8188-topckgen: Remove univpll from parents of mfg_core_tmp Pablo Sun
2024-09-22 21:09 ` Amit Singh Tomar [this message]
2024-09-23 8:38 ` AngeloGioacchino Del Regno
2024-09-20 13:41 ` [PATCH 3/5] nvmem: mtk-efuse: Enable postprocess for mt8188 GPU speed binning Pablo Sun
2024-09-23 8:37 ` AngeloGioacchino Del Regno
2024-09-23 9:20 ` Pablo Sun
2024-09-20 13:41 ` [PATCH 4/5] arm64: dts: mediatek: mt8188: Add efuse for " Pablo Sun
2024-09-23 8:39 ` AngeloGioacchino Del Regno
2024-09-20 13:41 ` [PATCH 5/5] arm64: dts: mediatek: mt8390-genio-700-evk: Enable Mali GPU Pablo Sun
2024-09-23 8:45 ` AngeloGioacchino Del Regno
2024-09-23 10:14 ` Pablo Sun
2024-09-23 12:25 ` AngeloGioacchino Del Regno
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