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Mon, 27 Oct 2025 09:46:07 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 1112444510141004708 EX-QQ-RecipientCnt: 17 Date: Mon, 27 Oct 2025 09:46:07 +0800 From: Troy Mitchell To: Junhui Liu , Troy Mitchell , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Conor Dooley Subject: Re: [PATCH v2 0/6] clk/reset: anlogic: add support for DR1V90 SoC Message-ID: References: <20251026-dr1v90-cru-v2-0-43b67acd6ddd@pigmoral.tech> <0E60AA15166FED21+aP7JRmPzDIq2WhWw@kernel.org> <1bceed11-e7d2-4d10-93fc-b40c6e102bc5@pigmoral.tech> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1bceed11-e7d2-4d10-93fc-b40c6e102bc5@pigmoral.tech> X-QQ-SENDSIZE: 520 Feedback-ID: esmtpsz:linux.spacemit.com:qybglogicsvrgz:qybglogicsvrgz3a-0 X-QQ-XMAILINFO: M9JuRt4Rc2r2oDU/NHKLbAQnXUpEL9vQnIroHbnehM7r8wSiM+robU4x FLKkYrNylWDkMKgw3Qp4sG60EMNrGdadfze6xSqckLgvcOFj4o9KqAhxcBucr834wAyYooL sNAKR0fAJQOeBEltqV+UWltHc1s43HlZCgbUy4FdZuwhEbus7Nb7TIuRPbX4bIv5jsEKUEh ztEKL9ZgYQ0CPwALKEiS3UEbXuRRchLOLInptNJ8irTESSVtZOQMszKdam3xsNap7ODVlbX DsskqfHTXnGcxQiVY3Hq35JcQk1kkLdhdrYC97AtbsjVI4/pxibQFmpLLI9suqo2Nr7+GyT A0VP8yOJ2YAmMS3zbbSIS/Q7QmEScdCpGq6+g3Gd3iSMD1pCzfvfCYpssQ1XkmuRG34SUHL CGVFqLBQ6sno/Tc4/Kelnt4FjzcBzUFngvmwsGr2I2OKYk0jq6vmkTpuHWntgUYQgGRwtxR y1Zeyx8Sz22QxVvJs3Lq9ku7fp2MFe76WfKS2cXFSahqkbUmv0y/T/mAVc8p5U0ovCyeM98 alh0INwzOHuhGPbIuQTw6XIEiGd0xe4RCY8JAJv/jU4jNLLkLR1mz42PjFN9edlR7ge70mg 3Qe2+RbtkmUsTJndum4bkcagzl+tkQQdu1p7DexoQOSxchLi+i+ktIw437fPnelHDWsQ6XB q35VOfmHr0rDp+jbhpoz7tAYrL4p3pMNsIceohHoOcGuqOKcYwgM5y/f5B0m9zphSNsAPdv 6nYpdLXFdYCQSbgRUxPOkSlsC2nWallKzXsCkvvqc763h+p9bmiEMybIrOTS3eEy5S/ISOG 5AYvn28xiRyJFCiGIqzUD7POT6R2OdmapHBQbt/2BUwTT6cG0FxP3mHrPcPCW5TeRJL6RWp Sh8+yPpIWqwJwJlYbirYMPBjHDOrAwwH5GQe25h75HdVKu5J/Jbf+cccrtY5wTAdjRLB+Lz +TIUTK1F7ipoxpIeGH7azU5fgEt1oYVTJ3SBDVZ0hQfCL/M00lfLgc/e+QhPjTwT9s/67sZ 02bXL7lkhqaLFBLxzVAft6bRNNBvJapXt4a/m5Adtg9nz5eNpSzTptteS/dX2Ea+Zz2g+Em 6le4rB20pLRcZua/r1ca/eSsfPbm2SfO8l8VackB62L2F//KdyY1uRyy/m38vH8wQ== X-QQ-XMRINFO: NS+P29fieYNw95Bth2bWPxk= X-QQ-RECHKSPAM: 0 On Mon, Oct 27, 2025 at 09:39:09AM +0800, Junhui Liu wrote: > Hi Troy, > > On 10/27/25 9:22 AM, Troy Mitchell wrote: > > On Sun, Oct 26, 2025 at 10:00:40PM +0800, Junhui Liu wrote: > > > This adds Clock and Reset Unit (CRU) support for the Anlogic DR1V90 SoC, > > > as well as corresponding dts bindings and dts integration. > > > > > > The CRU driver framework is built around the clock controller as the > > > primary device, with the reset controller implemented as an auxiliary > > > device. The clock part refers to the vendor's code [1] to determine the > > > structure of the clock tree. > > > > > > The Anlogic DR1 series includes not only the DR1V90 (based on the Nuclei > > > UX900 RISC-V core), but also the DR1M90 (based on the Cortex-A35 ARM64 > > > core). Most of the clock tree and CRU design can be shared between them. > > > This series only adds CRU support for DR1V90. Nevertheless, the driver > > > is structured to make future extension to other DR1 variants like > > > DR1M90. > > > > > > This depends on the basic dt series for DR1V90 SoC [2]. > > > > > > Link: https://gitee.com/anlogic/linux/blob/anlogic-6.1.54/drivers/clk/anlogic/anl_dr1x90_crp.c [1] > > > Link: https://lore.kernel.org/all/20251021-dr1v90-basic-dt-v3-0-5478db4f664a@pigmoral.tech/ [2] > > > --- > > Do we really need a cover-letter? Since you only have one patch, Is it > > better to put the above information below the --- line in the actual patch? > > Yes, we do need a cover letter since there are 6 patches in this series. > I think the b4 tool only added you to the To list in patch 0 and 1 because > you gave a Reviewed-by to patch 1 in v1. You can check the full patch > series from the mailing list [1]. Thanks. > > [1] https://lore.kernel.org/all/20251026-dr1v90-cru-v2-0-43b67acd6ddd@pigmoral.tech OOPS!I missed that... Thanks for your link. - Troy