From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C3F0C433EF for ; Tue, 10 May 2022 07:33:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237970AbiEJHgn (ORCPT ); Tue, 10 May 2022 03:36:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241537AbiEJHdW (ORCPT ); Tue, 10 May 2022 03:33:22 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BA4BA2A4A0A for ; Tue, 10 May 2022 00:29:22 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id p26so14469029lfh.10 for ; Tue, 10 May 2022 00:29:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:subject:from:in-reply-to:date:cc :content-transfer-encoding:message-id:references:to; bh=VSqxzZ29hbc10inJEDBipg5Dn8Q2IgbVBIfcAZuWFlc=; b=ZpYGnuztQW0iA1l4+RIZIihgQVuuvVmdcZwAdtEMwooAUiC0fu376dlSygjE8O0mwP Un7c+sHOg0wOmMwO9X3VZ5bJImTWXQDt4H+g/6l2K6SyjxdvvVuBcJFuTrTIwRKmNY+w +N174UAnqR55Gt87Kf2jwomaCpAia42vtxPOqGYvGSuVo1dmvtQyCLQfnjxlE/eBpFxJ e8HycjhiLJtATq/gLyrUAyVeAudl5qOh6Oyj1YhshYUZq8RaTRJu8wKj3izgSiGcD330 7C+Rqxh5C4QcmK9CIEm7JpQb0LQsQq76viDK4vVSRHLI0CQbOnVbwiIfscZMuMJIn5BQ EfVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:subject:from:in-reply-to:date:cc :content-transfer-encoding:message-id:references:to; bh=VSqxzZ29hbc10inJEDBipg5Dn8Q2IgbVBIfcAZuWFlc=; b=0Lu3i6+AckioUxw6fUTvlPYq9nvuZVaIE06eYZ3TmkmKZFvLTFgL57png9G30acTW3 DhL8ZDElrxITn0nYkWTzkC8MOodokiAVwkjQIlC8fBSl+5eUmrtxLtR4m4f3BpQgR64S FE+w/rZ63kOwzWrgFcA3HSVyuCD45IouFXymyuJy86fE/ZBlq5HAkoGgVLjPOTqaGflF Q05O7TL/GaZOYm+JVJ2wTcUHg5dc1UXySKnVKaQ5MbV2pKRgocthJJP1Q61cJbZWh/yX icTEVxtXjEfHeGL5yn+wuVQbPgXVkdRTwcldYgNNNfRU6bne/9ZMPN8Kt/IpqqQSEKJO jx5Q== X-Gm-Message-State: AOAM532CYu1J2C97BJvfMr+eEH4lFayW5F6EF231xO0J/nz4Z3wG23Ut H0W5ykdo/XPJ0r1VkOndc9s= X-Google-Smtp-Source: ABdhPJzuUZxd81Xg7d+yaJFS9q6e43uMHj3m7T3kM3PY0/JUhTO2qkFChHbG5NwyadTcS6MMwjtvHQ== X-Received: by 2002:a05:6512:1189:b0:473:b9ee:30cf with SMTP id g9-20020a056512118900b00473b9ee30cfmr15797805lfr.282.1652167760971; Tue, 10 May 2022 00:29:20 -0700 (PDT) Received: from smtpclient.apple (31-178-191-245.dynamic.chello.pl. [31.178.191.245]) by smtp.gmail.com with ESMTPSA id r10-20020a19da0a000000b0047255d211c1sm2189757lfg.240.2022.05.10.00.29.19 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 10 May 2022 00:29:20 -0700 (PDT) Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 14.0 \(3654.120.0.1.13\)) Subject: Re: [PATCH v11 20/24] arm64: dts: rockchip: enable vop2 and hdmi tx on rock-3a From: Piotr Oniszczuk In-Reply-To: Date: Tue, 10 May 2022 09:29:14 +0200 Cc: Sascha Hauer , Michael Riesch , dri-devel@lists.freedesktop.org, "linux-arm-kernel@lists.infradead.org" , "open list:ARM/Rockchip SoC..." , "devicetree@vger.kernel.org" , kernel@pengutronix.de, Andy Yan , Benjamin Gaignard , Sandy Huang , =?utf-8?Q?Heiko_St=C3=BCbner?= , kernel test robot Content-Transfer-Encoding: quoted-printable Message-Id: References: <20220422072841.2206452-1-s.hauer@pengutronix.de> <20220422072841.2206452-21-s.hauer@pengutronix.de> <0E6FE020-C95E-47CF-A9D6-AC3F2B2D334F@gmail.com> <9F2D8CFF-1EAE-4586-9EE9-82A9D67840BB@gmail.com> <812AC0DB-A6D0-4DA3-BCDC-7743E8F61821@gmail.com> To: Peter Geis X-Mailer: Apple Mail (2.3654.120.0.1.13) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org > Wiadomo=C5=9B=C4=87 napisana przez Peter Geis w = dniu 10.05.2022, o godz. 03:35: >=20 > Could you grab the clock tree from /sys/kernel/debug/clk/clk_summary > for the clk_hdmi_cec tree? Here it is: enable prepare protect = duty hardware clock count count count rate = accuracy phase cycle enable = --------------------------------------------------------------------------= ----------------------------- clk_rtc32k_frac 1 1 0 32768 = 0 0 50000 Y clk_rtc_32k 1 1 0 32768 = 0 0 50000 Y clk_hdmi_cec 1 2 0 32768 = 0 0 50000 Y=