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AJvYcCWmOO4RUhWBmY+GiVP7XeSYvBZMuYpi3ieVYBiTRCIO0QA6rdD2dEJ8MFK91d2Jha6c6swkng5Itu0Z@vger.kernel.org X-Gm-Message-State: AOJu0Yw1OjFK9Y3WxvalZ0lncK1GboBPU+qRSC0RsP3lvMSMpH7tL70i 2Ola8h8hmTd1iNEvDxN7WiMN5ImJEd67k73NO86cn53cu8EyKrRHpV36ZtfX9Guz8vI8JJtmZ1v 2LefUafyO78oDginC+BJUvDaFyOA3gtI= X-Gm-Gg: ASbGnctjMqtT4xPks4r6ButC6PCL6AIABH5vIl1rXmMa06O4gya5ePcRvc+UIjpB5aD ZP7J2etxTbr5WVYOdF4h3updiTWa5lMx2u/h0L8nQ4w82l4182uDsShbwq8on9kykBphyHfN/wB zcl5EZ2mC4/EAKfNsbV3Jc40vyD3CNRbAPM4GqWNT2gNw5pRUZBfLvZQEdCl7PjC59d9sceRHM6 g5SXc0ZEBSWvJAqMMUonmyn1rEtz5NEqEKglHdB9xz1wSM8knC1j8+qaItp X-Google-Smtp-Source: AGHT+IH5L1Mo7xLa57k+5KugvuK+N+9eSJpkUwgo4LQeKXBhJMy9CjFuhGIGVQ+i6zqQoqwOUPriVfL9xrycTyM9beg= X-Received: by 2002:a05:6000:43d6:20b0:426:f391:1968 with SMTP id ffacd0b85a97d-426f3911a30mr3441482f8f.35.1760540185079; Wed, 15 Oct 2025 07:56:25 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20251009160732.1623262-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20251009160732.1623262-3-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: "Lad, Prabhakar" Date: Wed, 15 Oct 2025 15:55:57 +0100 X-Gm-Features: AS18NWDborL4rX4hqJjZmtwrGarJ9O0NBNJ1OthS7bueNWRfQx925JxPvOSaoZs Message-ID: Subject: Re: [PATCH v10 2/6] clk: renesas: rzv2h-cpg: Add support for DSI clocks To: Geert Uytterhoeven , Tomi Valkeinen Cc: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Biju Das , Magnus Damm , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Fabrizio Castro , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Geert, Thank you for the review. On Mon, Oct 13, 2025 at 3:26=E2=80=AFPM Geert Uytterhoeven wrote: > > On Thu, 9 Oct 2025 at 18:07, Prabhakar wrote= : > > From: Lad Prabhakar > > > > Add support for PLLDSI and its post-dividers to the RZ/V2H CPG driver a= nd > > export a set of helper APIs to allow other consumers (notably the DSI > > driver) to compute and select PLL parameter combinations. > > > > Introduce per-PLL-DSI state in the CPG private structure and implement > > clk ops and registration for PLLDSI and PLLDSI divider clocks. Implemen= t > > rzv2h_cpg_plldsi_determine_rate and rzv2h_cpg_plldsi_set_rate to drive > > PLL programming via the new per-PLL state and add a plldsi divider clk > > with determine/set/recalc operations that cooperate with the PLL > > algorithm. > > > > Centralize PLL parameter types and limits by moving definitions into a > > shared header (include/linux/clk/renesas.h). Add struct rzv2h_pll_limit= s, > > struct rzv2h_pll_pars and struct rzv2h_pll_div_pars, plus the > > RZV2H_CPG_PLL_DSI_LIMITS() macro to declare DSI PLL limits. > > > > Provide two exported helper functions, rzv2h_get_pll_pars() and > > rzv2h_get_pll_divs_pars(), that perform iterative searches over PLL > > parameters (M, K, P, S) and optional post-dividers to find the best (or > > exact) match for a requested frequency. Export these helpers in the > > "RZV2H_CPG" namespace for use by external drivers. > > > > This change centralizes DSI PLL rate selection logic, prevents duplicat= e > > implementations in multiple drivers, and enables the DSI driver to > > request accurate PLL rates and program the hardware consistently. > > > > Co-developed-by: Fabrizio Castro > > Signed-off-by: Fabrizio Castro > > Signed-off-by: Lad Prabhakar > > --- > > v9->v10: > > - Dropped rzv2h_get_pll_div_pars() helper and opencoded instead. > > - Dropped rzv2h_get_pll_dtable_pars() helper and opencoded instead. > > - Added dummy helpers rzv2h_get_pll_pars() and rzv2h_get_pll_divs_pars(= ) > > in renesas.h for !CONFIG_CLK_RZV2H case. > > - Updated commit message. > > Thanks for the update! > > > --- a/drivers/clk/renesas/rzv2h-cpg.c > > +++ b/drivers/clk/renesas/rzv2h-cpg.c > > > +static int rzv2h_cpg_plldsi_div_determine_rate(struct clk_hw *hw, > > + struct clk_rate_request = *req) > > +{ > > + struct rzv2h_plldsi_div_clk *dsi_div =3D to_plldsi_div_clk(hw); > > + struct pll_clk *pll_clk =3D to_pll(clk_hw_get_parent(hw)); > > + struct rzv2h_cpg_priv *priv =3D dsi_div->priv; > > + u8 table[RZV2H_MAX_DIV_TABLES] =3D { 0 }; > > + struct rzv2h_pll_div_pars *dsi_params; > > + struct rzv2h_pll_dsi_info *dsi_info; > > + const struct clk_div_table *div; > > + u64 rate_millihz; > > + unsigned int i; > > + > > + dsi_info =3D &priv->pll_dsi_info[pll_clk->pll.instance]; > > + dsi_params =3D &dsi_info->pll_dsi_parameters; > > + > > + rate_millihz =3D mul_u32_u32(req->rate, MILLI); > > + if (rate_millihz =3D=3D dsi_params->div.error_millihz + dsi_par= ams->div.freq_millihz) > > + goto exit_determine_rate; > > + > > + div =3D dsi_div->dtable; > > This belongs inside the for-initializer below. > Agreed. > > + i =3D 0; > > Ditto; or better: in the variable declaration at the top of the function. > Ok, I will move to the top. > > + for (; div->div; div++) { > > + if (i >=3D RZV2H_MAX_DIV_TABLES) > > + return -EINVAL; > > + table[i++] =3D div->div; > > + } > > + > > + if (!rzv2h_get_pll_divs_pars(dsi_info->pll_dsi_limits, dsi_para= ms, table, i, > > + rate_millihz)) { > > + dev_err(priv->dev, "failed to determine rate for req->r= ate: %lu\n", > > + req->rate); > > + return -EINVAL; > > + } > > + > > +exit_determine_rate: > > + req->rate =3D DIV_ROUND_CLOSEST_ULL(dsi_params->div.freq_millih= z, MILLI); > > + req->best_parent_rate =3D req->rate * dsi_params->div.divider_v= alue; > > + dsi_info->req_pll_dsi_rate =3D req->best_parent_rate; > > + > > + return 0; > > +} > > The rest LGTM, so with the above fixed, and the field changes factored > out into a separate patch: Ok, I will move the field changes into a separate patch. > Reviewed-by: Geert Uytterhoeven Cheers, Prabhakar