[PATCH v2 0/9] clk: renesas: rzv2h: Add clock and reset entries for USB2 and GBETH

[PATCH v2 0/9] clk: renesas: rzv2h: Add clock and reset entries for USB2 and GBETH

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi All,

This patch series introduces enhancements and new features for the
Renesas RZ/V2H(P) family driver and R9A09G057 SoC specific clock drivers.
The changes include support for static mux clocks, static dividers,
support for ignoring monitoring bits for external clocks, and improved clock
state validation. Additionally, the series includes updates to device tree
bindings for USB2 PHY and GBETH PTP core clocks, as well as the
addition of clock and reset entries for USB2 and GBETH peripherals.

@Geert, Note I've squashed the below patch series [0] and [1] into a single
patch series to avoid conflicts. Patch [2] will be dropped from Biju's
patch series as this is now patch 3/9. Patches are based on the v6.15-rc1 +
renesas-drivers/renesas-clk-for-v6.16 branch.
[0] https://lore.kernel.org/all/20250328200105.176129-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[1] https://lore.kernel.org/all/20250228202655.491035-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[2] https://lore.kernel.org/all/20250303110433.76576-3-biju.das.jz@bp.renesas.com/

v1->v2
- Added ack from Krzysztof for the dt-bindings patch.
- Merged the series into a single patch series
- Introduced DDIV_PACK_NO_RMW macro to support static dividers

Cheers,
Prabhakar

Biju Das (1):
  clk: renesas: rzv2h-cpg: Support static dividers without RMW

Lad Prabhakar (8):
  clk: renesas: rzv2h-cpg: Add support for static mux clocks
  clk: renesas: rzv2h-cpg: Add macro for defining static dividers
  clk: renesas: rzv2h-cpg: Use str_on_off() helper in
    rzv2h_mod_clock_endisable()
  clk: renesas: rzv2h-cpg: Use both CLK_ON and CLK_MON bits for clock
    state validation
  clk: renesas: rzv2h-cpg: Ignore monitoring CLK_MON bits for external
    clocks
  dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP
    core clocks
  clk: renesas: r9a09g057: Add clock and reset entries for USB2
  clk: renesas: r9a09g057: Add clock and reset entries for GBETH0/1

 drivers/clk/renesas/r9a09g057-cpg.c           | 92 +++++++++++++++++-
 drivers/clk/renesas/rzv2h-cpg.c               | 65 ++++++++++++-
 drivers/clk/renesas/rzv2h-cpg.h               | 93 ++++++++++++++++++-
 .../dt-bindings/clock/renesas,r9a09g057-cpg.h |  4 +
 4 files changed, 244 insertions(+), 10 deletions(-)

-- 
2.49.0

[PATCH v2 1/9] clk: renesas: rzv2h-cpg: Add support for static mux clocks

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add support for `CLK_TYPE_SMUX` to register static muxed clocks on the
Renesas RZ/V2H(P) SoC. Extend `cpg_core_clk` to include parent names,
mux flags, and a new `smuxed` struct. Update clock registration to
handle static mux clocks.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clk/renesas/rzv2h-cpg.c | 21 +++++++++++++++++++++
 drivers/clk/renesas/rzv2h-cpg.h | 32 ++++++++++++++++++++++++++++++++
 2 files changed, 53 insertions(+)

diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index b8bed0c1d918..4cda36d7f0a7 100644
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -399,6 +399,24 @@ rzv2h_cpg_ddiv_clk_register(const struct cpg_core_clk *core,
 	return div->hw.clk;
 }
 
+static struct clk * __init
+rzv2h_cpg_mux_clk_register(const struct cpg_core_clk *core,
+			   struct rzv2h_cpg_priv *priv)
+{
+	struct smuxed mux = core->cfg.smux;
+	const struct clk_hw *clk_hw;
+
+	clk_hw = devm_clk_hw_register_mux(priv->dev, core->name,
+					  core->parent_names, core->num_parents,
+					  core->flag, priv->base + mux.offset,
+					  mux.shift, mux.width,
+					  core->mux_flags, &priv->rmw_lock);
+	if (IS_ERR(clk_hw))
+		return ERR_CAST(clk_hw);
+
+	return clk_hw->clk;
+}
+
 static struct clk
 *rzv2h_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec,
 			       void *data)
@@ -483,6 +501,9 @@ rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core,
 	case CLK_TYPE_DDIV:
 		clk = rzv2h_cpg_ddiv_clk_register(core, priv);
 		break;
+	case CLK_TYPE_SMUX:
+		clk = rzv2h_cpg_mux_clk_register(core, priv);
+		break;
 	default:
 		goto fail;
 	}
diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index 59f72fbed133..03e602d70f69 100644
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -53,6 +53,26 @@ struct ddiv {
 		.monbit = _monbit \
 	})
 
+/**
+ * struct smuxed - Structure for static muxed clocks
+ *
+ * @offset: register offset
+ * @shift: position of the divider field
+ * @width: width of the divider field
+ */
+struct smuxed {
+	unsigned int offset:11;
+	unsigned int shift:4;
+	unsigned int width:4;
+};
+
+#define SMUX_PACK(_offset, _shift, _width) \
+	((struct smuxed){ \
+		.offset = (_offset), \
+		.shift = (_shift), \
+		.width = (_width), \
+	})
+
 #define CPG_CDDIV0		(0x400)
 #define CPG_CDDIV1		(0x404)
 #define CPG_CDDIV3		(0x40C)
@@ -96,8 +116,12 @@ struct cpg_core_clk {
 		unsigned int conf;
 		struct ddiv ddiv;
 		struct pll pll;
+		struct smuxed smux;
 	} cfg;
 	const struct clk_div_table *dtable;
+	const char * const *parent_names;
+	unsigned int num_parents;
+	u8 mux_flags;
 	u32 flag;
 };
 
@@ -107,6 +131,7 @@ enum clk_types {
 	CLK_TYPE_FF,		/* Fixed Factor Clock */
 	CLK_TYPE_PLL,
 	CLK_TYPE_DDIV,		/* Dynamic Switching Divider */
+	CLK_TYPE_SMUX,		/* Static Mux */
 };
 
 #define DEF_TYPE(_name, _id, _type...) \
@@ -125,6 +150,13 @@ enum clk_types {
 		.parent = _parent, \
 		.dtable = _dtable, \
 		.flag = CLK_DIVIDER_HIWORD_MASK)
+#define DEF_SMUX(_name, _id, _smux_packed, _parent_names) \
+	DEF_TYPE(_name, _id, CLK_TYPE_SMUX, \
+		 .cfg.smux = _smux_packed, \
+		 .parent_names = _parent_names, \
+		 .num_parents = ARRAY_SIZE(_parent_names), \
+		 .flag = CLK_SET_RATE_PARENT, \
+		 .mux_flags = CLK_MUX_HIWORD_MASK)
 
 /**
  * struct rzv2h_mod_clk - Module Clocks definitions
-- 
2.49.0

Re: [PATCH v2 1/9] clk: renesas: rzv2h-cpg: Add support for static mux clocks

[Geert Uytterhoeven]

On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add support for `CLK_TYPE_SMUX` to register static muxed clocks on the
> Renesas RZ/V2H(P) SoC. Extend `cpg_core_clk` to include parent names,
> mux flags, and a new `smuxed` struct. Update clock registration to
> handle static mux clocks.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk for v6.16.


> ---
>  drivers/clk/renesas/rzv2h-cpg.c | 21 +++++++++++++++++++++
>  drivers/clk/renesas/rzv2h-cpg.h | 32 ++++++++++++++++++++++++++++++++
>  2 files changed, 53 insertions(+)
>
> diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
> index b8bed0c1d918..4cda36d7f0a7 100644
> --- a/drivers/clk/renesas/rzv2h-cpg.c
> +++ b/drivers/clk/renesas/rzv2h-cpg.c
> @@ -399,6 +399,24 @@ rzv2h_cpg_ddiv_clk_register(const struct cpg_core_clk *core,
>         return div->hw.clk;
>  }
>
> +static struct clk * __init
> +rzv2h_cpg_mux_clk_register(const struct cpg_core_clk *core,
> +                          struct rzv2h_cpg_priv *priv)
> +{
> +       struct smuxed mux = core->cfg.smux;
> +       const struct clk_hw *clk_hw;
> +
> +       clk_hw = devm_clk_hw_register_mux(priv->dev, core->name,
> +                                         core->parent_names, core->num_parents,
> +                                         core->flag, priv->base + mux.offset,
> +                                         mux.shift, mux.width,
> +                                         core->mux_flags, &priv->rmw_lock);
> +       if (IS_ERR(clk_hw))
> +               return ERR_CAST(clk_hw);
> +
> +       return clk_hw->clk;
> +}
> +
>  static struct clk
>  *rzv2h_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec,
>                                void *data)
> @@ -483,6 +501,9 @@ rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core,
>         case CLK_TYPE_DDIV:
>                 clk = rzv2h_cpg_ddiv_clk_register(core, priv);
>                 break;
> +       case CLK_TYPE_SMUX:
> +               clk = rzv2h_cpg_mux_clk_register(core, priv);
> +               break;
>         default:
>                 goto fail;
>         }
> diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
> index 59f72fbed133..03e602d70f69 100644
> --- a/drivers/clk/renesas/rzv2h-cpg.h
> +++ b/drivers/clk/renesas/rzv2h-cpg.h
> @@ -53,6 +53,26 @@ struct ddiv {
>                 .monbit = _monbit \
>         })
>
> +/**
> + * struct smuxed - Structure for static muxed clocks
> + *
> + * @offset: register offset
> + * @shift: position of the divider field
> + * @width: width of the divider field
> + */
> +struct smuxed {
> +       unsigned int offset:11;
> +       unsigned int shift:4;
> +       unsigned int width:4;
> +};
> +
> +#define SMUX_PACK(_offset, _shift, _width) \
> +       ((struct smuxed){ \
> +               .offset = (_offset), \
> +               .shift = (_shift), \
> +               .width = (_width), \
> +       })
> +
>  #define CPG_CDDIV0             (0x400)
>  #define CPG_CDDIV1             (0x404)
>  #define CPG_CDDIV3             (0x40C)
> @@ -96,8 +116,12 @@ struct cpg_core_clk {
>                 unsigned int conf;
>                 struct ddiv ddiv;
>                 struct pll pll;
> +               struct smuxed smux;
>         } cfg;
>         const struct clk_div_table *dtable;
> +       const char * const *parent_names;
> +       unsigned int num_parents;
> +       u8 mux_flags;
>         u32 flag;
>  };
>
> @@ -107,6 +131,7 @@ enum clk_types {
>         CLK_TYPE_FF,            /* Fixed Factor Clock */
>         CLK_TYPE_PLL,
>         CLK_TYPE_DDIV,          /* Dynamic Switching Divider */
> +       CLK_TYPE_SMUX,          /* Static Mux */
>  };
>
>  #define DEF_TYPE(_name, _id, _type...) \
> @@ -125,6 +150,13 @@ enum clk_types {
>                 .parent = _parent, \
>                 .dtable = _dtable, \
>                 .flag = CLK_DIVIDER_HIWORD_MASK)
> +#define DEF_SMUX(_name, _id, _smux_packed, _parent_names) \
> +       DEF_TYPE(_name, _id, CLK_TYPE_SMUX, \
> +                .cfg.smux = _smux_packed, \
> +                .parent_names = _parent_names, \
> +                .num_parents = ARRAY_SIZE(_parent_names), \
> +                .flag = CLK_SET_RATE_PARENT, \
> +                .mux_flags = CLK_MUX_HIWORD_MASK)
>
>  /**
>   * struct rzv2h_mod_clk - Module Clocks definitions
> --
> 2.49.0
>


--
Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 2/9] clk: renesas: rzv2h-cpg: Add macro for defining static dividers

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Unlike dynamic dividers, static dividers do not have a monitor bit.
Introduce the `DEF_CSDIV()` macro for defining static dividers, ensuring
consistency with existing dynamic divider macros.

Additionally, introduce the `CSDIV_NO_MON` macro to indicate the absence
of a monitor bit, allowing the monitoring step to be skipped when
`mon` is set to `CSDIV_NO_MON`.

Note, `rzv2h_cpg_ddiv_clk_register()` will be re-used instead of generic
`clk_hw_register_divider_table()` for registering satic dividers
as some of the static dividers require RMW operations.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clk/renesas/rzv2h-cpg.c |  3 +++
 drivers/clk/renesas/rzv2h-cpg.h | 10 ++++++++++
 2 files changed, 13 insertions(+)

diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index 4cda36d7f0a7..4123c30e8663 100644
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -298,6 +298,9 @@ static inline int rzv2h_cpg_wait_ddiv_clk_update_done(void __iomem *base, u8 mon
 	u32 bitmask = BIT(mon);
 	u32 val;
 
+	if (mon == CSDIV_NO_MON)
+		return 0;
+
 	return readl_poll_timeout_atomic(base + CPG_CLKSTATUS0, val, !(val & bitmask), 10, 200);
 }
 
diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index 03e602d70f69..00b52b459aad 100644
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -45,6 +45,14 @@ struct ddiv {
 	unsigned int monbit:5;
 };
 
+/*
+ * On RZ/V2H(P), the dynamic divider clock supports up to 19 monitor bits,
+ * while on RZ/G3E, it supports up to 16 monitor bits. Use the maximum value
+ * `0x1f` to indicate that monitor bits are not supported for static divider
+ * clocks.
+ */
+#define CSDIV_NO_MON	(0x1f)
+
 #define DDIV_PACK(_offset, _shift, _width, _monbit) \
 	((struct ddiv){ \
 		.offset = _offset, \
@@ -150,6 +158,8 @@ enum clk_types {
 		.parent = _parent, \
 		.dtable = _dtable, \
 		.flag = CLK_DIVIDER_HIWORD_MASK)
+#define DEF_CSDIV(_name, _id, _parent, _ddiv_packed, _dtable) \
+	DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable)
 #define DEF_SMUX(_name, _id, _smux_packed, _parent_names) \
 	DEF_TYPE(_name, _id, CLK_TYPE_SMUX, \
 		 .cfg.smux = _smux_packed, \
-- 
2.49.0

Re: [PATCH v2 2/9] clk: renesas: rzv2h-cpg: Add macro for defining static dividers

[Geert Uytterhoeven]

On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Unlike dynamic dividers, static dividers do not have a monitor bit.
> Introduce the `DEF_CSDIV()` macro for defining static dividers, ensuring
> consistency with existing dynamic divider macros.
>
> Additionally, introduce the `CSDIV_NO_MON` macro to indicate the absence
> of a monitor bit, allowing the monitoring step to be skipped when
> `mon` is set to `CSDIV_NO_MON`.
>
> Note, `rzv2h_cpg_ddiv_clk_register()` will be re-used instead of generic
> `clk_hw_register_divider_table()` for registering satic dividers
> as some of the static dividers require RMW operations.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk for v6.16.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 3/9] clk: renesas: rzv2h-cpg: Support static dividers without RMW

[Prabhakar]

From: Biju Das <biju.das.jz@bp.renesas.com>

Add support for static dividers that do not require read-modify-write (RMW)
operations. This enables the use of the generic clk_divider_ops instead of
the custom RMW-based implementation.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Co-developed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clk/renesas/rzv2h-cpg.c |  5 ++++-
 drivers/clk/renesas/rzv2h-cpg.h | 12 ++++++++++++
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index 4123c30e8663..e53cd31c218e 100644
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -380,7 +380,10 @@ rzv2h_cpg_ddiv_clk_register(const struct cpg_core_clk *core,
 		return ERR_PTR(-ENOMEM);
 
 	init.name = core->name;
-	init.ops = &rzv2h_ddiv_clk_divider_ops;
+	if (cfg_ddiv.no_rmw)
+		init.ops = &clk_divider_ops;
+	else
+		init.ops = &rzv2h_ddiv_clk_divider_ops;
 	init.parent_names = &parent_name;
 	init.num_parents = 1;
 
diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index 00b52b459aad..97054f207113 100644
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -37,12 +37,15 @@ struct pll {
  * @shift: position of the divider bit
  * @width: width of the divider
  * @monbit: monitor bit in CPG_CLKSTATUS0 register
+ * @no_rmw: flag to indicate if the register is read-modify-write
+ *        (1: no RMW, 0: RMW)
  */
 struct ddiv {
 	unsigned int offset:11;
 	unsigned int shift:4;
 	unsigned int width:4;
 	unsigned int monbit:5;
+	unsigned int no_rmw:1;
 };
 
 /*
@@ -61,6 +64,15 @@ struct ddiv {
 		.monbit = _monbit \
 	})
 
+#define DDIV_PACK_NO_RMW(_offset, _shift, _width, _monbit) \
+	((struct ddiv){ \
+		.offset = (_offset), \
+		.shift = (_shift), \
+		.width = (_width), \
+		.monbit = (_monbit), \
+		.no_rmw = 1 \
+	})
+
 /**
  * struct smuxed - Structure for static muxed clocks
  *
-- 
2.49.0

Re: [PATCH v2 3/9] clk: renesas: rzv2h-cpg: Support static dividers without RMW

[Geert Uytterhoeven]

On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Add support for static dividers that do not require read-modify-write (RMW)
> operations. This enables the use of the generic clk_divider_ops instead of
> the custom RMW-based implementation.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Co-developed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk for v6.16.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 4/9] clk: renesas: rzv2h-cpg: Use str_on_off() helper in rzv2h_mod_clock_endisable()

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Replace hard-coded "ON"/"OFF" strings with the `str_on_off()` helper in
`rzv2h_mod_clock_endisable()`.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clk/renesas/rzv2h-cpg.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index e53cd31c218e..39d81da096b2 100644
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -25,6 +25,7 @@
 #include <linux/pm_domain.h>
 #include <linux/refcount.h>
 #include <linux/reset-controller.h>
+#include <linux/string_choices.h>
 
 #include <dt-bindings/clock/renesas-cpg-mssr.h>
 
@@ -598,7 +599,7 @@ static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable)
 	int error;
 
 	dev_dbg(dev, "CLK_ON 0x%x/%pC %s\n", reg, hw->clk,
-		enable ? "ON" : "OFF");
+		str_on_off(enable));
 
 	if (enabled == enable)
 		return 0;
-- 
2.49.0

Re: [PATCH v2 4/9] clk: renesas: rzv2h-cpg: Use str_on_off() helper in rzv2h_mod_clock_endisable()

[Geert Uytterhoeven]

On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Replace hard-coded "ON"/"OFF" strings with the `str_on_off()` helper in
> `rzv2h_mod_clock_endisable()`.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk for v6.16.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 5/9] clk: renesas: rzv2h-cpg: Use both CLK_ON and CLK_MON bits for clock state validation

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Update the clock enable/disable logic to follow the latest hardware
manual's guidelines, ensuring that both CLK_ON and CLK_MON bits are used to
confirm the clock state.

According to the manual, enabling a clock requires setting the CPG_CLK_ON
bit and verifying the clock has started using the CPG_CLK_MON bit.
Similarly, disabling a clock requires clearing the CPG_CLK_ON bit and
confirming the clock has stopped via the CPG_CLK_MON bit.

Modify `rzv2h_mod_clock_is_enabled()` to check CLK_MON first and then
validate CLK_ON for a more accurate clock status evaluation.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clk/renesas/rzv2h-cpg.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index 39d81da096b2..c75ed6ed087b 100644
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -579,11 +579,14 @@ static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)
 	if (clock->mon_index >= 0) {
 		offset = GET_CLK_MON_OFFSET(clock->mon_index);
 		bitmask = BIT(clock->mon_bit);
-	} else {
-		offset = GET_CLK_ON_OFFSET(clock->on_index);
-		bitmask = BIT(clock->on_bit);
+
+		if (!(readl(priv->base + offset) & bitmask))
+			return 0;
 	}
 
+	offset = GET_CLK_ON_OFFSET(clock->on_index);
+	bitmask = BIT(clock->on_bit);
+
 	return readl(priv->base + offset) & bitmask;
 }
 
-- 
2.49.0

Re: [PATCH v2 5/9] clk: renesas: rzv2h-cpg: Use both CLK_ON and CLK_MON bits for clock state validation

[Geert Uytterhoeven]

On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Update the clock enable/disable logic to follow the latest hardware
> manual's guidelines, ensuring that both CLK_ON and CLK_MON bits are used to
> confirm the clock state.
>
> According to the manual, enabling a clock requires setting the CPG_CLK_ON
> bit and verifying the clock has started using the CPG_CLK_MON bit.
> Similarly, disabling a clock requires clearing the CPG_CLK_ON bit and
> confirming the clock has stopped via the CPG_CLK_MON bit.
>
> Modify `rzv2h_mod_clock_is_enabled()` to check CLK_MON first and then
> validate CLK_ON for a more accurate clock status evaluation.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk for v6.16.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 6/9] clk: renesas: rzv2h-cpg: Ignore monitoring CLK_MON bits for external clocks

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Ignore CLK_MON bits when turning on/off module clocks that use an external
clock source.

Introduce the `DEF_MOD_EXTERNAL()` macro for defining module clocks that
may have an external clock source. Update `rzv2h_cpg_register_mod_clk()`
to update mon_index.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clk/renesas/rzv2h-cpg.c | 24 ++++++++++++++++++++++++
 drivers/clk/renesas/rzv2h-cpg.h | 28 ++++++++++++++++++++++++----
 2 files changed, 48 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index c75ed6ed087b..dca0940b3df9 100644
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -569,6 +569,25 @@ static void rzv2h_mod_clock_mstop_disable(struct rzv2h_cpg_priv *priv,
 	spin_unlock_irqrestore(&priv->rmw_lock, flags);
 }
 
+static bool rzv2h_mod_clock_is_external(struct rzv2h_cpg_priv *priv,
+					u16 ext_clk_offset,
+					u8 ext_clk_bit,
+					u8 ext_cond)
+{
+	u32 value;
+
+	if (!ext_clk_offset)
+		return false;
+
+	value = readl(priv->base + ext_clk_offset) & BIT(ext_clk_bit);
+	value >>= ext_clk_bit;
+
+	if (value == ext_cond)
+		return true;
+
+	return false;
+}
+
 static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)
 {
 	struct mod_clock *clock = to_mod_clock(hw);
@@ -691,6 +710,11 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
 	clock->on_index = mod->on_index;
 	clock->on_bit = mod->on_bit;
 	clock->mon_index = mod->mon_index;
+	/* If clock is coming from external source ignore the monitor bit for it */
+	if (rzv2h_mod_clock_is_external(priv, mod->external_clk_offset,
+					mod->external_clk_bit,
+					mod->external_cond))
+		clock->mon_index = -1;
 	clock->mon_bit = mod->mon_bit;
 	clock->no_pm = mod->no_pm;
 	clock->priv = priv;
diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index 97054f207113..c64cfead6dc1 100644
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -192,6 +192,10 @@ enum clk_types {
  * @on_bit: ON bit
  * @mon_index: monitor register index
  * @mon_bit: monitor bit
+ * @external_clk_offset: Offset to check to determine if the clock is external
+ * @external_clk_bit: Bit to check to determine if the clock is external
+ * @external_cond: Condition to determine whether a given clock source is external;
+ *                 it can be either 0 or 1.
  */
 struct rzv2h_mod_clk {
 	const char *name;
@@ -203,9 +207,14 @@ struct rzv2h_mod_clk {
 	u8 on_bit;
 	s8 mon_index;
 	u8 mon_bit;
+	u16 external_clk_offset:10;
+	u8 external_clk_bit:5;
+	u8 external_cond:1;
 };
 
-#define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, _onbit, _monindex, _monbit) \
+#define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, \
+		     _onbit, _monindex, _monbit, _external_clk_offset, \
+		     _external_clk_bit, _external_cond) \
 	{ \
 		.name = (_name), \
 		.mstop_data = (_mstop), \
@@ -216,16 +225,27 @@ struct rzv2h_mod_clk {
 		.on_bit = (_onbit), \
 		.mon_index = (_monindex), \
 		.mon_bit = (_monbit), \
+		.external_clk_offset = (_external_clk_offset), \
+		.external_clk_bit = (_external_clk_bit), \
+		.external_cond = (_external_cond), \
 	}
 
 #define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
-	DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
+	DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, \
+		     0, 0, 0)
 
 #define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
-	DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit)
+	DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit, \
+		     0, 0, 0)
 
 #define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
-	DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit)
+	DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit, \
+		     0, 0, 0)
+
+#define DEF_MOD_EXTERNAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop, \
+			_external_clk_offset, _external_clk_bit, _external_cond) \
+	DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, \
+		     _external_clk_offset, _external_clk_bit, _external_cond)
 
 /**
  * struct rzv2h_reset - Reset definitions
-- 
2.49.0

Re: [PATCH v2 6/9] clk: renesas: rzv2h-cpg: Ignore monitoring CLK_MON bits for external clocks

[Geert Uytterhoeven]

Hi Prabhakar,

Thanks for your patch!

On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Ignore CLK_MON bits when turning on/off module clocks that use an external
> clock source.
>
> Introduce the `DEF_MOD_EXTERNAL()` macro for defining module clocks that
> may have an external clock source. Update `rzv2h_cpg_register_mod_clk()`
> to update mon_index.

So I guess you implemented this because the external clock was not
running, and you got into an infinite loop?

This looks rather fragile to me. How do you know when the clock
is actually running, and thus usable?

> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

> --- a/drivers/clk/renesas/rzv2h-cpg.c
> +++ b/drivers/clk/renesas/rzv2h-cpg.c
> @@ -569,6 +569,25 @@ static void rzv2h_mod_clock_mstop_disable(struct rzv2h_cpg_priv *priv,
>         spin_unlock_irqrestore(&priv->rmw_lock, flags);
>  }
>
> +static bool rzv2h_mod_clock_is_external(struct rzv2h_cpg_priv *priv,
> +                                       u16 ext_clk_offset,

unsigned int

> +                                       u8 ext_clk_bit,

unsigned int

> +                                       u8 ext_cond)

bool

> +{
> +       u32 value;
> +
> +       if (!ext_clk_offset)
> +               return false;
> +
> +       value = readl(priv->base + ext_clk_offset) & BIT(ext_clk_bit);
> +       value >>= ext_clk_bit;

No need to shift:

    return !!value == ext_cond;

> +
> +       if (value == ext_cond)
> +               return true;
> +
> +       return false;
> +}
> +
>  static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)
>  {
>         struct mod_clock *clock = to_mod_clock(hw);
> @@ -691,6 +710,11 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
>         clock->on_index = mod->on_index;
>         clock->on_bit = mod->on_bit;
>         clock->mon_index = mod->mon_index;
> +       /* If clock is coming from external source ignore the monitor bit for it */
> +       if (rzv2h_mod_clock_is_external(priv, mod->external_clk_offset,
> +                                       mod->external_clk_bit,
> +                                       mod->external_cond))

Perhaps just pass "mod" instead of three of its members, to fully
hide the logic inside the helper function?

> +               clock->mon_index = -1;
>         clock->mon_bit = mod->mon_bit;
>         clock->no_pm = mod->no_pm;
>         clock->priv = priv;

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 6/9] clk: renesas: rzv2h-cpg: Ignore monitoring CLK_MON bits for external clocks

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Tue, Apr 15, 2025 at 3:36 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> Thanks for your patch!
>
> On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Ignore CLK_MON bits when turning on/off module clocks that use an external
> > clock source.
> >
> > Introduce the `DEF_MOD_EXTERNAL()` macro for defining module clocks that
> > may have an external clock source. Update `rzv2h_cpg_register_mod_clk()`
> > to update mon_index.
>
> So I guess you implemented this because the external clock was not
> running, and you got into an infinite loop?
>
Yes, partially right but we didn't enter an infinite loop as we have a timeout.

For the CLK_MON, the HW manual for RZ/V2H section 4.4.4.8 CGC Control
Registers and 4.4.4.10 CGC Monitor Registers will be updated to below
in the next version.
 "The clock gating cells require source clocks to operate correctly.
If the source clocks are stopped, these registers cannot be used."

Currently without the series when we turn ON the clock the CLK_ON bit
gets set and to make sure it's turned ON the corresponding CLK_MON bit
is checked to ensure it's ON. When a request is made to turn ON the
clock first we check the CLK_MON bit and if it's being set we return
early as the clock was ON. This worked OK up until now where the
clocks used were internally generated.

In the case of RGMII interface where the Rx/Rx-180 clock was coming
from an PHY on an external pin the above didn't work as expected. When
we issued an unbind request on the glue driver all the clocks were
gated to OFF state i.e CLK_ON bits were set to '0'. Now when the bind
operation was requested  the clocks were requested to be turned ON, ie
when CLK_MON bits for RX/Rx-180 reported to be '1'  that is because
PHY was providing the clock and due to which the CLK_ON bit was unset
(and not gated to ON state)  due to which the DMA reset operation
failed in dwmac-core  driver.

Below is the thread,
[0] https://lore.kernel.org/all/CA+V-a8uWY1Av8eS1k9C6Td=RuB4PbCnQyXbNLzmhao0nr8Spbg@mail.gmail.com/

> This looks rather fragile to me. How do you know when the clock
> is actually running, and thus usable?
>
I was thinking the consumer driver would request the external device
to turn it ON/OFF.

> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> > --- a/drivers/clk/renesas/rzv2h-cpg.c
> > +++ b/drivers/clk/renesas/rzv2h-cpg.c
> > @@ -569,6 +569,25 @@ static void rzv2h_mod_clock_mstop_disable(struct rzv2h_cpg_priv *priv,
> >         spin_unlock_irqrestore(&priv->rmw_lock, flags);
> >  }
> >
> > +static bool rzv2h_mod_clock_is_external(struct rzv2h_cpg_priv *priv,
> > +                                       u16 ext_clk_offset,
>
> unsigned int
>
> > +                                       u8 ext_clk_bit,
>
> unsigned int
>
> > +                                       u8 ext_cond)
>
> bool
>
Agreed I 'll change to the above.

> > +{
> > +       u32 value;
> > +
> > +       if (!ext_clk_offset)
> > +               return false;
> > +
> > +       value = readl(priv->base + ext_clk_offset) & BIT(ext_clk_bit);
> > +       value >>= ext_clk_bit;
>
> No need to shift:
>
>     return !!value == ext_cond;
>
OK.

> > +
> > +       if (value == ext_cond)
> > +               return true;
> > +
> > +       return false;
> > +}
> > +
> >  static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)
> >  {
> >         struct mod_clock *clock = to_mod_clock(hw);
> > @@ -691,6 +710,11 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
> >         clock->on_index = mod->on_index;
> >         clock->on_bit = mod->on_bit;
> >         clock->mon_index = mod->mon_index;
> > +       /* If clock is coming from external source ignore the monitor bit for it */
> > +       if (rzv2h_mod_clock_is_external(priv, mod->external_clk_offset,
> > +                                       mod->external_clk_bit,
> > +                                       mod->external_cond))
>
> Perhaps just pass "mod" instead of three of its members, to fully
> hide the logic inside the helper function?
>
Agreed.

Cheers,
Prabhakar

Re: [PATCH v2 6/9] clk: renesas: rzv2h-cpg: Ignore monitoring CLK_MON bits for external clocks

[Geert Uytterhoeven]

Hi Prabhakar,

On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Ignore CLK_MON bits when turning on/off module clocks that use an external
> clock source.
>
> Introduce the `DEF_MOD_EXTERNAL()` macro for defining module clocks that
> may have an external clock source. Update `rzv2h_cpg_register_mod_clk()`
> to update mon_index.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

> --- a/drivers/clk/renesas/rzv2h-cpg.c
> +++ b/drivers/clk/renesas/rzv2h-cpg.c
> @@ -569,6 +569,25 @@ static void rzv2h_mod_clock_mstop_disable(struct rzv2h_cpg_priv *priv,
>         spin_unlock_irqrestore(&priv->rmw_lock, flags);
>  }
>
> +static bool rzv2h_mod_clock_is_external(struct rzv2h_cpg_priv *priv,
> +                                       u16 ext_clk_offset,
> +                                       u8 ext_clk_bit,
> +                                       u8 ext_cond)
> +{
> +       u32 value;
> +
> +       if (!ext_clk_offset)
> +               return false;
> +
> +       value = readl(priv->base + ext_clk_offset) & BIT(ext_clk_bit);

As ext_clk_offset is actually the offset of the Static Mux Control
Registers (CPG_SSELm), this reads the current state of the mux.
However, can't the state be changed at runtime (despite it being named
a "static mux")?

> +       value >>= ext_clk_bit;
> +
> +       if (value == ext_cond)
> +               return true;
> +
> +       return false;
> +}
> +
>  static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)
>  {
>         struct mod_clock *clock = to_mod_clock(hw);

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 6/9] clk: renesas: rzv2h-cpg: Ignore monitoring CLK_MON bits for external clocks

[Lad, Prabhakar]

Hi Geert,

On Tue, Apr 15, 2025 at 4:01 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Ignore CLK_MON bits when turning on/off module clocks that use an external
> > clock source.
> >
> > Introduce the `DEF_MOD_EXTERNAL()` macro for defining module clocks that
> > may have an external clock source. Update `rzv2h_cpg_register_mod_clk()`
> > to update mon_index.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> > --- a/drivers/clk/renesas/rzv2h-cpg.c
> > +++ b/drivers/clk/renesas/rzv2h-cpg.c
> > @@ -569,6 +569,25 @@ static void rzv2h_mod_clock_mstop_disable(struct rzv2h_cpg_priv *priv,
> >         spin_unlock_irqrestore(&priv->rmw_lock, flags);
> >  }
> >
> > +static bool rzv2h_mod_clock_is_external(struct rzv2h_cpg_priv *priv,
> > +                                       u16 ext_clk_offset,
> > +                                       u8 ext_clk_bit,
> > +                                       u8 ext_cond)
> > +{
> > +       u32 value;
> > +
> > +       if (!ext_clk_offset)
> > +               return false;
> > +
> > +       value = readl(priv->base + ext_clk_offset) & BIT(ext_clk_bit);
>
> As ext_clk_offset is actually the offset of the Static Mux Control
> Registers (CPG_SSELm), this reads the current state of the mux.
> However, can't the state be changed at runtime (despite it being named
> a "static mux")?
>
Agreed based on the HW manual this can be changed at runtime. So this
check needs to be done in the rzv2h_mod_clock_is_enabled().

Cheers,
Prabhakar

[PATCH v2 7/9] dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add definitions for USB2 PHY core clocks and Gigabit Ethernet PTP
reference core clocks in the R9A09G057 CPG bindings header file.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 include/dt-bindings/clock/renesas,r9a09g057-cpg.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/dt-bindings/clock/renesas,r9a09g057-cpg.h b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h
index 541e6d719bd6..884dbeb1e139 100644
--- a/include/dt-bindings/clock/renesas,r9a09g057-cpg.h
+++ b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h
@@ -17,5 +17,9 @@
 #define R9A09G057_CM33_CLK0			6
 #define R9A09G057_CST_0_SWCLKTCK		7
 #define R9A09G057_IOTOP_0_SHCLK			8
+#define R9A09G057_USB2_0_CLK_CORE0		9
+#define R9A09G057_USB2_0_CLK_CORE1		10
+#define R9A09G057_GBETH_0_CLK_PTP_REF_I		11
+#define R9A09G057_GBETH_1_CLK_PTP_REF_I		12
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */
-- 
2.49.0

Re: [PATCH v2 7/9] dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks

[Geert Uytterhoeven]

On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add definitions for USB2 PHY core clocks and Gigabit Ethernet PTP
> reference core clocks in the R9A09G057 CPG bindings header file.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in a branch shared by renesas-devel and renesas-clk
for v6.16.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 8/9] clk: renesas: r9a09g057: Add clock and reset entries for USB2

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add clock and reset entries for USB2.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clk/renesas/r9a09g057-cpg.c | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
index da20dbaead1f..3c40e36259fe 100644
--- a/drivers/clk/renesas/r9a09g057-cpg.c
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -16,7 +16,7 @@
 
 enum clk_ids {
 	/* Core Clock Outputs exported to DT */
-	LAST_DT_CORE_CLK = R9A09G057_IOTOP_0_SHCLK,
+	LAST_DT_CORE_CLK = R9A09G057_GBETH_1_CLK_PTP_REF_I,
 
 	/* External Input Clocks */
 	CLK_AUDIO_EXTAL,
@@ -41,6 +41,7 @@ enum clk_ids {
 	CLK_PLLDTY_ACPU,
 	CLK_PLLDTY_ACPU_DIV2,
 	CLK_PLLDTY_ACPU_DIV4,
+	CLK_PLLDTY_DIV8,
 	CLK_PLLDTY_DIV16,
 	CLK_PLLDTY_RCPU,
 	CLK_PLLDTY_RCPU_DIV4,
@@ -104,6 +105,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
 	DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
 	DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
 	DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
+	DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
 	DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
 	DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dtable_2_64),
 	DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4),
@@ -126,6 +128,8 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
 	DEF_DDIV("ca55_0_coreclk3", R9A09G057_CA55_0_CORE_CLK3, CLK_PLLCA55,
 		 CDDIV1_DIVCTL3, dtable_1_8),
 	DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
+	DEF_FIXED("usb2_0_clk_core0", R9A09G057_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1),
+	DEF_FIXED("usb2_0_clk_core1", R9A09G057_USB2_0_CLK_CORE1, CLK_QEXTAL, 1, 1),
 };
 
 static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
@@ -219,6 +223,16 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
 						BUS_MSTOP(8, BIT(4))),
 	DEF_MOD("sdhi_2_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
 						BUS_MSTOP(8, BIT(4))),
+	DEF_MOD("usb2_0_u2h0_hclk",		CLK_PLLDTY_DIV8, 11, 3, 5, 19,
+						BUS_MSTOP(7, BIT(7))),
+	DEF_MOD("usb2_0_u2h1_hclk",		CLK_PLLDTY_DIV8, 11, 4, 5, 20,
+						BUS_MSTOP(7, BIT(8))),
+	DEF_MOD("usb2_0_u2p_exr_cpuclk",	CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,
+						BUS_MSTOP(7, BIT(9))),
+	DEF_MOD("usb2_0_pclk_usbtst0",		CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22,
+						BUS_MSTOP(7, BIT(10))),
+	DEF_MOD("usb2_0_pclk_usbtst1",		CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
+						BUS_MSTOP(7, BIT(11))),
 	DEF_MOD("cru_0_aclk",			CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
 						BUS_MSTOP(9, BIT(4))),
 	DEF_MOD_NO_PM("cru_0_vclk",		CLK_PLLVDO_CRU0, 13, 3, 6, 19,
@@ -286,6 +300,10 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
 	DEF_RST(10, 7, 4, 24),		/* SDHI_0_IXRST */
 	DEF_RST(10, 8, 4, 25),		/* SDHI_1_IXRST */
 	DEF_RST(10, 9, 4, 26),		/* SDHI_2_IXRST */
+	DEF_RST(10, 12, 4, 29),		/* USB2_0_U2H0_HRESETN */
+	DEF_RST(10, 13, 4, 30),		/* USB2_0_U2H1_HRESETN */
+	DEF_RST(10, 14, 4, 31),		/* USB2_0_U2P_EXL_SYSRST */
+	DEF_RST(10, 15, 5, 0),		/* USB2_0_PRESETN */
 	DEF_RST(12, 5, 5, 22),		/* CRU_0_PRESETN */
 	DEF_RST(12, 6, 5, 23),		/* CRU_0_ARESETN */
 	DEF_RST(12, 7, 5, 24),		/* CRU_0_S_RESETN */
-- 
2.49.0

Re: [PATCH v2 8/9] clk: renesas: r9a09g057: Add clock and reset entries for USB2

[Geert Uytterhoeven]

On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add clock and reset entries for USB2.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk for v6.16.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 9/9] clk: renesas: r9a09g057: Add clock and reset entries for GBETH0/1

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add clock and reset entries for GBETH instances. Include core clocks for
PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks
used as clock sources for the GBETH IP.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clk/renesas/r9a09g057-cpg.c | 72 +++++++++++++++++++++++++++++
 drivers/clk/renesas/rzv2h-cpg.h     | 11 +++++
 2 files changed, 83 insertions(+)

diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
index 3c40e36259fe..057bfa0e2a57 100644
--- a/drivers/clk/renesas/r9a09g057-cpg.c
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -29,6 +29,7 @@ enum clk_ids {
 	CLK_PLLDTY,
 	CLK_PLLCA55,
 	CLK_PLLVDO,
+	CLK_PLLETH,
 	CLK_PLLGPU,
 
 	/* Internal Core Clocks */
@@ -49,6 +50,14 @@ enum clk_ids {
 	CLK_PLLVDO_CRU1,
 	CLK_PLLVDO_CRU2,
 	CLK_PLLVDO_CRU3,
+	CLK_PLLETH_DIV_250_FIX,
+	CLK_PLLETH_DIV_125_FIX,
+	CLK_CSDIV_PLLETH_GBE0,
+	CLK_CSDIV_PLLETH_GBE1,
+	CLK_SMUX2_GBE0_TXCLK,
+	CLK_SMUX2_GBE0_RXCLK,
+	CLK_SMUX2_GBE1_TXCLK,
+	CLK_SMUX2_GBE1_RXCLK,
 	CLK_PLLGPU_GEAR,
 
 	/* Module Clocks */
@@ -78,6 +87,19 @@ static const struct clk_div_table dtable_2_64[] = {
 	{0, 0},
 };
 
+static const struct clk_div_table dtable_2_100[] = {
+	{0, 2},
+	{1, 10},
+	{2, 100},
+	{0, 0},
+};
+
+/* Mux clock tables */
+static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0-rxc-rxclk" };
+static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0-txc-txclk" };
+static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1-rxc-rxclk" };
+static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1-txc-txclk" };
+
 static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
 	/* External Clock Inputs */
 	DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
@@ -90,6 +112,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
 	DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
 	DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
 	DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
+	DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
 	DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU),
 
 	/* Internal Core Clocks */
@@ -115,6 +138,17 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
 	DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4),
 	DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4),
 
+	DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
+	DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
+	DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0,
+		  CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL0, dtable_2_100),
+	DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1,
+		  CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL1, dtable_2_100),
+	DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk),
+	DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
+	DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
+	DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
+
 	DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
 
 	/* Core Clocks */
@@ -130,6 +164,10 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
 	DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
 	DEF_FIXED("usb2_0_clk_core0", R9A09G057_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1),
 	DEF_FIXED("usb2_0_clk_core1", R9A09G057_USB2_0_CLK_CORE1, CLK_QEXTAL, 1, 1),
+	DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G057_GBETH_0_CLK_PTP_REF_I,
+		  CLK_PLLETH_DIV_125_FIX, 1, 1),
+	DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G057_GBETH_1_CLK_PTP_REF_I,
+		  CLK_PLLETH_DIV_125_FIX, 1, 1),
 };
 
 static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
@@ -233,6 +271,38 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
 						BUS_MSTOP(7, BIT(10))),
 	DEF_MOD("usb2_0_pclk_usbtst1",		CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
 						BUS_MSTOP(7, BIT(11))),
+	DEF_MOD_EXTERNAL("gbeth_0_clk_tx_i",	CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
+						BUS_MSTOP(8, BIT(5)),
+						0x300, 8, 1),
+	DEF_MOD_EXTERNAL("gbeth_0_clk_rx_i",	CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
+						BUS_MSTOP(8, BIT(5)),
+						0x300, 12, 1),
+	DEF_MOD_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
+						BUS_MSTOP(8, BIT(5)),
+						0x300, 8, 1),
+	DEF_MOD_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
+						BUS_MSTOP(8, BIT(5)),
+						0x300, 12, 1),
+	DEF_MOD("gbeth_0_aclk_csr_i",		CLK_PLLDTY_DIV8, 11, 12, 5, 28,
+						BUS_MSTOP(8, BIT(5))),
+	DEF_MOD("gbeth_0_aclk_i",		CLK_PLLDTY_DIV8, 11, 13, 5, 29,
+						BUS_MSTOP(8, BIT(5))),
+	DEF_MOD_EXTERNAL("gbeth_1_clk_tx_i",	CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
+						BUS_MSTOP(8, BIT(6)),
+						0x304, 8, 1),
+	DEF_MOD_EXTERNAL("gbeth_1_clk_rx_i",	CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
+						BUS_MSTOP(8, BIT(6)),
+						0x304, 12, 1),
+	DEF_MOD_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0,
+						BUS_MSTOP(8, BIT(6)),
+						0x304, 8, 1),
+	DEF_MOD_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
+						BUS_MSTOP(8, BIT(6)),
+						0x304, 12, 1),
+	DEF_MOD("gbeth_1_aclk_csr_i",		CLK_PLLDTY_DIV8, 12, 2, 6, 2,
+						BUS_MSTOP(8, BIT(6))),
+	DEF_MOD("gbeth_1_aclk_i",		CLK_PLLDTY_DIV8, 12, 3, 6, 3,
+						BUS_MSTOP(8, BIT(6))),
 	DEF_MOD("cru_0_aclk",			CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
 						BUS_MSTOP(9, BIT(4))),
 	DEF_MOD_NO_PM("cru_0_vclk",		CLK_PLLVDO_CRU0, 13, 3, 6, 19,
@@ -304,6 +374,8 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
 	DEF_RST(10, 13, 4, 30),		/* USB2_0_U2H1_HRESETN */
 	DEF_RST(10, 14, 4, 31),		/* USB2_0_U2P_EXL_SYSRST */
 	DEF_RST(10, 15, 5, 0),		/* USB2_0_PRESETN */
+	DEF_RST(11, 0, 5, 1),		/* GBETH_0_ARESETN_I */
+	DEF_RST(11, 1, 5, 2),		/* GBETH_1_ARESETN_I */
 	DEF_RST(12, 5, 5, 22),		/* CRU_0_PRESETN */
 	DEF_RST(12, 6, 5, 23),		/* CRU_0_ARESETN */
 	DEF_RST(12, 7, 5, 24),		/* CRU_0_S_RESETN */
diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index c64cfead6dc1..e730179d92aa 100644
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -93,10 +93,13 @@ struct smuxed {
 		.width = (_width), \
 	})
 
+#define CPG_SSEL0		(0x300)
+#define CPG_SSEL1		(0x304)
 #define CPG_CDDIV0		(0x400)
 #define CPG_CDDIV1		(0x404)
 #define CPG_CDDIV3		(0x40C)
 #define CPG_CDDIV4		(0x410)
+#define CPG_CSDIV0		(0x500)
 
 #define CDDIV0_DIVCTL1	DDIV_PACK(CPG_CDDIV0, 4, 3, 1)
 #define CDDIV0_DIVCTL2	DDIV_PACK(CPG_CDDIV0, 8, 3, 2)
@@ -111,6 +114,14 @@ struct smuxed {
 #define CDDIV4_DIVCTL1	DDIV_PACK(CPG_CDDIV4, 4, 1, 17)
 #define CDDIV4_DIVCTL2	DDIV_PACK(CPG_CDDIV4, 8, 1, 18)
 
+#define CSDIV0_DIVCTL0	DDIV_PACK(CPG_CSDIV0, 0, 2, CSDIV_NO_MON)
+#define CSDIV0_DIVCTL1	DDIV_PACK(CPG_CSDIV0, 4, 2, CSDIV_NO_MON)
+
+#define SSEL0_SELCTL2	SMUX_PACK(CPG_SSEL0, 8, 1)
+#define SSEL0_SELCTL3	SMUX_PACK(CPG_SSEL0, 12, 1)
+#define SSEL1_SELCTL0	SMUX_PACK(CPG_SSEL1, 0, 1)
+#define SSEL1_SELCTL1	SMUX_PACK(CPG_SSEL1, 4, 1)
+
 #define BUS_MSTOP_IDX_MASK	GENMASK(31, 16)
 #define BUS_MSTOP_BITS_MASK	GENMASK(15, 0)
 #define BUS_MSTOP(idx, mask)	(FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \
-- 
2.49.0

Re: [PATCH v2 9/9] clk: renesas: r9a09g057: Add clock and reset entries for GBETH0/1

[Geert Uytterhoeven]

Hi Prabhakar,

On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add clock and reset entries for GBETH instances. Include core clocks for
> PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks
> used as clock sources for the GBETH IP.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- a/drivers/clk/renesas/r9a09g057-cpg.c
> +++ b/drivers/clk/renesas/r9a09g057-cpg.c

> @@ -78,6 +87,19 @@ static const struct clk_div_table dtable_2_64[] = {
>         {0, 0},
>  };
>
> +static const struct clk_div_table dtable_2_100[] = {
> +       {0, 2},
> +       {1, 10},
> +       {2, 100},
> +       {0, 0},
> +};
> +
> +/* Mux clock tables */
> +static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0-rxc-rxclk" };
> +static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0-txc-txclk" };
> +static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1-rxc-rxclk" };
> +static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1-txc-txclk" };

The "et[01]-[rt]xc-[rt]xclk" clocks are not created by this driver.
IIUIC, they are actually Ethernet PHY signals.
How is this supposed to work?

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 9/9] clk: renesas: r9a09g057: Add clock and reset entries for GBETH0/1

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Tue, Apr 15, 2025 at 3:37 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add clock and reset entries for GBETH instances. Include core clocks for
> > PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks
> > used as clock sources for the GBETH IP.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/clk/renesas/r9a09g057-cpg.c
> > +++ b/drivers/clk/renesas/r9a09g057-cpg.c
>
> > @@ -78,6 +87,19 @@ static const struct clk_div_table dtable_2_64[] = {
> >         {0, 0},
> >  };
> >
> > +static const struct clk_div_table dtable_2_100[] = {
> > +       {0, 2},
> > +       {1, 10},
> > +       {2, 100},
> > +       {0, 0},
> > +};
> > +
> > +/* Mux clock tables */
> > +static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0-rxc-rxclk" };
> > +static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0-txc-txclk" };
> > +static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1-rxc-rxclk" };
> > +static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1-txc-txclk" };
>
> The "et[01]-[rt]xc-[rt]xclk" clocks are not created by this driver.
> IIUIC, they are actually Ethernet PHY signals.
> How is this supposed to work?
>
My intention was to add support for PHY drivers to provide the clocks
and hook them up accordingly. Currently, for the RX clocks, we get a
rate of 0 since they are external.

# cat /sys/kernel/debug/clk/clk_summary | grep eth_0
                gbeth_0_clk_tx_180_i     1   1   0   125000000   0   0
  50000   Y   15c30000.ethernet   tx-180
                gbeth_0_clk_tx_i         1   1   0   125000000   0   0
  50000   Y   15c30000.ethernet   tx
                gbeth_0_clk_ptp_ref_i    1   1   0   125000000   0   0
  50000   Y   15c30000.ethernet   ptp_ref
                gbeth_0_aclk_i           1   1   0   200000000   0   0
  50000   Y   15c30000.ethernet   stmmaceth
                gbeth_0_aclk_csr_i       1   1   0   200000000   0   0
  50000   Y   15c30000.ethernet   pclk
                gbeth_0_clk_rx_180_i     1   1   0   0           0   0
  50000   Y   15c30000.ethernet   rx-180
                gbeth_0_clk_rx_i         1   1   0   0           0   0
  50000   Y   15c30000.ethernet   rx

I haven’t written a prototype yet for the PHY driver to provide the
clocks, but the plan is to get the initial pieces in place and then
extend support for that.

Is my understanding correct that the PHY should provide the clocks? Or
would you suggest a different approach?

Cheers,
Prabhakar

Re: [PATCH v2 9/9] clk: renesas: r9a09g057: Add clock and reset entries for GBETH0/1

[Geert Uytterhoeven]

Hi Prabhakar,

On Tue, 15 Apr 2025 at 21:25, Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> On Tue, Apr 15, 2025 at 3:37 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Add clock and reset entries for GBETH instances. Include core clocks for
> > > PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks
> > > used as clock sources for the GBETH IP.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> > > --- a/drivers/clk/renesas/r9a09g057-cpg.c
> > > +++ b/drivers/clk/renesas/r9a09g057-cpg.c
> >
> > > @@ -78,6 +87,19 @@ static const struct clk_div_table dtable_2_64[] = {
> > >         {0, 0},
> > >  };
> > >
> > > +static const struct clk_div_table dtable_2_100[] = {
> > > +       {0, 2},
> > > +       {1, 10},
> > > +       {2, 100},
> > > +       {0, 0},
> > > +};
> > > +
> > > +/* Mux clock tables */
> > > +static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0-rxc-rxclk" };
> > > +static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0-txc-txclk" };
> > > +static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1-rxc-rxclk" };
> > > +static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1-txc-txclk" };
> >
> > The "et[01]-[rt]xc-[rt]xclk" clocks are not created by this driver.
> > IIUIC, they are actually Ethernet PHY signals.
> > How is this supposed to work?
> >
> My intention was to add support for PHY drivers to provide the clocks
> and hook them up accordingly. Currently, for the RX clocks, we get a
> rate of 0 since they are external.

So the link would not be provided by DT?
If these clocks are inputs to the clock controller, they should be
listed in the clock controller's clock{,-name}s' properties...

> I haven’t written a prototype yet for the PHY driver to provide the
> clocks, but the plan is to get the initial pieces in place and then
> extend support for that.
>
> Is my understanding correct that the PHY should provide the clocks? Or
> would you suggest a different approach?

The Static Mux Control Registers (CPG_SSEL[01]) registers treat them as
clock inputs.  However, Figure 6.3-1 ("Block Diagram of the Ethernet
Interface") shows the TX clocks are bidirectional, so they can be used
as either inputs or outputs?  On RGMII[1], RXC is an input (PHY-to-MAC),
while TXC is an output (MAC-to-PHY).

I'm a bit lost on how this works, and how to model and handle this...

[1] https://en.wikipedia.org/wiki/Media-independent_interface#Reduced_gigabit_media-independent_interface

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 9/9] clk: renesas: r9a09g057: Add clock and reset entries for GBETH0/1

[Lad, Prabhakar]

Hi Geert,

On Wed, Apr 16, 2025 at 8:37 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, 15 Apr 2025 at 21:25, Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > On Tue, Apr 15, 2025 at 3:37 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Add clock and reset entries for GBETH instances. Include core clocks for
> > > > PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks
> > > > used as clock sources for the GBETH IP.
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Thanks for your patch!
> > >
> > > > --- a/drivers/clk/renesas/r9a09g057-cpg.c
> > > > +++ b/drivers/clk/renesas/r9a09g057-cpg.c
> > >
> > > > @@ -78,6 +87,19 @@ static const struct clk_div_table dtable_2_64[] = {
> > > >         {0, 0},
> > > >  };
> > > >
> > > > +static const struct clk_div_table dtable_2_100[] = {
> > > > +       {0, 2},
> > > > +       {1, 10},
> > > > +       {2, 100},
> > > > +       {0, 0},
> > > > +};
> > > > +
> > > > +/* Mux clock tables */
> > > > +static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0-rxc-rxclk" };
> > > > +static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0-txc-txclk" };
> > > > +static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1-rxc-rxclk" };
> > > > +static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1-txc-txclk" };
> > >
> > > The "et[01]-[rt]xc-[rt]xclk" clocks are not created by this driver.
> > > IIUIC, they are actually Ethernet PHY signals.
> > > How is this supposed to work?
> > >
> > My intention was to add support for PHY drivers to provide the clocks
> > and hook them up accordingly. Currently, for the RX clocks, we get a
> > rate of 0 since they are external.
>
> So the link would not be provided by DT?
> If these clocks are inputs to the clock controller, they should be
> listed in the clock controller's clock{,-name}s' properties...
>
> > I haven’t written a prototype yet for the PHY driver to provide the
> > clocks, but the plan is to get the initial pieces in place and then
> > extend support for that.
> >
> > Is my understanding correct that the PHY should provide the clocks? Or
> > would you suggest a different approach?
>
> The Static Mux Control Registers (CPG_SSEL[01]) registers treat them as
> clock inputs.  However, Figure 6.3-1 ("Block Diagram of the Ethernet
> Interface") shows the TX clocks are bidirectional, so they can be used
> as either inputs or outputs?  On RGMII[1], RXC is an input (PHY-to-MAC),
> while TXC is an output (MAC-to-PHY).
>
I think the Figure 6.3-1 shows TX clocks are bidirectional because
PFC_OEN.OEN0/1 can be used to configure input/output for the TXC
pins..

I added the below POC and did some limited testing, (not the code in
PHY driver is not complete as it still needs to check interface mode
and depending on that register one/two clocks)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 76e6b658077a..08d2651eba59 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -105,6 +105,50 @@ L3_CA55: cache-controller-0 {
                };
        };

+       et0_rxclk: et0-rxclk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <0>;
+               /*
+                * This value must be overridden by the board depending
+                * on PHY connection
+                */
+               status = "disabled";
+       };
+
+       et0_txclk: et0-txclk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <0>;
+               /*
+                * This value must be overridden by the board depending
+                * on PHY connection
+                */
+               status = "disabled";
+       };
+
+       et1_rxclk: et1-rxclk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <0>;
+               /*
+                * This value must be overridden by the board depending
+                * on PHY connection
+                */
+               status = "disabled";
+       };
+
+       et1_txclk: et1-txclk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <0>;
+               /*
+                * This value must be overridden by the board depending
+                * on PHY connection
+                */
+               status = "disabled";
+       };
+
        gpu_opp_table: opp-table-1 {
                compatible = "operating-points-v2";

@@ -266,8 +310,12 @@ pinctrl: pinctrl@10410000 {
                cpg: clock-controller@10420000 {
                        compatible = "renesas,r9a09g057-cpg";
                        reg = <0 0x10420000 0 0x10000>;
-                       clocks = <&audio_extal_clk>, <&rtxin_clk>,
<&qextal_clk>;
-                       clock-names = "audio_extal", "rtxin", "qextal";
+                       clocks = <&audio_extal_clk>, <&rtxin_clk>,
<&qextal_clk>,
+                                <&et0_txclk>, <&et0_rxclk>,
+                                <&et1_txclk>, <&et1_rxclk>;
+                       clock-names = "audio_extal", "rtxin", "qextal",
+                                     "et0_txclk", "et0_rxclk",
+                                     "et1_txclk", "et1_rxclk";
                        #clock-cells = <2>;
                        #reset-cells = <1>;
                        #power-domain-cells = <0>;
diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
index d0160ae4d4cd..3f9c9cf1a468 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
@@ -136,6 +136,11 @@ &audio_extal_clk {
        clock-frequency = <22579200>;
 };

+&cpg {
+       clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>,
+                <&phy0 0>, <&phy0 1>, <&phy1 0>, <&phy1 1>;
+};
+
 &cru0 {
        status = "disabled";
 };
@@ -248,6 +253,8 @@ mdio {

                phy0: ethernet-phy@0 {
                        compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
+                       #clock-cells = <1>;
+                       clock-output-names = "et0_rxclk", "et0_txclk";
                        reg = <0>;
                        rxc-skew-psec = <0>;
                        txc-skew-psec = <0>;
@@ -279,6 +286,8 @@ mdio {

                phy1: ethernet-phy@1 {
                        compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
+                       #clock-cells = <1>;
+                       clock-output-names = "et1_rxclk", "et1_txclk";
                        reg = <0>;
                        rxc-skew-psec = <0>;
                        txc-skew-psec = <0>;
diff --git a/drivers/clk/renesas/r9a09g057-cpg.c
b/drivers/clk/renesas/r9a09g057-cpg.c
index 94c959577f03..5a0f0b9e62c6 100644
--- a/drivers/clk/renesas/r9a09g057-cpg.c
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -23,6 +23,10 @@ enum clk_ids {
        CLK_AUDIO_EXTAL,
        CLK_RTXIN,
        CLK_QEXTAL,
+       CLK_ET0_RXCLK,
+       CLK_ET0_TXCLK,
+       CLK_ET1_RXCLK,
+       CLK_ET1_TXCLK,

        /* PLL Clocks */
        CLK_PLLCM33,
@@ -128,16 +132,20 @@ static const struct clk_div_table dtable_16_128[] = {
 };

 /* Mux clock tables */
-static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0",
"et0-rxc-rxclk" };
-static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0",
"et0-txc-txclk" };
-static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1",
"et1-rxc-rxclk" };
-static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1",
"et1-txc-txclk" };
+static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
+static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
+static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" };
+static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1_txclk" };

 static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
        /* External Clock Inputs */
        DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
        DEF_INPUT("rtxin", CLK_RTXIN),
        DEF_INPUT("qextal", CLK_QEXTAL),
+       DEF_INPUT("et0_rxclk", CLK_ET0_RXCLK),
+       DEF_INPUT("et0_txclk", CLK_ET0_TXCLK),
+       DEF_INPUT("et1_rxclk", CLK_ET1_RXCLK),
+       DEF_INPUT("et1_txclk", CLK_ET1_TXCLK),

        /* PLL Clocks */
        DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 71fb4410c31b..79245b81a8dc 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -20,6 +20,7 @@
  */

 #include <linux/bitfield.h>
+#include <linux/clk-provider.h>
 #include <linux/ethtool_netlink.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
@@ -362,6 +363,13 @@
 /* Delay used to get the second part from the LTC */
 #define LAN8841_GET_SEC_LTC_DELAY              (500 * NSEC_PER_MSEC)

+struct micrel_phy_clk {
+       struct phy_device *phydev;
+       struct clk_hw clk[2];
+};
+
+static struct micrel_phy_clk phy_clk;
+
 struct kszphy_hw_stat {
        const char *string;
        u8 reg;
@@ -1527,7 +1535,11 @@ static int ksz9131_read_status(struct phy_device *phydev)
        if (ret < 0)
                return ret;

-       return genphy_read_status(phydev);
+       ret = genphy_read_status(phydev);
+       clk_set_rate(phy_clk.clk[0].clk, rgmii_clock(phydev->speed));
+       clk_set_rate(phy_clk.clk[1].clk, rgmii_clock(phydev->speed));
+       return ret;
 }

 static int ksz9131_config_aneg(struct phy_device *phydev)
@@ -2272,6 +2284,41 @@ static int ksz8061_suspend(struct phy_device *phydev)
        return kszphy_suspend(phydev);
 }

+static struct clk_hw *kszphy_of_clk_get(struct of_phandle_args *clkspec,
+                                       void *data)
+{
+       unsigned int idx = clkspec->args[0];
+       struct clk_hw **clkout_hw = data;
+
+       if (idx >= ARRAY_SIZE(phy_clk.clk))
+               return ERR_PTR(-EINVAL);
+
+       return clkout_hw[idx];
+}
+
+static unsigned long phy_clk_recalc_rate(struct clk_hw *hw, unsigned
long parent_rate)
+{
+       if (phy_clk.phydev->speed == SPEED_1000)
+               return 125000000UL;
+       else if (phy_clk.phydev->speed == SPEED_100)
+               return 25000000UL;
+       else if (phy_clk.phydev->speed == SPEED_10)
+               return 2500000UL;
+       else
+               return 0;
+}
+
+static long phy_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                              unsigned long *parent_rate)
+{
+       return clamp(rate, 2500000UL, 125000000UL);
+}
+
+static const struct clk_ops phy_clk_ops = {
+       .recalc_rate   = phy_clk_recalc_rate,
+       .round_rate    = phy_clk_round_rate,
+};
+
 static int kszphy_probe(struct phy_device *phydev)
 {
        const struct kszphy_type *type = phydev->drv->driver_data;
@@ -2329,7 +2376,32 @@ static int kszphy_probe(struct phy_device *phydev)
                priv->rmii_ref_clk_sel_val = true;
        }

-       return 0;
+       phy_clk.phydev = phydev;
+       /* Register clk outputs */
+       for (u8 i = 0; i < 2; i++) {
+               struct clk_init_data init;
+               const char *name;
+               int ret;
+
+               phy_clk.clk[i].init = &init;
+               ret = of_property_read_string_index(phydev->mdio.dev.of_node,
+                                                   "clock-output-names",
+                                                   i, &name);
+               if (ret) {
+                       phydev_err(phydev, "Failed to get clock name %d\n", i);
+                       return ret;
+               }
+               init.name = name;
+               init.ops = &phy_clk_ops;
+               init.flags = 0;
+               init.parent_names = NULL;
+               init.num_parents = 0;
+               ret = devm_clk_hw_register(&phydev->mdio.dev, &phy_clk.clk[i]);
+               if (ret)
+                       return ret;
+       }
+
+       return devm_of_clk_add_hw_provider(&phydev->mdio.dev,
kszphy_of_clk_get, &phy_clk.clk);
 }

 static int lan8814_cable_test_start(struct phy_device *phydev)


Below are the logs:
root@rzv2h-evk:~# cat /sys/kernel/debug/clk/clk_summary | grep gbeth_0
       gbeth_0_clk_rx_180_i          1       1        0
125000000   0          0     50000      Y         15c30000.ethernet
           rx-180
       gbeth_0_clk_rx_i              1       1        0
125000000   0          0     50000      Y         15c30000.ethernet
           rx
                gbeth_0_clk_tx_180_i 1       1        0
125000000   0          0     50000      Y
15c30000.ethernet               tx-180
                gbeth_0_clk_tx_i     1       1        0
125000000   0          0     50000      Y
15c30000.ethernet               tx
             gbeth_0_clk_ptp_ref_i   1       1        0
125000000   0          0     50000      Y
15c30000.ethernet               ptp_ref
          gbeth_0_aclk_i             1       1        0
200000000   0          0     50000      Y            15c30000.ethernet
              stmmaceth
          gbeth_0_aclk_csr_i         1       1        0
200000000   0          0     50000      Y            15c30000.ethernet
              pclk
root@rzv2h-evk:~#
root@rzv2h-evk:~#
root@rzv2h-evk:~#
root@rzv2h-evk:~# [   44.853189] kauditd_printk_skb: 5 callbacks suppressed
[   44.853204] audit: type=1334 audit(1744888354.247:22): prog-id=18 op=UNLOAD
[   44.865320] audit: type=1334 audit(1744888354.247:23): prog-id=17 op=UNLOAD
[   44.872331] audit: type=1334 audit(1744888354.247:24): prog-id=16 op=UNLOAD

root@rzv2h-evk:~#
root@rzv2h-evk:~# ethtool -s end0 speed 100
[   97.153939] renesas-gbeth 15c30000.ethernet end0: Link is Down

[  101.258899] renesas-gbeth 15c30000.ethernet end0: Link is Up -
100Mbps/Full - flow control rx/tx
root@rzv2h-evk:~#
root@rzv2h-evk:~#
root@rzv2h-evk:~# cat /sys/kernel/debug/clk/clk_summary | grep gbeth_0
       gbeth_0_clk_rx_180_i          1       1        0
25000000    0          0     50000      Y         15c30000.ethernet
           rx-180
       gbeth_0_clk_rx_i              1       1        0
25000000    0          0     50000      Y         15c30000.ethernet
           rx
                gbeth_0_clk_tx_180_i 1       1        0
25000000    0          0     50000      Y
15c30000.ethernet               tx-180
                gbeth_0_clk_tx_i     1       1        0
25000000    0          0     50000      Y
15c30000.ethernet               tx
             gbeth_0_clk_ptp_ref_i   1       1        0
125000000   0          0     50000      Y
15c30000.ethernet               ptp_ref
          gbeth_0_aclk_i             1       1        0
200000000   0          0     50000      Y            15c30000.ethernet
              stmmaceth
          gbeth_0_aclk_csr_i         1       1        0
200000000   0          0     50000      Y            15c30000.ethernet
              pclk
root@rzv2h-evk:~# ethtool -s end0 speed 10
root@rzv2h-evk:~# [  117.300170] renesas-gbeth 15c30000.ethernet end0:
Link is Down
[  119.338798] renesas-gbeth 15c30000.ethernet end0: Link is Up -
10Mbps/Full - flow control rx/tx

root@rzv2h-evk:~# cat /sys/kernel/debug/clk/clk_summary | grep gbeth_0
       gbeth_0_clk_rx_180_i          1       1        0        2500000
    0          0     50000      Y         15c30000.ethernet
   rx-180
       gbeth_0_clk_rx_i              1       1        0        2500000
    0          0     50000      Y         15c30000.ethernet
   rx
                gbeth_0_clk_tx_180_i 1       1        0        2500000
    0          0     50000      Y                  15c30000.ethernet
            tx-180
                gbeth_0_clk_tx_i     1       1        0        2500000
    0          0     50000      Y                  15c30000.ethernet
            tx
             gbeth_0_clk_ptp_ref_i   1       1        0
125000000   0          0     50000      Y
15c30000.ethernet               ptp_ref
          gbeth_0_aclk_i             1       1        0
200000000   0          0     50000      Y            15c30000.ethernet
              stmmaceth
          gbeth_0_aclk_csr_i         1       1        0
200000000   0          0     50000      Y            15c30000.ethernet
              pclk


Cheers,
Prabhakar

Re: [PATCH v2 9/9] clk: renesas: r9a09g057: Add clock and reset entries for GBETH0/1

[Geert Uytterhoeven]

Hi Prabhakar,

On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add clock and reset entries for GBETH instances. Include core clocks for
> PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks
> used as clock sources for the GBETH IP.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  drivers/clk/renesas/r9a09g057-cpg.c | 72 +++++++++++++++++++++++++++++
>  drivers/clk/renesas/rzv2h-cpg.h     | 11 +++++
>  2 files changed, 83 insertions(+)
>
> diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
> index 3c40e36259fe..057bfa0e2a57 100644
> --- a/drivers/clk/renesas/r9a09g057-cpg.c
> +++ b/drivers/clk/renesas/r9a09g057-cpg.c

> @@ -115,6 +138,17 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
>         DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4),
>         DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4),
>
> +       DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
> +       DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
> +       DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0,
> +                 CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL0, dtable_2_100),
> +       DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1,
> +                 CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL1, dtable_2_100),
> +       DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk),
> +       DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
> +       DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
> +       DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
> +
>         DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
>
>         /* Core Clocks */

> @@ -233,6 +271,38 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
>                                                 BUS_MSTOP(7, BIT(10))),
>         DEF_MOD("usb2_0_pclk_usbtst1",          CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
>                                                 BUS_MSTOP(7, BIT(11))),
> +       DEF_MOD_EXTERNAL("gbeth_0_clk_tx_i",    CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
> +                                               BUS_MSTOP(8, BIT(5)),
> +                                               0x300, 8, 1),

CPG_SSEL0

I'm wondering if you really have to store and duplicate this info here.
Can't you infer it from the parent's smux description?

> +       DEF_MOD_EXTERNAL("gbeth_0_clk_rx_i",    CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
> +                                               BUS_MSTOP(8, BIT(5)),
> +                                               0x300, 12, 1),
> +       DEF_MOD_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
> +                                               BUS_MSTOP(8, BIT(5)),
> +                                               0x300, 8, 1),
> +       DEF_MOD_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
> +                                               BUS_MSTOP(8, BIT(5)),
> +                                               0x300, 12, 1),
> +       DEF_MOD("gbeth_0_aclk_csr_i",           CLK_PLLDTY_DIV8, 11, 12, 5, 28,
> +                                               BUS_MSTOP(8, BIT(5))),
> +       DEF_MOD("gbeth_0_aclk_i",               CLK_PLLDTY_DIV8, 11, 13, 5, 29,
> +                                               BUS_MSTOP(8, BIT(5))),
> +       DEF_MOD_EXTERNAL("gbeth_1_clk_tx_i",    CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
> +                                               BUS_MSTOP(8, BIT(6)),
> +                                               0x304, 8, 1),

CPG_SSEL0

> +       DEF_MOD_EXTERNAL("gbeth_1_clk_rx_i",    CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
> +                                               BUS_MSTOP(8, BIT(6)),
> +                                               0x304, 12, 1),
> +       DEF_MOD_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0,
> +                                               BUS_MSTOP(8, BIT(6)),
> +                                               0x304, 8, 1),
> +       DEF_MOD_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
> +                                               BUS_MSTOP(8, BIT(6)),
> +                                               0x304, 12, 1),
> +       DEF_MOD("gbeth_1_aclk_csr_i",           CLK_PLLDTY_DIV8, 12, 2, 6, 2,
> +                                               BUS_MSTOP(8, BIT(6))),
> +       DEF_MOD("gbeth_1_aclk_i",               CLK_PLLDTY_DIV8, 12, 3, 6, 3,
> +                                               BUS_MSTOP(8, BIT(6))),
>         DEF_MOD("cru_0_aclk",                   CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
>                                                 BUS_MSTOP(9, BIT(4))),
>         DEF_MOD_NO_PM("cru_0_vclk",             CLK_PLLVDO_CRU0, 13, 3, 6, 19,
> @@ -304,6 +374,8 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
>         DEF_RST(10, 13, 4, 30),         /* USB2_0_U2H1_HRESETN */
>         DEF_RST(10, 14, 4, 31),         /* USB2_0_U2P_EXL_SYSRST */
>         DEF_RST(10, 15, 5, 0),          /* USB2_0_PRESETN */
> +       DEF_RST(11, 0, 5, 1),           /* GBETH_0_ARESETN_I */
> +       DEF_RST(11, 1, 5, 2),           /* GBETH_1_ARESETN_I */
>         DEF_RST(12, 5, 5, 22),          /* CRU_0_PRESETN */
>         DEF_RST(12, 6, 5, 23),          /* CRU_0_ARESETN */
>         DEF_RST(12, 7, 5, 24),          /* CRU_0_S_RESETN */
> diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
> index c64cfead6dc1..e730179d92aa 100644
> --- a/drivers/clk/renesas/rzv2h-cpg.h
> +++ b/drivers/clk/renesas/rzv2h-cpg.h
> @@ -93,10 +93,13 @@ struct smuxed {
>                 .width = (_width), \
>         })
>
> +#define CPG_SSEL0              (0x300)
> +#define CPG_SSEL1              (0x304)
>  #define CPG_CDDIV0             (0x400)
>  #define CPG_CDDIV1             (0x404)
>  #define CPG_CDDIV3             (0x40C)
>  #define CPG_CDDIV4             (0x410)
> +#define CPG_CSDIV0             (0x500)
>
>  #define CDDIV0_DIVCTL1 DDIV_PACK(CPG_CDDIV0, 4, 3, 1)
>  #define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2)
> @@ -111,6 +114,14 @@ struct smuxed {
>  #define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17)
>  #define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18)
>
> +#define CSDIV0_DIVCTL0 DDIV_PACK(CPG_CSDIV0, 0, 2, CSDIV_NO_MON)
> +#define CSDIV0_DIVCTL1 DDIV_PACK(CPG_CSDIV0, 4, 2, CSDIV_NO_MON)
> +
> +#define SSEL0_SELCTL2  SMUX_PACK(CPG_SSEL0, 8, 1)
> +#define SSEL0_SELCTL3  SMUX_PACK(CPG_SSEL0, 12, 1)
> +#define SSEL1_SELCTL0  SMUX_PACK(CPG_SSEL1, 0, 1)
> +#define SSEL1_SELCTL1  SMUX_PACK(CPG_SSEL1, 4, 1)
> +
>  #define BUS_MSTOP_IDX_MASK     GENMASK(31, 16)
>  #define BUS_MSTOP_BITS_MASK    GENMASK(15, 0)
>  #define BUS_MSTOP(idx, mask)   (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 9/9] clk: renesas: r9a09g057: Add clock and reset entries for GBETH0/1

[Lad, Prabhakar]

Hi Geert,

On Tue, Apr 15, 2025 at 3:55 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add clock and reset entries for GBETH instances. Include core clocks for
> > PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks
> > used as clock sources for the GBETH IP.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> >  drivers/clk/renesas/r9a09g057-cpg.c | 72 +++++++++++++++++++++++++++++
> >  drivers/clk/renesas/rzv2h-cpg.h     | 11 +++++
> >  2 files changed, 83 insertions(+)
> >
> > diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
> > index 3c40e36259fe..057bfa0e2a57 100644
> > --- a/drivers/clk/renesas/r9a09g057-cpg.c
> > +++ b/drivers/clk/renesas/r9a09g057-cpg.c
>
> > @@ -115,6 +138,17 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
> >         DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4),
> >         DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4),
> >
> > +       DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
> > +       DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
> > +       DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0,
> > +                 CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL0, dtable_2_100),
> > +       DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1,
> > +                 CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL1, dtable_2_100),
> > +       DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk),
> > +       DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
> > +       DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
> > +       DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
> > +
> >         DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
> >
> >         /* Core Clocks */
>
> > @@ -233,6 +271,38 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
> >                                                 BUS_MSTOP(7, BIT(10))),
> >         DEF_MOD("usb2_0_pclk_usbtst1",          CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
> >                                                 BUS_MSTOP(7, BIT(11))),
> > +       DEF_MOD_EXTERNAL("gbeth_0_clk_tx_i",    CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
> > +                                               BUS_MSTOP(8, BIT(5)),
> > +                                               0x300, 8, 1),
>
> CPG_SSEL0
>
> I'm wondering if you really have to store and duplicate this info here.
> Can't you infer it from the parent's smux description?
>
To clarify, you mean to get the parent of the mod clock and then get
the clk_mux to get the base?

Cheers,
Prabhakar

Re: [PATCH v2 9/9] clk: renesas: r9a09g057: Add clock and reset entries for GBETH0/1

[Geert Uytterhoeven]

Hi Prabhakar,

On Mon, 28 Apr 2025 at 15:22, Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> On Tue, Apr 15, 2025 at 3:55 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Add clock and reset entries for GBETH instances. Include core clocks for
> > > PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks
> > > used as clock sources for the GBETH IP.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > >  drivers/clk/renesas/r9a09g057-cpg.c | 72 +++++++++++++++++++++++++++++
> > >  drivers/clk/renesas/rzv2h-cpg.h     | 11 +++++
> > >  2 files changed, 83 insertions(+)
> > >
> > > diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
> > > index 3c40e36259fe..057bfa0e2a57 100644
> > > --- a/drivers/clk/renesas/r9a09g057-cpg.c
> > > +++ b/drivers/clk/renesas/r9a09g057-cpg.c
> >
> > > @@ -115,6 +138,17 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
> > >         DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4),
> > >         DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4),
> > >
> > > +       DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
> > > +       DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
> > > +       DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0,
> > > +                 CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL0, dtable_2_100),
> > > +       DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1,
> > > +                 CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL1, dtable_2_100),
> > > +       DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk),
> > > +       DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
> > > +       DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
> > > +       DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
> > > +
> > >         DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
> > >
> > >         /* Core Clocks */
> >
> > > @@ -233,6 +271,38 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
> > >                                                 BUS_MSTOP(7, BIT(10))),
> > >         DEF_MOD("usb2_0_pclk_usbtst1",          CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
> > >                                                 BUS_MSTOP(7, BIT(11))),
> > > +       DEF_MOD_EXTERNAL("gbeth_0_clk_tx_i",    CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
> > > +                                               BUS_MSTOP(8, BIT(5)),
> > > +                                               0x300, 8, 1),
> >
> > CPG_SSEL0
> >
> > I'm wondering if you really have to store and duplicate this info here.
> > Can't you infer it from the parent's smux description?
> >
> To clarify, you mean to get the parent of the mod clock and then get
> the clk_mux to get the base?

Indeed.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 9/9] clk: renesas: r9a09g057: Add clock and reset entries for GBETH0/1

[Lad, Prabhakar]

Hi Geert,

On Mon, Apr 28, 2025 at 2:36 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, 28 Apr 2025 at 15:22, Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > On Tue, Apr 15, 2025 at 3:55 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Add clock and reset entries for GBETH instances. Include core clocks for
> > > > PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks
> > > > used as clock sources for the GBETH IP.
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > >  drivers/clk/renesas/r9a09g057-cpg.c | 72 +++++++++++++++++++++++++++++
> > > >  drivers/clk/renesas/rzv2h-cpg.h     | 11 +++++
> > > >  2 files changed, 83 insertions(+)
> > > >
> > > > diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
> > > > index 3c40e36259fe..057bfa0e2a57 100644
> > > > --- a/drivers/clk/renesas/r9a09g057-cpg.c
> > > > +++ b/drivers/clk/renesas/r9a09g057-cpg.c
> > >
> > > > @@ -115,6 +138,17 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
> > > >         DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4),
> > > >         DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4),
> > > >
> > > > +       DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
> > > > +       DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
> > > > +       DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0,
> > > > +                 CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL0, dtable_2_100),
> > > > +       DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1,
> > > > +                 CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL1, dtable_2_100),
> > > > +       DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk),
> > > > +       DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
> > > > +       DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
> > > > +       DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
> > > > +
> > > >         DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
> > > >
> > > >         /* Core Clocks */
> > >
> > > > @@ -233,6 +271,38 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
> > > >                                                 BUS_MSTOP(7, BIT(10))),
> > > >         DEF_MOD("usb2_0_pclk_usbtst1",          CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
> > > >                                                 BUS_MSTOP(7, BIT(11))),
> > > > +       DEF_MOD_EXTERNAL("gbeth_0_clk_tx_i",    CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
> > > > +                                               BUS_MSTOP(8, BIT(5)),
> > > > +                                               0x300, 8, 1),
> > >
> > > CPG_SSEL0
> > >
> > > I'm wondering if you really have to store and duplicate this info here.
> > > Can't you infer it from the parent's smux description?
> > >
> > To clarify, you mean to get the parent of the mod clock and then get
> > the clk_mux to get the base?
>
> Indeed.
>
Thank you for the clarification.

Cheers,
Prabhakar