[PATCH 00/13] arm64: dts: renesas: Add support for SCI/LEDs/I2C/MMC on RZ/{T2H,RZ/N2H} SoCs and boards

[PATCH 00/13] arm64: dts: renesas: Add support for SCI/LEDs/I2C/MMC on RZ/{T2H,RZ/N2H} SoCs and boards

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi All,

Extend hardware support on Renesas RZ/T2H and RZ/N2H SoCs and evaluation
boards. Below are the features added for the RZ/T2H and RZ/N2H SoCs and
EVKs:
- Add SCI nodes for RZ/T2H and RZ/N2H SoCs.
- Enable I2C0 and I2C1 support
- Enable EEPROM on I2C0
- Enable LEDs on RZ/T2H and RZ/N2H EVKs.
- Enable MMC on RZ/T2H and RZ/N2H EVKs.
- Enable MicroSD card slot on RZ/T2H and RZ/N2H EVKs.
- Enable SD card slot on RZ/T2H and RZ/N2H EVKs.

Cheers,
Prabhakar

Lad Prabhakar (12):
  arm64: dts: renesas: r9a09g077: Add DT nodes for SCI channels 1-5
  arm64: dts: renesas: r9a09g087: Add DT nodes for SCI channels 1-5
  arm64: dts: renesas: r9a09g087: Add pinctrl node
  arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Add user LEDs
  arm64: dts: renesas: r9a09g087m44-rzn2h-evk: Add user LEDs
  arm64: dts: renesas: rzt2h-evk-common: Add pinctrl for SCI0 node
  arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Enable I2C0 and I2C1
    support
  arm64: dts: renesas: r9a09g087m44-rzt2h-evk: Enable I2C0 and I2C1
    support
  arm64: dts: renesas: rzt2h-evk-common: Enable EEPROM on I2C0
  arm64: dts: renesas: rzt2h/rzn2h: Enable eMMC
  arm64: dts: renesas: rzt2h/rzn2h: Enable MicroSD card slot
  arm64: dts: renesas: rzt2h/rzn2h: Enable SD card slot

Thierry Bultel (1):
  arm64: dts: renesas: r9a09g077: Add pinctrl node

 arch/arm64/boot/dts/renesas/r9a09g077.dtsi    |  83 ++++++++
 .../dts/renesas/r9a09g077m44-rzt2h-evk.dts    | 108 ++++++++++
 arch/arm64/boot/dts/renesas/r9a09g087.dtsi    |  94 +++++++++
 .../dts/renesas/r9a09g087m44-rzn2h-evk.dts    | 134 ++++++++++++
 .../dts/renesas/rzt2h-n2h-evk-common.dtsi     | 196 ++++++++++++++++++
 5 files changed, 615 insertions(+)

-- 
2.50.1

[PATCH 01/13] arm64: dts: renesas: r9a09g077: Add DT nodes for SCI channels 1-5

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

The RZ/T2H SoC exposes six SCI controllers; sci0 was already present in
the SoC DTSI. Add the remaining SCI nodes (sci1-sci5).

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 70 ++++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index b16fd9259d8d..8ee88b8e8f33 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -90,6 +90,76 @@ sci0: serial@80005000 {
 			status = "disabled";
 		};
 
+		sci1: serial@80005400 {
+			compatible = "renesas,r9a09g077-rsci";
+			reg = <0 0x80005400 0 0x400>;
+			interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 595 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 596 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 9>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
+			clock-names = "operation", "bus";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		sci2: serial@80005800 {
+			compatible = "renesas,r9a09g077-rsci";
+			reg = <0 0x80005800 0 0x400>;
+			interrupts = <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 599 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 600 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 10>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
+			clock-names = "operation", "bus";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		sci3: serial@80005c00 {
+			compatible = "renesas,r9a09g077-rsci";
+			reg = <0 0x80005c00 0 0x400>;
+			interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 11>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
+			clock-names = "operation", "bus";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		sci4: serial@80006000 {
+			compatible = "renesas,r9a09g077-rsci";
+			reg = <0 0x80006000 0 0x400>;
+			interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 607 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 608 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 12>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
+			clock-names = "operation", "bus";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		sci5: serial@81005000 {
+			compatible = "renesas,r9a09g077-rsci";
+			reg = <0 0x81005000 0 0x400>;
+			interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 611 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 612 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 600>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
+			clock-names = "operation", "bus";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
 		i2c0: i2c@80088000 {
 			compatible = "renesas,riic-r9a09g077";
 			reg = <0 0x80088000 0 0x400>;
-- 
2.50.1

Re: [PATCH 01/13] arm64: dts: renesas: r9a09g077: Add DT nodes for SCI channels 1-5

[Geert Uytterhoeven]

On Tue, 12 Aug 2025 at 22:03, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> The RZ/T2H SoC exposes six SCI controllers; sci0 was already present in
> the SoC DTSI. Add the remaining SCI nodes (sci1-sci5).
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.18.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 02/13] arm64: dts: renesas: r9a09g087: Add DT nodes for SCI channels 1-5

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

The RZ/N2H SoC exposes six SCI controllers; sci0 was already present in
the SoC DTSI. Add the remaining SCI nodes (sci1-sci5).

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 70 ++++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
index 4da21199d22e..7dcaee711486 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
@@ -90,6 +90,76 @@ sci0: serial@80005000 {
 			status = "disabled";
 		};
 
+		sci1: serial@80005400 {
+			compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
+			reg = <0 0x80005400 0 0x400>;
+			interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 595 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 596 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 9>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
+			clock-names = "operation", "bus";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		sci2: serial@80005800 {
+			compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
+			reg = <0 0x80005800 0 0x400>;
+			interrupts = <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 599 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 600 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 10>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
+			clock-names = "operation", "bus";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		sci3: serial@80005c00 {
+			compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
+			reg = <0 0x80005c00 0 0x400>;
+			interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 11>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
+			clock-names = "operation", "bus";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		sci4: serial@80006000 {
+			compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
+			reg = <0 0x80006000 0 0x400>;
+			interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 607 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 608 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 12>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
+			clock-names = "operation", "bus";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		sci5: serial@81005000 {
+			compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
+			reg = <0 0x81005000 0 0x400>;
+			interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 611 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 612 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 600>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
+			clock-names = "operation", "bus";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
 		i2c0: i2c@80088000 {
 			compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077";
 			reg = <0 0x80088000 0 0x400>;
-- 
2.50.1

Re: [PATCH 02/13] arm64: dts: renesas: r9a09g087: Add DT nodes for SCI channels 1-5

[Geert Uytterhoeven]

On Tue, 12 Aug 2025 at 22:03, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> The RZ/N2H SoC exposes six SCI controllers; sci0 was already present in
> the SoC DTSI. Add the remaining SCI nodes (sci1-sci5).
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.18.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 03/13] arm64: dts: renesas: r9a09g077: Add pinctrl node

[Prabhakar]

From: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>

Add pinctrl node to RZ/T2H ("R9A09G077") SoC DTSI.

Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index 8ee88b8e8f33..0929ce2db05c 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -216,6 +216,19 @@ cpg: clock-controller@80280000 {
 			#power-domain-cells = <0>;
 		};
 
+		pinctrl: pinctrl@802c0000 {
+			compatible = "renesas,r9a09g077-pinctrl";
+			reg = <0 0x802c0000 0 0x10000>,
+			      <0 0x812c0000 0 0x10000>,
+			      <0 0x802b0000 0 0x10000>;
+			reg-names = "nsr", "srs", "srn";
+			clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl 0 0 288>;
+			power-domains = <&cpg>;
+		};
+
 		gic: interrupt-controller@83000000 {
 			compatible = "arm,gic-v3";
 			reg = <0x0 0x83000000 0 0x40000>,
-- 
2.50.1

Re: [PATCH 03/13] arm64: dts: renesas: r9a09g077: Add pinctrl node

[Geert Uytterhoeven]

On Tue, 12 Aug 2025 at 22:03, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
>
> Add pinctrl node to RZ/T2H ("R9A09G077") SoC DTSI.
>
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.18.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 04/13] arm64: dts: renesas: r9a09g087: Add pinctrl node

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add pinctrl node to RZ/N2H ("R9A09G087") SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 24 ++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
index 7dcaee711486..3d243096b04c 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
@@ -5,6 +5,17 @@
  * Copyright (C) 2025 Renesas Electronics Corp.
  */
 
+#define RZN2H_PINS_PER_PORT    8
+
+/*
+ * Create the pin index from its bank and position numbers and store in
+ * the upper 16 bits the alternate function identifier
+ */
+#define RZN2H_PORT_PINMUX(b, p, f)     ((b) * RZN2H_PINS_PER_PORT + (p) | ((f) << 16))
+
+/* Convert a port and pin label to its global pin index */
+#define RZN2H_GPIO(port, pin)  ((port) * RZN2H_PINS_PER_PORT + (pin))
+
 #include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
@@ -216,6 +227,19 @@ cpg: clock-controller@80280000 {
 			#power-domain-cells = <0>;
 		};
 
+		pinctrl: pinctrl@802c0000 {
+			compatible = "renesas,r9a09g087-pinctrl";
+			reg = <0 0x802c0000 0 0x10000>,
+			      <0 0x812c0000 0 0x10000>,
+			      <0 0x802b0000 0 0x10000>;
+			reg-names = "nsr", "srs", "srn";
+			clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl 0 0 280>;
+			power-domains = <&cpg>;
+		};
+
 		gic: interrupt-controller@83000000 {
 			compatible = "arm,gic-v3";
 			reg = <0x0 0x83000000 0 0x40000>,
-- 
2.50.1

Re: [PATCH 04/13] arm64: dts: renesas: r9a09g087: Add pinctrl node

[Geert Uytterhoeven]

Hi Prabhakar,

On Tue, 12 Aug 2025 at 22:03, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add pinctrl node to RZ/N2H ("R9A09G087") SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
> @@ -5,6 +5,17 @@
>   * Copyright (C) 2025 Renesas Electronics Corp.
>   */
>
> +#define RZN2H_PINS_PER_PORT    8
> +
> +/*
> + * Create the pin index from its bank and position numbers and store in
> + * the upper 16 bits the alternate function identifier
> + */
> +#define RZN2H_PORT_PINMUX(b, p, f)     ((b) * RZN2H_PINS_PER_PORT + (p) | ((f) << 16))
> +
> +/* Convert a port and pin label to its global pin index */
> +#define RZN2H_GPIO(port, pin)  ((port) * RZN2H_PINS_PER_PORT + (pin))

Shouldn't this be in a header file under include/dt-bindings/pinctrl/?
Else you have to duplicate these definitions in DT overlays.

The rest LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 04/13] arm64: dts: renesas: r9a09g087: Add pinctrl node

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Mon, Aug 18, 2025 at 2:34 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, 12 Aug 2025 at 22:03, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add pinctrl node to RZ/N2H ("R9A09G087") SoC DTSI.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
> > @@ -5,6 +5,17 @@
> >   * Copyright (C) 2025 Renesas Electronics Corp.
> >   */
> >
> > +#define RZN2H_PINS_PER_PORT    8
> > +
> > +/*
> > + * Create the pin index from its bank and position numbers and store in
> > + * the upper 16 bits the alternate function identifier
> > + */
> > +#define RZN2H_PORT_PINMUX(b, p, f)     ((b) * RZN2H_PINS_PER_PORT + (p) | ((f) << 16))
> > +
> > +/* Convert a port and pin label to its global pin index */
> > +#define RZN2H_GPIO(port, pin)  ((port) * RZN2H_PINS_PER_PORT + (pin))
>
> Shouldn't this be in a header file under include/dt-bindings/pinctrl/?
Agreed, theT2H related macros are used in the driver whereas the above
aren't. In the past DT maintainers opposed including such headers
which aren't used in the DT and drivers. Hence I choose this approach.
Please let me know if you want me to move this into a header file
under dt-bindings.

> Else you have to duplicate these definitions in DT overlays.
>
> The rest LGTM, so
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>

Cheers,
Prabhakar

Re: [PATCH 04/13] arm64: dts: renesas: r9a09g087: Add pinctrl node

[Geert Uytterhoeven]

Hi Prabhakar,

On Mon, 18 Aug 2025 at 15:44, Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> On Mon, Aug 18, 2025 at 2:34 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Tue, 12 Aug 2025 at 22:03, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Add pinctrl node to RZ/N2H ("R9A09G087") SoC DTSI.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> > > --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
> > > @@ -5,6 +5,17 @@
> > >   * Copyright (C) 2025 Renesas Electronics Corp.
> > >   */
> > >
> > > +#define RZN2H_PINS_PER_PORT    8
> > > +
> > > +/*
> > > + * Create the pin index from its bank and position numbers and store in
> > > + * the upper 16 bits the alternate function identifier
> > > + */
> > > +#define RZN2H_PORT_PINMUX(b, p, f)     ((b) * RZN2H_PINS_PER_PORT + (p) | ((f) << 16))
> > > +
> > > +/* Convert a port and pin label to its global pin index */
> > > +#define RZN2H_GPIO(port, pin)  ((port) * RZN2H_PINS_PER_PORT + (pin))
> >
> > Shouldn't this be in a header file under include/dt-bindings/pinctrl/?
>
> Agreed, theT2H related macros are used in the driver whereas the above
> aren't. In the past DT maintainers opposed including such headers
> which aren't used in the DT and drivers. Hence I choose this approach.
> Please let me know if you want me to move this into a header file
> under dt-bindings.

We need to share the definitions between DT sources and DT overlay
sources, so that sounds like a convincing argument for a header file
to me.

Now, as RZT2H_PORT_PINMUX() must be identical to RZN2H_PORT_PINMUX(),
this could be the existing
<dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h> file
(cfr. my comment on [PATCH 07/13]).

> > Else you have to duplicate these definitions in DT overlays.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 05/13] arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Add user LEDs

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add USER LED0-LED8, which are available on RZ/T2H EVK.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../dts/renesas/r9a09g077m44-rzt2h-evk.dts    | 51 +++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
index 486584fefead..a0cf01978f15 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
@@ -7,10 +7,61 @@
 
 /dts-v1/;
 
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
+
 #include "r9a09g077m44.dtsi"
 #include "rzt2h-n2h-evk-common.dtsi"
 
 / {
 	model = "Renesas RZ/T2H EVK Board based on r9a09g077m44";
 	compatible = "renesas,rzt2h-evk", "renesas,r9a09g077m44", "renesas,r9a09g077";
+
+	leds {
+		compatible = "gpio-leds";
+
+		led0 {
+			/* SW8-9: ON, SW8-10: OFF */
+			gpios = <&pinctrl RZT2H_GPIO(23, 1) GPIO_ACTIVE_LOW>;
+		};
+
+		led1 {
+			/* SW5-1: OFF, SW5-2: ON */
+			gpios = <&pinctrl RZT2H_GPIO(32, 2) GPIO_ACTIVE_LOW>;
+		};
+
+		led2 {
+			gpios = <&pinctrl RZT2H_GPIO(6, 7) GPIO_ACTIVE_LOW>;
+		};
+
+		led3 {
+			/* SW2-3: OFF */
+			gpios = <&pinctrl RZT2H_GPIO(8, 5) GPIO_ACTIVE_LOW>;
+		};
+
+		led4 {
+			/* SW8-3: ON, SW8-4: OFF */
+			gpios = <&pinctrl RZT2H_GPIO(18, 0) GPIO_ACTIVE_LOW>;
+		};
+
+		led5 {
+			/* SW8-1: ON, SW8-2: OFF */
+			gpios = <&pinctrl RZT2H_GPIO(18, 1) GPIO_ACTIVE_LOW>;
+		};
+
+		led6 {
+			/* SW5-9: OFF, SW5-10: ON */
+			gpios = <&pinctrl RZT2H_GPIO(22, 7) GPIO_ACTIVE_LOW>;
+		};
+
+		led7 {
+			/* SW5-7: OFF, SW5-8: ON */
+			gpios = <&pinctrl RZT2H_GPIO(23, 0) GPIO_ACTIVE_LOW>;
+		};
+
+		led8 {
+			/* SW7-5: OFF, SW7-6: ON */
+			gpios = <&pinctrl RZT2H_GPIO(23, 5) GPIO_ACTIVE_LOW>;
+		};
+	};
 };
-- 
2.50.1

Re: [PATCH 05/13] arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Add user LEDs

[Geert Uytterhoeven]

Hi Prabhakar,

Thanks for your patch!

On Tue, 12 Aug 2025 at 22:03, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add USER LED0-LED8, which are available on RZ/T2H EVK.

According to the schematics, only the first four are user LEDs?

>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

> --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
> +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
> @@ -7,10 +7,61 @@
>
>  /dts-v1/;
>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
> +
>  #include "r9a09g077m44.dtsi"
>  #include "rzt2h-n2h-evk-common.dtsi"
>
>  / {
>         model = "Renesas RZ/T2H EVK Board based on r9a09g077m44";
>         compatible = "renesas,rzt2h-evk", "renesas,r9a09g077m44", "renesas,r9a09g077";
> +
> +       leds {
> +               compatible = "gpio-leds";
> +
> +               led0 {

led-0

Cfr. Documentation/devicetree/bindings/leds/leds-gpio.yaml:

    # The first form is preferred, but fall back to just 'led' anywhere in the
    # node name to at least catch some child nodes.
    "(^led-[0-9a-f]$|led)":

> +                       /* SW8-9: ON, SW8-10: OFF */
> +                       gpios = <&pinctrl RZT2H_GPIO(23, 1) GPIO_ACTIVE_LOW>;

color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_DEBUG;
function-enumerator = <0>;

> +               };
> +
> +               led1 {
> +                       /* SW5-1: OFF, SW5-2: ON */
> +                       gpios = <&pinctrl RZT2H_GPIO(32, 2) GPIO_ACTIVE_LOW>;

color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_DEBUG;
function-enumerator = <1>;

> +               };
> +
> +               led2 {
> +                       gpios = <&pinctrl RZT2H_GPIO(6, 7) GPIO_ACTIVE_LOW>;

color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_DEBUG;
function-enumerator = <2>;

> +               };
> +
> +               led3 {
> +                       /* SW2-3: OFF */
> +                       gpios = <&pinctrl RZT2H_GPIO(8, 5) GPIO_ACTIVE_LOW>;

color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_DEBUG;
function-enumerator = <3>;

> +               };
> +
> +               led4 {
> +                       /* SW8-3: ON, SW8-4: OFF */
> +                       gpios = <&pinctrl RZT2H_GPIO(18, 0) GPIO_ACTIVE_LOW>;

Schematics say "run", so perhaps LED_FUNCTION_ACTIVITY?

    color = <LED_COLOR_ID_GREEN>;
    function = LED_FUNCTION_ACTIVITY;

> +               };
> +
> +               led5 {
> +                       /* SW8-1: ON, SW8-2: OFF */
> +                       gpios = <&pinctrl RZT2H_GPIO(18, 1) GPIO_ACTIVE_LOW>;

Schematics say "error", so

    color = <LED_COLOR_ID_RED>;
    function = LED_FUNCTION_FAULT;

> +               };
> +
> +               led6 {
> +                       /* SW5-9: OFF, SW5-10: ON */
> +                       gpios = <&pinctrl RZT2H_GPIO(22, 7) GPIO_ACTIVE_LOW>;

Schematics says Ether-Cat link-activity, so LED_FUNCTION_LAN?

    color = <LED_COLOR_ID_GREEN>;
    function = LED_FUNCTION_LAN;
    function-enumerator = <0>;

> +               };
> +
> +               led7 {
> +                       /* SW5-7: OFF, SW5-8: ON */
> +                       gpios = <&pinctrl RZT2H_GPIO(23, 0) GPIO_ACTIVE_LOW>;

color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
function-enumerator = <1>;

> +               };
> +
> +               led8 {
> +                       /* SW7-5: OFF, SW7-6: ON */
> +                       gpios = <&pinctrl RZT2H_GPIO(23, 5) GPIO_ACTIVE_LOW>;

color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
function-enumerator = <2>;

> +               };
> +       };
>  };

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 05/13] arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Add user LEDs

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Mon, Aug 18, 2025 at 2:15 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> Thanks for your patch!
>
> On Tue, 12 Aug 2025 at 22:03, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add USER LED0-LED8, which are available on RZ/T2H EVK.
>
> According to the schematics, only the first four are user LEDs?
>
As per [0] user manual Table 7-4, LEDs4-8 can be used as USER LEDs or
for Ethercat Slave. Since ESC is not enabled I haven't added any
#ifdefs.

[0] https://www.renesas.com/en/document/mat/rzt2h-evaluation-board-kit-users-manual?r=25567073

> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> > --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
> > @@ -7,10 +7,61 @@
> >
> >  /dts-v1/;
> >
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
> > +
> >  #include "r9a09g077m44.dtsi"
> >  #include "rzt2h-n2h-evk-common.dtsi"
> >
> >  / {
> >         model = "Renesas RZ/T2H EVK Board based on r9a09g077m44";
> >         compatible = "renesas,rzt2h-evk", "renesas,r9a09g077m44", "renesas,r9a09g077";
> > +
> > +       leds {
> > +               compatible = "gpio-leds";
> > +
> > +               led0 {
>
> led-0
>
Ok.
> Cfr. Documentation/devicetree/bindings/leds/leds-gpio.yaml:
>
Thanks for the pointer.

>     # The first form is preferred, but fall back to just 'led' anywhere in the
>     # node name to at least catch some child nodes.
>     "(^led-[0-9a-f]$|led)":
>
> > +                       /* SW8-9: ON, SW8-10: OFF */
> > +                       gpios = <&pinctrl RZT2H_GPIO(23, 1) GPIO_ACTIVE_LOW>;
>
> color = <LED_COLOR_ID_GREEN>;
> function = LED_FUNCTION_DEBUG;
> function-enumerator = <0>;
>
> > +               };
> > +
> > +               led1 {
> > +                       /* SW5-1: OFF, SW5-2: ON */
> > +                       gpios = <&pinctrl RZT2H_GPIO(32, 2) GPIO_ACTIVE_LOW>;
>
> color = <LED_COLOR_ID_GREEN>;
> function = LED_FUNCTION_DEBUG;
> function-enumerator = <1>;
>
> > +               };
> > +
> > +               led2 {
> > +                       gpios = <&pinctrl RZT2H_GPIO(6, 7) GPIO_ACTIVE_LOW>;
>
> color = <LED_COLOR_ID_YELLOW>;
> function = LED_FUNCTION_DEBUG;
> function-enumerator = <2>;
>
> > +               };
> > +
> > +               led3 {
> > +                       /* SW2-3: OFF */
> > +                       gpios = <&pinctrl RZT2H_GPIO(8, 5) GPIO_ACTIVE_LOW>;
>
> color = <LED_COLOR_ID_RED>;
> function = LED_FUNCTION_DEBUG;
> function-enumerator = <3>;
>
> > +               };
> > +
> > +               led4 {
> > +                       /* SW8-3: ON, SW8-4: OFF */
> > +                       gpios = <&pinctrl RZT2H_GPIO(18, 0) GPIO_ACTIVE_LOW>;
>
> Schematics say "run", so perhaps LED_FUNCTION_ACTIVITY?
>
>     color = <LED_COLOR_ID_GREEN>;
>     function = LED_FUNCTION_ACTIVITY;
>
Perhaps I'll have LED_FUNCTION_DEBUG for LEDs4-8 as currently they are
used as USER LEDs and  function-enumerator = 4/5/6/7?

Cheers,
Prabhakar

> > +               };
> > +
> > +               led5 {
> > +                       /* SW8-1: ON, SW8-2: OFF */
> > +                       gpios = <&pinctrl RZT2H_GPIO(18, 1) GPIO_ACTIVE_LOW>;
>
> Schematics say "error", so
>
>     color = <LED_COLOR_ID_RED>;
>     function = LED_FUNCTION_FAULT;
>
> > +               };
> > +
> > +               led6 {
> > +                       /* SW5-9: OFF, SW5-10: ON */
> > +                       gpios = <&pinctrl RZT2H_GPIO(22, 7) GPIO_ACTIVE_LOW>;
>
> Schematics says Ether-Cat link-activity, so LED_FUNCTION_LAN?
>
>     color = <LED_COLOR_ID_GREEN>;
>     function = LED_FUNCTION_LAN;
>     function-enumerator = <0>;
>
> > +               };
> > +
> > +               led7 {
> > +                       /* SW5-7: OFF, SW5-8: ON */
> > +                       gpios = <&pinctrl RZT2H_GPIO(23, 0) GPIO_ACTIVE_LOW>;
>
> color = <LED_COLOR_ID_GREEN>;
> function = LED_FUNCTION_LAN;
> function-enumerator = <1>;
>
> > +               };
> > +
> > +               led8 {
> > +                       /* SW7-5: OFF, SW7-6: ON */
> > +                       gpios = <&pinctrl RZT2H_GPIO(23, 5) GPIO_ACTIVE_LOW>;
>
> color = <LED_COLOR_ID_GREEN>;
> function = LED_FUNCTION_LAN;
> function-enumerator = <2>;
>
> > +               };
> > +       };
> >  };
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

Re: [PATCH 05/13] arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Add user LEDs

[Geert Uytterhoeven]

Hi Prabhakar,

On Mon, 18 Aug 2025 at 15:40, Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> On Mon, Aug 18, 2025 at 2:15 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Tue, 12 Aug 2025 at 22:03, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Add USER LED0-LED8, which are available on RZ/T2H EVK.
> >
> > According to the schematics, only the first four are user LEDs?
> >
> As per [0] user manual Table 7-4, LEDs4-8 can be used as USER LEDs or
> for Ethercat Slave. Since ESC is not enabled I haven't added any
> #ifdefs.

OK

> [0] https://www.renesas.com/en/document/mat/rzt2h-evaluation-board-kit-users-manual?r=25567073
>
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > > --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
> > > +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts

> Perhaps I'll have LED_FUNCTION_DEBUG for LEDs4-8 as currently they are
> used as USER LEDs and  function-enumerator = 4/5/6/7?

That sounds fine, thanks!

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 06/13] arm64: dts: renesas: r9a09g087m44-rzn2h-evk: Add user LEDs

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add USER LED0-LED8, which are available on RZ/N2H EVK.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../dts/renesas/r9a09g087m44-rzn2h-evk.dts    | 54 +++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
index d6ba14a26f03..f6437e82a7de 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
@@ -7,10 +7,64 @@
 
 /dts-v1/;
 
+#include <dt-bindings/gpio/gpio.h>
+
 #include "r9a09g087m44.dtsi"
 #include "rzt2h-n2h-evk-common.dtsi"
 
 / {
 	model = "Renesas RZ/N2H EVK Board based on r9a09g087m44";
 	compatible = "renesas,rzn2h-evk", "renesas,r9a09g087m44", "renesas,r9a09g087";
+
+	leds {
+		compatible = "gpio-leds";
+
+		led3 {
+			/* DSW18-7: ON, DSW18-8: OFF */
+			gpios = <&pinctrl RZN2H_GPIO(31, 6) GPIO_ACTIVE_LOW>;
+		};
+
+		led4 {
+			/* DSW18-9: ON, DSW18-10: OFF */
+			gpios = <&pinctrl RZN2H_GPIO(18, 1) GPIO_ACTIVE_LOW>;
+		};
+
+		led5 {
+			/* DSW18-1: ON, DSW18-2: OFF */
+			gpios = <&pinctrl RZN2H_GPIO(22, 7) GPIO_ACTIVE_LOW>;
+		};
+
+		led6 {
+			/* DSW18-3: ON, DSW18-4: OFF */
+			gpios = <&pinctrl RZN2H_GPIO(23, 0) GPIO_ACTIVE_LOW>;
+		};
+
+		led7 {
+			/*
+			 * DSW18-5: ON, DSW18-6: OFF
+			 * DSW19-3: ON, DSW19-4: OFF
+			 */
+			gpios = <&pinctrl RZN2H_GPIO(14, 3) GPIO_ACTIVE_LOW>;
+		};
+
+		led8 {
+			/* DSW15-8: OFF, DSW15-9: OFF, DSW15-10: ON */
+			gpios = <&pinctrl RZN2H_GPIO(14, 6) GPIO_ACTIVE_LOW>;
+		};
+
+		led9 {
+			/* DSW15-5: OFF, DSW16-6: ON */
+			gpios = <&pinctrl RZN2H_GPIO(14, 7) GPIO_ACTIVE_LOW>;
+		};
+
+		led10 {
+			/* DSW17-3: OFF, DSW17-4: ON */
+			gpios = <&pinctrl RZN2H_GPIO(2, 7) GPIO_ACTIVE_LOW>;
+		};
+
+		led11 {
+			/* DSW17-1: OFF, DSW17-2: ON */
+			gpios = <&pinctrl RZN2H_GPIO(3, 0) GPIO_ACTIVE_LOW>;
+		};
+	};
 };
-- 
2.50.1

Re: [PATCH 06/13] arm64: dts: renesas: r9a09g087m44-rzn2h-evk: Add user LEDs

[Geert Uytterhoeven]

Hi Prabhakar,

On Tue, 12 Aug 2025 at 22:03, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add USER LED0-LED8, which are available on RZ/N2H EVK.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
> +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
> @@ -7,10 +7,64 @@
>
>  /dts-v1/;
>
> +#include <dt-bindings/gpio/gpio.h>
> +
>  #include "r9a09g087m44.dtsi"
>  #include "rzt2h-n2h-evk-common.dtsi"
>
>  / {
>         model = "Renesas RZ/N2H EVK Board based on r9a09g087m44";
>         compatible = "renesas,rzn2h-evk", "renesas,r9a09g087m44", "renesas,r9a09g087";
> +
> +       leds {
> +               compatible = "gpio-leds";
> +
> +               led3 {
> +                       /* DSW18-7: ON, DSW18-8: OFF */
> +                       gpios = <&pinctrl RZN2H_GPIO(31, 6) GPIO_ACTIVE_LOW>;

Similar comments like for the RZ/T2H EVB, e.g.

    led-3 {
            /* DSW18-7: ON, DSW18-8: OFF */
            gpios = <&pinctrl RZN2H_GPIO(31, 6) GPIO_ACTIVE_LOW>;
            color = <LED_COLOR_ID_GREEN>;
            function = LED_FUNCTION_DEBUG;
            function-enumerator = <4>;
    };

> +               };
> +
> +               led4 {
> +                       /* DSW18-9: ON, DSW18-10: OFF */
> +                       gpios = <&pinctrl RZN2H_GPIO(18, 1) GPIO_ACTIVE_LOW>;
> +               };
> +
> +               led5 {
> +                       /* DSW18-1: ON, DSW18-2: OFF */
> +                       gpios = <&pinctrl RZN2H_GPIO(22, 7) GPIO_ACTIVE_LOW>;
> +               };
> +
> +               led6 {
> +                       /* DSW18-3: ON, DSW18-4: OFF */
> +                       gpios = <&pinctrl RZN2H_GPIO(23, 0) GPIO_ACTIVE_LOW>;
> +               };
> +
> +               led7 {
> +                       /*
> +                        * DSW18-5: ON, DSW18-6: OFF
> +                        * DSW19-3: ON, DSW19-4: OFF

Shouldn't that be "DSW19-3: OFF, DSW19-4: ON"?

> +                        */
> +                       gpios = <&pinctrl RZN2H_GPIO(14, 3) GPIO_ACTIVE_LOW>;
> +               };
> +
> +               led8 {
> +                       /* DSW15-8: OFF, DSW15-9: OFF, DSW15-10: ON */
> +                       gpios = <&pinctrl RZN2H_GPIO(14, 6) GPIO_ACTIVE_LOW>;
> +               };
> +
> +               led9 {
> +                       /* DSW15-5: OFF, DSW16-6: ON */

s/DSW16/DSW15/

> +                       gpios = <&pinctrl RZN2H_GPIO(14, 7) GPIO_ACTIVE_LOW>;
> +               };
> +
> +               led10 {
> +                       /* DSW17-3: OFF, DSW17-4: ON */
> +                       gpios = <&pinctrl RZN2H_GPIO(2, 7) GPIO_ACTIVE_LOW>;
> +               };
> +
> +               led11 {
> +                       /* DSW17-1: OFF, DSW17-2: ON */
> +                       gpios = <&pinctrl RZN2H_GPIO(3, 0) GPIO_ACTIVE_LOW>;
> +               };
> +       };
>  };

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 06/13] arm64: dts: renesas: r9a09g087m44-rzn2h-evk: Add user LEDs

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Mon, Aug 18, 2025 at 3:15 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, 12 Aug 2025 at 22:03, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add USER LED0-LED8, which are available on RZ/N2H EVK.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
> > @@ -7,10 +7,64 @@
> >
> >  /dts-v1/;
> >
> > +#include <dt-bindings/gpio/gpio.h>
> > +
> >  #include "r9a09g087m44.dtsi"
> >  #include "rzt2h-n2h-evk-common.dtsi"
> >
> >  / {
> >         model = "Renesas RZ/N2H EVK Board based on r9a09g087m44";
> >         compatible = "renesas,rzn2h-evk", "renesas,r9a09g087m44", "renesas,r9a09g087";
> > +
> > +       leds {
> > +               compatible = "gpio-leds";
> > +
> > +               led3 {
> > +                       /* DSW18-7: ON, DSW18-8: OFF */
> > +                       gpios = <&pinctrl RZN2H_GPIO(31, 6) GPIO_ACTIVE_LOW>;
>
> Similar comments like for the RZ/T2H EVB, e.g.
>
>     led-3 {
>             /* DSW18-7: ON, DSW18-8: OFF */
>             gpios = <&pinctrl RZN2H_GPIO(31, 6) GPIO_ACTIVE_LOW>;
>             color = <LED_COLOR_ID_GREEN>;
>             function = LED_FUNCTION_DEBUG;
>             function-enumerator = <4>;
>     };
>
Agreed.

> > +               };
> > +
> > +               led4 {
> > +                       /* DSW18-9: ON, DSW18-10: OFF */
> > +                       gpios = <&pinctrl RZN2H_GPIO(18, 1) GPIO_ACTIVE_LOW>;
> > +               };
> > +
> > +               led5 {
> > +                       /* DSW18-1: ON, DSW18-2: OFF */
> > +                       gpios = <&pinctrl RZN2H_GPIO(22, 7) GPIO_ACTIVE_LOW>;
> > +               };
> > +
> > +               led6 {
> > +                       /* DSW18-3: ON, DSW18-4: OFF */
> > +                       gpios = <&pinctrl RZN2H_GPIO(23, 0) GPIO_ACTIVE_LOW>;
> > +               };
> > +
> > +               led7 {
> > +                       /*
> > +                        * DSW18-5: ON, DSW18-6: OFF
> > +                        * DSW19-3: ON, DSW19-4: OFF
>
> Shouldn't that be "DSW19-3: OFF, DSW19-4: ON"?
>
Agreed.

> > +                        */
> > +                       gpios = <&pinctrl RZN2H_GPIO(14, 3) GPIO_ACTIVE_LOW>;
> > +               };
> > +
> > +               led8 {
> > +                       /* DSW15-8: OFF, DSW15-9: OFF, DSW15-10: ON */
> > +                       gpios = <&pinctrl RZN2H_GPIO(14, 6) GPIO_ACTIVE_LOW>;
> > +               };
> > +
> > +               led9 {
> > +                       /* DSW15-5: OFF, DSW16-6: ON */
>
> s/DSW16/DSW15/
>
Agreed, (Ive also notified to update the user manual).


Cheers,
Prabhakar

[PATCH 07/13] arm64: dts: renesas: rzt2h-evk-common: Add pinctrl for SCI0 node

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add pinctrl for SCI0 node.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../dts/renesas/rzt2h-n2h-evk-common.dtsi     | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
index 5f17996bcd6b..868abfdfd342 100644
--- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
@@ -5,6 +5,8 @@
  * Copyright (C) 2025 Renesas Electronics Corp.
  */
 
+#include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
+
 / {
 	aliases {
 		serial0 = &sci0;
@@ -19,6 +21,23 @@ &extal_clk {
 	clock-frequency = <25000000>;
 };
 
+&pinctrl {
+	/*
+	 * SCI0 Pin Configuration:
+	 * ------------------------
+	 * Signal     | Pin     | RZ/T2H (SW4) | RZ/N2H (DSW9)
+	 * -----------|---------|--------------|---------------
+	 * SCI0_RXD   | P27_4   | 5: ON, 6: OFF| 1: ON, 2: OFF
+	 * SCI0_TXD   | P27_5   | 7: ON, 8: OFF| 3: ON, 4: OFF
+	 */
+	sci0_pins: sci0-pins {
+		pinmux = <RZT2H_PORT_PINMUX(27, 4, 0x14)>,
+			 <RZT2H_PORT_PINMUX(27, 5, 0x14)>;
+	};
+};
+
 &sci0 {
+	pinctrl-0 = <&sci0_pins>;
+	pinctrl-names = "default";
 	status = "okay";
 };
-- 
2.50.1

Re: [PATCH 07/13] arm64: dts: renesas: rzt2h-evk-common: Add pinctrl for SCI0 node

[Geert Uytterhoeven]

Hi Prabhakar,

On Tue, 12 Aug 2025 at 22:03, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add pinctrl for SCI0 node.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> @@ -5,6 +5,8 @@
>   * Copyright (C) 2025 Renesas Electronics Corp.
>   */
>
> +#include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>

This relies on RZT2H_PORT_PINMUX() == RZN2H_PORT_PINMUX.
So perhaps it is best to get rid of the latter, and always use the former?

> +
>  / {
>         aliases {
>                 serial0 = &sci0;

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.18.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 07/13] arm64: dts: renesas: rzt2h-evk-common: Add pinctrl for SCI0 node

[Geert Uytterhoeven]

On Mon, 18 Aug 2025 at 15:35, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Tue, 12 Aug 2025 at 22:03, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add pinctrl for SCI0 node.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> > @@ -5,6 +5,8 @@
> >   * Copyright (C) 2025 Renesas Electronics Corp.
> >   */
> >
> > +#include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
>
> This relies on RZT2H_PORT_PINMUX() == RZN2H_PORT_PINMUX.
> So perhaps it is best to get rid of the latter, and always use the former?
>
> > +
> >  / {
> >         aliases {
> >                 serial0 = &sci0;
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> i.e. will queue in renesas-devel for v6.18.

Oops, this has a hard dependency on "[PATCH 04/13]", so I postpone
queuing.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 07/13] arm64: dts: renesas: rzt2h-evk-common: Add pinctrl for SCI0 node

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Mon, Aug 18, 2025 at 2:35 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, 12 Aug 2025 at 22:03, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add pinctrl for SCI0 node.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> > @@ -5,6 +5,8 @@
> >   * Copyright (C) 2025 Renesas Electronics Corp.
> >   */
> >
> > +#include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
>
> This relies on RZT2H_PORT_PINMUX() == RZN2H_PORT_PINMUX.
> So perhaps it is best to get rid of the latter, and always use the former?
>
Ok makes sense, I'll drop the RZN2H_* macro definitions from patch
04/13 and use RZT2H_* macros for RZ/N2H.

Cheers,
Prabhakar

> > +
> >  / {
> >         aliases {
> >                 serial0 = &sci0;
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> i.e. will queue in renesas-devel for v6.18.
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

[PATCH 08/13] arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Enable I2C0 and I2C1 support

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Enable I2C0 and I2C1 on the RZ/T2H evaluation board.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../dts/renesas/r9a09g077m44-rzt2h-evk.dts    | 34 +++++++++++++++++++
 .../dts/renesas/rzt2h-n2h-evk-common.dtsi     |  2 ++
 2 files changed, 36 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
index a0cf01978f15..36e3b630727a 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
@@ -65,3 +65,37 @@ led8 {
 		};
 	};
 };
+
+&i2c0 {
+	pinctrl-0 = <&i2c0_pins>;
+	pinctrl-names = "default";
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&i2c1 {
+	pinctrl-0 = <&i2c1_pins>;
+	pinctrl-names = "default";
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&pinctrl {
+	/*
+	 * I2C0 Pin Configuration:
+	 * ------------------------
+	 * Signal | Pin     | SW6
+	 * -------|---------|--------------
+	 * SCL    | P23_3   | 7: ON, 8: OFF
+	 * SDA    | P23_4   | 9: ON, 10: OFF
+	 */
+	i2c0_pins: i2c0-pins {
+		pinmux = <RZT2H_PORT_PINMUX(23, 3, 0x17)>,
+			 <RZT2H_PORT_PINMUX(23, 4, 0x17)>;
+	};
+
+	i2c1_pins: i2c1-pins {
+		pinmux = <RZT2H_PORT_PINMUX(5, 0, 0x17)>, /* SDA */
+			 <RZT2H_PORT_PINMUX(4, 7, 0x17)>; /* SCL */
+	};
+};
diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
index 868abfdfd342..127e96395f8e 100644
--- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
@@ -9,6 +9,8 @@
 
 / {
 	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
 		serial0 = &sci0;
 	};
 
-- 
2.50.1

Re: [PATCH 08/13] arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Enable I2C0 and I2C1 support

[Geert Uytterhoeven]

On Tue, 12 Aug 2025 at 22:03, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Enable I2C0 and I2C1 on the RZ/T2H evaluation board.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.18.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 09/13] arm64: dts: renesas: r9a09g087m44-rzt2h-evk: Enable I2C0 and I2C1 support

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Enable I2C0 and I2C1 on the RZ/N2H evaluation board.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../dts/renesas/r9a09g087m44-rzn2h-evk.dts    | 56 +++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
index f6437e82a7de..e41b687e5497 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
@@ -12,6 +12,14 @@
 #include "r9a09g087m44.dtsi"
 #include "rzt2h-n2h-evk-common.dtsi"
 
+/*
+ * I2C0 and LED8/9 share the same pins use the below
+ * macro to choose (and set approopriate DIP switches).
+ */
+#define I2C0	1
+#define LED8	(!I2C0)
+#define LED9	(!I2C0)
+
 / {
 	model = "Renesas RZ/N2H EVK Board based on r9a09g087m44";
 	compatible = "renesas,rzn2h-evk", "renesas,r9a09g087m44", "renesas,r9a09g087";
@@ -47,15 +55,19 @@ led7 {
 			gpios = <&pinctrl RZN2H_GPIO(14, 3) GPIO_ACTIVE_LOW>;
 		};
 
+#if LED8
 		led8 {
 			/* DSW15-8: OFF, DSW15-9: OFF, DSW15-10: ON */
 			gpios = <&pinctrl RZN2H_GPIO(14, 6) GPIO_ACTIVE_LOW>;
 		};
+#endif
 
+#if LED9
 		led9 {
 			/* DSW15-5: OFF, DSW16-6: ON */
 			gpios = <&pinctrl RZN2H_GPIO(14, 7) GPIO_ACTIVE_LOW>;
 		};
+#endif
 
 		led10 {
 			/* DSW17-3: OFF, DSW17-4: ON */
@@ -68,3 +80,47 @@ led11 {
 		};
 	};
 };
+
+#if I2C0
+&i2c0 {
+	pinctrl-0 = <&i2c0_pins>;
+	pinctrl-names = "default";
+	clock-frequency = <400000>;
+	status = "okay";
+};
+#endif
+
+&i2c1 {
+	pinctrl-0 = <&i2c1_pins>;
+	pinctrl-names = "default";
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&pinctrl {
+	/*
+	 * I2C0 Pin Configuration:
+	 * ------------------------
+	 * Signal | Pin     | DSW15
+	 * -------|---------|--------------
+	 * SCL    | P14_6   | 8: OFF, 9: ON, 10: OFF
+	 * SDA    | P14_7   | 5: ON, 6: OFF
+	 */
+	i2c0_pins: i2c0-pins {
+		pinmux = <RZN2H_PORT_PINMUX(14, 6, 0x17)>,
+			 <RZN2H_PORT_PINMUX(14, 7, 0x17)>;
+	};
+
+	/*
+	 * I2C1 Pin Configuration:
+	 * ------------------------
+	 * Signal | Pin     | DSW7
+	 * -------|---------|--------------
+	 * SCL    | P03_3   | 3: ON, 4: OFF
+	 * SDA    | P03_4   | 1: ON, 2: OFF
+	 */
+	i2c1_pins: i2c1-pins {
+		pinmux = <RZN2H_PORT_PINMUX(3, 3, 0x17)>,
+			 <RZN2H_PORT_PINMUX(3, 4, 0x17)>;
+	};
+};
-- 
2.50.1

Re: [PATCH 09/13] arm64: dts: renesas: r9a09g087m44-rzt2h-evk: Enable I2C0 and I2C1 support

[Geert Uytterhoeven]

Hi Prabhakar,

On Tue, 12 Aug 2025 at 22:03, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Enable I2C0 and I2C1 on the RZ/N2H evaluation board.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
> +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts

> +       /*
> +        * I2C1 Pin Configuration:
> +        * ------------------------
> +        * Signal | Pin     | DSW7
> +        * -------|---------|--------------
> +        * SCL    | P03_3   | 3: ON, 4: OFF

1: ON, 2: OFF

> +        * SDA    | P03_4   | 1: ON, 2: OFF

3: ON, 4: OFF

> +        */
> +       i2c1_pins: i2c1-pins {
> +               pinmux = <RZN2H_PORT_PINMUX(3, 3, 0x17)>,
> +                        <RZN2H_PORT_PINMUX(3, 4, 0x17)>;
> +       };
> +};

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 09/13] arm64: dts: renesas: r9a09g087m44-rzt2h-evk: Enable I2C0 and I2C1 support

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Mon, Aug 18, 2025 at 3:00 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, 12 Aug 2025 at 22:03, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Enable I2C0 and I2C1 on the RZ/N2H evaluation board.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
>
> > +       /*
> > +        * I2C1 Pin Configuration:
> > +        * ------------------------
> > +        * Signal | Pin     | DSW7
> > +        * -------|---------|--------------
> > +        * SCL    | P03_3   | 3: ON, 4: OFF
>
> 1: ON, 2: OFF
>
> > +        * SDA    | P03_4   | 1: ON, 2: OFF
>
> 3: ON, 4: OFF
>
Agreed, I will fix it in v2.

Cheers,
Prabhakar

> > +        */
> > +       i2c1_pins: i2c1-pins {
> > +               pinmux = <RZN2H_PORT_PINMUX(3, 3, 0x17)>,
> > +                        <RZN2H_PORT_PINMUX(3, 4, 0x17)>;
> > +       };
> > +};
>
> The rest LGTM.
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds
>

[PATCH 10/13] arm64: dts: renesas: rzt2h-evk-common: Enable EEPROM on I2C0

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Enable support for the R1EX24016 EEPROM connected to I2C0 on the
Renesas RZ/T2H and RZ/N2H Evaluation Kits.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
index 127e96395f8e..1a3d28054bf7 100644
--- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
@@ -23,6 +23,14 @@ &extal_clk {
 	clock-frequency = <25000000>;
 };
 
+&i2c0 {
+	eeprom: eeprom@50 {
+		compatible = "renesas,r1ex24016", "atmel,24c16";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+};
+
 &pinctrl {
 	/*
 	 * SCI0 Pin Configuration:
-- 
2.50.1

Re: [PATCH 10/13] arm64: dts: renesas: rzt2h-evk-common: Enable EEPROM on I2C0

[Geert Uytterhoeven]

On Tue, 12 Aug 2025 at 22:03, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Enable support for the R1EX24016 EEPROM connected to I2C0 on the
> Renesas RZ/T2H and RZ/N2H Evaluation Kits.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 11/13] arm64: dts: renesas: rzt2h/rzn2h: Enable eMMC

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Enable eMMC on RZ/T2H and RZ/N2H EVKs. As SDHI0 can be connected to
either eMMC0/SD0 `SD0_EMMC` macro is added.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../dts/renesas/r9a09g077m44-rzt2h-evk.dts    |  9 +++
 .../dts/renesas/r9a09g087m44-rzn2h-evk.dts    |  9 +++
 .../dts/renesas/rzt2h-n2h-evk-common.dtsi     | 62 +++++++++++++++++++
 3 files changed, 80 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
index 36e3b630727a..05945a8a3228 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
@@ -11,6 +11,15 @@
 #include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
 
 #include "r9a09g077m44.dtsi"
+
+/*
+ * SD0 can be connected to either eMMC (IC49) or SD card slot CN31
+ * Lets by default enable the eMMC, note we need the below SW settings
+ * for eMMC.
+ * SW2[1] = ON; SW2[2] = ON
+ */
+#define SD0_EMMC	1
+
 #include "rzt2h-n2h-evk-common.dtsi"
 
 / {
diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
index e41b687e5497..89baa601a179 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
@@ -10,6 +10,15 @@
 #include <dt-bindings/gpio/gpio.h>
 
 #include "r9a09g087m44.dtsi"
+
+/*
+ * SD0 can be connected to either eMMC (U33) or SD card slot CN21
+ * Lets by default enable the eMMC, note we need the below SW settings
+ * for eMMC.
+ * DSW5[1] = ON; DSW5[2] = ON
+ */
+#define SD0_EMMC       1
+
 #include "rzt2h-n2h-evk-common.dtsi"
 
 /*
diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
index 1a3d28054bf7..7fa49de2a243 100644
--- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
@@ -11,12 +11,31 @@ / {
 	aliases {
 		i2c0 = &i2c0;
 		i2c1 = &i2c1;
+		mmc0 = &sdhi0;
 		serial0 = &sci0;
 	};
 
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
+
+	reg_1p8v: regulator-1p8v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
 };
 
 &extal_clk {
@@ -44,6 +63,34 @@ sci0_pins: sci0-pins {
 		pinmux = <RZT2H_PORT_PINMUX(27, 4, 0x14)>,
 			 <RZT2H_PORT_PINMUX(27, 5, 0x14)>;
 	};
+
+#if SD0_EMMC
+	sdhi0-emmc-iovs-hog {
+		gpio-hog;
+		gpios = <RZT2H_GPIO(2, 6) GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "SD0_IOVS";
+	};
+#endif
+
+	sdhi0_emmc_pins: sd0-emmc-group {
+		sd0-emmc-data-pins {
+			pinmux = <RZT2H_PORT_PINMUX(12, 2, 0x29)>, /* SD0_DATA0 */
+				 <RZT2H_PORT_PINMUX(12, 3, 0x29)>, /* SD0_DATA1 */
+				 <RZT2H_PORT_PINMUX(12, 4, 0x29)>, /* SD0_DATA2 */
+				 <RZT2H_PORT_PINMUX(12, 5, 0x29)>, /* SD0_DATA3 */
+				 <RZT2H_PORT_PINMUX(12, 6, 0x29)>, /* SD0_DATA4 */
+				 <RZT2H_PORT_PINMUX(12, 7, 0x29)>, /* SD0_DATA5 */
+				 <RZT2H_PORT_PINMUX(13, 0, 0x29)>, /* SD0_DATA6 */
+				 <RZT2H_PORT_PINMUX(13, 1, 0x29)>; /* SD0_DATA7 */
+		};
+
+		sd0-emmc-ctrl-pins {
+			pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
+				 <RZT2H_PORT_PINMUX(12, 1, 0x29)>, /* SD0_CMD */
+				 <RZT2H_PORT_PINMUX(13, 2, 0x29)>; /* SD0_RST# */
+		};
+	};
 };
 
 &sci0 {
@@ -51,3 +98,18 @@ &sci0 {
 	pinctrl-names = "default";
 	status = "okay";
 };
+
+#if SD0_EMMC
+&sdhi0 {
+	pinctrl-0 = <&sdhi0_emmc_pins>;
+	pinctrl-1 = <&sdhi0_emmc_pins>;
+	pinctrl-names = "default", "state_uhs";
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_1p8v>;
+	bus-width = <8>;
+	non-removable;
+	mmc-hs200-1_8v;
+	fixed-emmc-driver-type = <1>;
+	status = "okay";
+};
+#endif
-- 
2.50.1

Re: [PATCH 11/13] arm64: dts: renesas: rzt2h/rzn2h: Enable eMMC

[Geert Uytterhoeven]

Hi Prabhakar,

On Tue, 12 Aug 2025 at 22:03, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Enable eMMC on RZ/T2H and RZ/N2H EVKs. As SDHI0 can be connected to
> either eMMC0/SD0 `SD0_EMMC` macro is added.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
> +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
> @@ -10,6 +10,15 @@
>  #include <dt-bindings/gpio/gpio.h>
>
>  #include "r9a09g087m44.dtsi"
> +
> +/*
> + * SD0 can be connected to either eMMC (U33) or SD card slot CN21
> + * Lets by default enable the eMMC, note we need the below SW settings
> + * for eMMC.
> + * DSW5[1] = ON; DSW5[2] = ON
> + */

Both SD0 and eMMC also need DSW17[5] = OFF; DSW17[6] = ON.

> +#define SD0_EMMC       1
> +
>  #include "rzt2h-n2h-evk-common.dtsi"
>
>  /*

> --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi

> @@ -44,6 +63,34 @@ sci0_pins: sci0-pins {
>                 pinmux = <RZT2H_PORT_PINMUX(27, 4, 0x14)>,
>                          <RZT2H_PORT_PINMUX(27, 5, 0x14)>;
>         };
> +
> +#if SD0_EMMC
> +       sdhi0-emmc-iovs-hog {
> +               gpio-hog;
> +               gpios = <RZT2H_GPIO(2, 6) GPIO_ACTIVE_HIGH>;
> +               output-high;
> +               line-name = "SD0_IOVS";
> +       };
> +#endif
> +
> +       sdhi0_emmc_pins: sd0-emmc-group {
> +               sd0-emmc-data-pins {

No need for repeated sd0-emmc-prefixes in the subnodes.


> +                       pinmux = <RZT2H_PORT_PINMUX(12, 2, 0x29)>, /* SD0_DATA0 */
> +                                <RZT2H_PORT_PINMUX(12, 3, 0x29)>, /* SD0_DATA1 */
> +                                <RZT2H_PORT_PINMUX(12, 4, 0x29)>, /* SD0_DATA2 */
> +                                <RZT2H_PORT_PINMUX(12, 5, 0x29)>, /* SD0_DATA3 */
> +                                <RZT2H_PORT_PINMUX(12, 6, 0x29)>, /* SD0_DATA4 */
> +                                <RZT2H_PORT_PINMUX(12, 7, 0x29)>, /* SD0_DATA5 */
> +                                <RZT2H_PORT_PINMUX(13, 0, 0x29)>, /* SD0_DATA6 */
> +                                <RZT2H_PORT_PINMUX(13, 1, 0x29)>; /* SD0_DATA7 */
> +               };
> +
> +               sd0-emmc-ctrl-pins {
> +                       pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
> +                                <RZT2H_PORT_PINMUX(12, 1, 0x29)>, /* SD0_CMD */
> +                                <RZT2H_PORT_PINMUX(13, 2, 0x29)>; /* SD0_RST# */
> +               };
> +       };
>  };

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 11/13] arm64: dts: renesas: rzt2h/rzn2h: Enable eMMC

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Mon, Aug 18, 2025 at 5:02 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, 12 Aug 2025 at 22:03, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Enable eMMC on RZ/T2H and RZ/N2H EVKs. As SDHI0 can be connected to
> > either eMMC0/SD0 `SD0_EMMC` macro is added.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
> > @@ -10,6 +10,15 @@
> >  #include <dt-bindings/gpio/gpio.h>
> >
> >  #include "r9a09g087m44.dtsi"
> > +
> > +/*
> > + * SD0 can be connected to either eMMC (U33) or SD card slot CN21
> > + * Lets by default enable the eMMC, note we need the below SW settings
> > + * for eMMC.
> > + * DSW5[1] = ON; DSW5[2] = ON
> > + */
>
> Both SD0 and eMMC also need DSW17[5] = OFF; DSW17[6] = ON.
>
Agreed.

> > +#define SD0_EMMC       1
> > +
> >  #include "rzt2h-n2h-evk-common.dtsi"
> >
> >  /*
>
> > --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
>
> > @@ -44,6 +63,34 @@ sci0_pins: sci0-pins {
> >                 pinmux = <RZT2H_PORT_PINMUX(27, 4, 0x14)>,
> >                          <RZT2H_PORT_PINMUX(27, 5, 0x14)>;
> >         };
> > +
> > +#if SD0_EMMC
> > +       sdhi0-emmc-iovs-hog {
> > +               gpio-hog;
> > +               gpios = <RZT2H_GPIO(2, 6) GPIO_ACTIVE_HIGH>;
> > +               output-high;
> > +               line-name = "SD0_IOVS";
> > +       };
> > +#endif
> > +
> > +       sdhi0_emmc_pins: sd0-emmc-group {
> > +               sd0-emmc-data-pins {
>
> No need for repeated sd0-emmc-prefixes in the subnodes.
>
>
Ok, I will get rid of them.

Cheers,
Prabhakar

> > +                       pinmux = <RZT2H_PORT_PINMUX(12, 2, 0x29)>, /* SD0_DATA0 */
> > +                                <RZT2H_PORT_PINMUX(12, 3, 0x29)>, /* SD0_DATA1 */
> > +                                <RZT2H_PORT_PINMUX(12, 4, 0x29)>, /* SD0_DATA2 */
> > +                                <RZT2H_PORT_PINMUX(12, 5, 0x29)>, /* SD0_DATA3 */
> > +                                <RZT2H_PORT_PINMUX(12, 6, 0x29)>, /* SD0_DATA4 */
> > +                                <RZT2H_PORT_PINMUX(12, 7, 0x29)>, /* SD0_DATA5 */
> > +                                <RZT2H_PORT_PINMUX(13, 0, 0x29)>, /* SD0_DATA6 */
> > +                                <RZT2H_PORT_PINMUX(13, 1, 0x29)>; /* SD0_DATA7 */
> > +               };
> > +
> > +               sd0-emmc-ctrl-pins {
> > +                       pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
> > +                                <RZT2H_PORT_PINMUX(12, 1, 0x29)>, /* SD0_CMD */
> > +                                <RZT2H_PORT_PINMUX(13, 2, 0x29)>; /* SD0_RST# */
> > +               };
> > +       };
> >  };
>
> The rest LGTM.
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

[PATCH 12/13] arm64: dts: renesas: rzt2h/rzn2h: Enable MicroSD card slot

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Enable MicroSD card slot which is connected to SDHI1 on the RZ/T2H and
RZ/N2H EVKs.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../dts/renesas/r9a09g077m44-rzt2h-evk.dts    |  9 ++++
 .../dts/renesas/r9a09g087m44-rzn2h-evk.dts    |  6 +++
 .../dts/renesas/rzt2h-n2h-evk-common.dtsi     | 50 +++++++++++++++++++
 3 files changed, 65 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
index 05945a8a3228..1841700b264f 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
@@ -20,6 +20,13 @@
  */
 #define SD0_EMMC	1
 
+/*
+ * P17_4 = SD1_CD; SW2[3] = ON
+ * P08_5 = SD1_PWEN; SW2[3] = ON
+ * P08_6 = IOVS SW2[3] = ON; SW5[3] = OFF; SW5[4] = ON
+ */
+#define SD1_MICRO_SD	1
+
 #include "rzt2h-n2h-evk-common.dtsi"
 
 / {
@@ -43,10 +50,12 @@ led2 {
 			gpios = <&pinctrl RZT2H_GPIO(6, 7) GPIO_ACTIVE_LOW>;
 		};
 
+#if (!SD1_MICRO_SD)
 		led3 {
 			/* SW2-3: OFF */
 			gpios = <&pinctrl RZT2H_GPIO(8, 5) GPIO_ACTIVE_LOW>;
 		};
+#endif
 
 		led4 {
 			/* SW8-3: ON, SW8-4: OFF */
diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
index 89baa601a179..1b13995e5020 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
@@ -19,6 +19,12 @@
  */
 #define SD0_EMMC       1
 
+/*
+ * P17_4 = SD1_CD; DSW5[3] = ON; DSW19[1] = OFF; DSW19[2] = ON
+ * P08_6 = IOVSp DSW5[3] = ON
+ */
+#define SD1_MICRO_SD	1
+
 #include "rzt2h-n2h-evk-common.dtsi"
 
 /*
diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
index 7fa49de2a243..304a0c8764ca 100644
--- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
@@ -36,6 +36,18 @@ reg_3p3v: regulator-3p3v {
 		regulator-boot-on;
 		regulator-always-on;
 	};
+
+#if SD1_MICRO_SD
+	vccq_sdhi1: regulator-vccq-sdhi1 {
+		compatible = "regulator-gpio";
+		regulator-name = "SDHI1 VccQ";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		gpios = <&pinctrl RZT2H_GPIO(8, 6) GPIO_ACTIVE_HIGH>;
+		gpios-states = <0>;
+		states = <3300000 0>, <1800000 1>;
+	};
+#endif
 };
 
 &extal_clk {
@@ -91,6 +103,30 @@ sd0-emmc-ctrl-pins {
 				 <RZT2H_PORT_PINMUX(13, 2, 0x29)>; /* SD0_RST# */
 		};
 	};
+
+#if SD1_MICRO_SD
+	sdhi1-pwen-hog {
+		gpio-hog;
+		gpios = <RZT2H_GPIO(8, 5) GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "SD1_PWEN";
+	};
+#endif
+
+	sdhi1_pins: sd1-group {
+		sd1-data-pins {
+			pinmux = <RZT2H_PORT_PINMUX(16, 7, 0x29)>, /* SD1_DATA0 */
+				 <RZT2H_PORT_PINMUX(17, 0, 0x29)>, /* SD1_DATA1 */
+				 <RZT2H_PORT_PINMUX(17, 1, 0x29)>, /* SD1_DATA2 */
+				 <RZT2H_PORT_PINMUX(17, 2, 0x29)>; /* SD1_DATA3 */
+		};
+
+		sd1-ctrl-pins {
+			pinmux = <RZT2H_PORT_PINMUX(16, 5, 0x29)>, /* SD1_CLK */
+				 <RZT2H_PORT_PINMUX(16, 6, 0x29)>, /* SD1_CMD */
+				 <RZT2H_PORT_PINMUX(17, 4, 0x29)>; /* SD1_CD */
+		};
+	};
 };
 
 &sci0 {
@@ -113,3 +149,17 @@ &sdhi0 {
 	status = "okay";
 };
 #endif
+
+#if SD1_MICRO_SD
+&sdhi1 {
+	pinctrl-0 = <&sdhi1_pins>;
+	pinctrl-1 = <&sdhi1_pins>;
+	pinctrl-names = "default", "state_uhs";
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&vccq_sdhi1>;
+	bus-width = <4>;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+#endif
-- 
2.50.1

Re: [PATCH 12/13] arm64: dts: renesas: rzt2h/rzn2h: Enable MicroSD card slot

[Geert Uytterhoeven]

Hi Prabhakar,

On Tue, 12 Aug 2025 at 22:04, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Enable MicroSD card slot which is connected to SDHI1 on the RZ/T2H and
> RZ/N2H EVKs.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi

No mmc1 alias?

> @@ -91,6 +103,30 @@ sd0-emmc-ctrl-pins {
>                                  <RZT2H_PORT_PINMUX(13, 2, 0x29)>; /* SD0_RST# */
>                 };
>         };
> +
> +#if SD1_MICRO_SD
> +       sdhi1-pwen-hog {
> +               gpio-hog;
> +               gpios = <RZT2H_GPIO(8, 5) GPIO_ACTIVE_HIGH>;
> +               output-high;
> +               line-name = "SD1_PWEN";
> +       };
> +#endif
> +
> +       sdhi1_pins: sd1-group {
> +               sd1-data-pins {

No need for repeated sd1-prefixes in the subnodes.


> +                       pinmux = <RZT2H_PORT_PINMUX(16, 7, 0x29)>, /* SD1_DATA0 */
> +                                <RZT2H_PORT_PINMUX(17, 0, 0x29)>, /* SD1_DATA1 */
> +                                <RZT2H_PORT_PINMUX(17, 1, 0x29)>, /* SD1_DATA2 */
> +                                <RZT2H_PORT_PINMUX(17, 2, 0x29)>; /* SD1_DATA3 */
> +               };
> +
> +               sd1-ctrl-pins {
> +                       pinmux = <RZT2H_PORT_PINMUX(16, 5, 0x29)>, /* SD1_CLK */
> +                                <RZT2H_PORT_PINMUX(16, 6, 0x29)>, /* SD1_CMD */
> +                                <RZT2H_PORT_PINMUX(17, 4, 0x29)>; /* SD1_CD */
> +               };
> +       };
>  };
>
>  &sci0 {

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 12/13] arm64: dts: renesas: rzt2h/rzn2h: Enable MicroSD card slot

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Mon, Aug 18, 2025 at 5:03 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, 12 Aug 2025 at 22:04, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Enable MicroSD card slot which is connected to SDHI1 on the RZ/T2H and
> > RZ/N2H EVKs.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
>
> No mmc1 alias?
>
Ouch missed it.

> > @@ -91,6 +103,30 @@ sd0-emmc-ctrl-pins {
> >                                  <RZT2H_PORT_PINMUX(13, 2, 0x29)>; /* SD0_RST# */
> >                 };
> >         };
> > +
> > +#if SD1_MICRO_SD
> > +       sdhi1-pwen-hog {
> > +               gpio-hog;
> > +               gpios = <RZT2H_GPIO(8, 5) GPIO_ACTIVE_HIGH>;
> > +               output-high;
> > +               line-name = "SD1_PWEN";
> > +       };
> > +#endif
> > +
> > +       sdhi1_pins: sd1-group {
> > +               sd1-data-pins {
>
> No need for repeated sd1-prefixes in the subnodes.
>
Ok, I will drop them in v2.

Cheers,
Prabhakar

>
> > +                       pinmux = <RZT2H_PORT_PINMUX(16, 7, 0x29)>, /* SD1_DATA0 */
> > +                                <RZT2H_PORT_PINMUX(17, 0, 0x29)>, /* SD1_DATA1 */
> > +                                <RZT2H_PORT_PINMUX(17, 1, 0x29)>, /* SD1_DATA2 */
> > +                                <RZT2H_PORT_PINMUX(17, 2, 0x29)>; /* SD1_DATA3 */
> > +               };
> > +
> > +               sd1-ctrl-pins {
> > +                       pinmux = <RZT2H_PORT_PINMUX(16, 5, 0x29)>, /* SD1_CLK */
> > +                                <RZT2H_PORT_PINMUX(16, 6, 0x29)>, /* SD1_CMD */
> > +                                <RZT2H_PORT_PINMUX(17, 4, 0x29)>; /* SD1_CD */
> > +               };
> > +       };
> >  };
> >
> >  &sci0 {
>
> The rest LGTM.
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

[PATCH 13/13] arm64: dts: renesas: rzt2h/rzn2h: Enable SD card slot

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Enable SD card slot which is connected to SDHI0 on the RZ/T2H and
RZ/N2H EVKs.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../dts/renesas/r9a09g077m44-rzt2h-evk.dts    |  5 ++
 .../dts/renesas/r9a09g087m44-rzn2h-evk.dts    |  9 +++
 .../dts/renesas/rzt2h-n2h-evk-common.dtsi     | 55 +++++++++++++++++++
 3 files changed, 69 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
index 1841700b264f..309080767ff2 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
@@ -17,8 +17,13 @@
  * Lets by default enable the eMMC, note we need the below SW settings
  * for eMMC.
  * SW2[1] = ON; SW2[2] = ON
+ *
+ * To enable SD card and disable eMMC on SDHI0 disable the below macro
+ * and set the below switch setting:
+ * SW2[1] = OFF; SW2[2] = ON
  */
 #define SD0_EMMC	1
+#define SD0_SD		(!SD0_EMMC)
 
 /*
  * P17_4 = SD1_CD; SW2[3] = ON
diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
index 1b13995e5020..33d9b783ff11 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
@@ -16,8 +16,17 @@
  * Lets by default enable the eMMC, note we need the below SW settings
  * for eMMC.
  * DSW5[1] = ON; DSW5[2] = ON
+ *
+ * To enable SD card and disable eMMC on SDHI0 disable the below macro
+ * and set the below switch setting:
+ * DSW5[1] = OFF; DSW5[2] = ON
+ * DSW15[3] = OFF; DSW15[4] = ON
+ * DSW15[1] = OFF; DSW15[2] = ON
+ * DSW17[7] = OFF; DSW17[8] = ON
+ * DSW17[5] = OFF; DSW17[6] = ON
  */
 #define SD0_EMMC       1
+#define SD0_SD		(!SD0_EMMC)
 
 /*
  * P17_4 = SD1_CD; DSW5[3] = ON; DSW19[1] = OFF; DSW19[2] = ON
diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
index 304a0c8764ca..f87dde8716d8 100644
--- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
@@ -37,6 +37,18 @@ reg_3p3v: regulator-3p3v {
 		regulator-always-on;
 	};
 
+#if SD0_SD
+	vqmmc_sdhi0: regulator-vqmmc-sdhi0 {
+		compatible = "regulator-gpio";
+		regulator-name = "SDHI0 VqmmC";
+		gpios = <&pinctrl RZT2H_GPIO(2, 6) GPIO_ACTIVE_HIGH>;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		gpios-states = <0>;
+		states = <3300000 0>, <1800000 1>;
+	};
+#endif
+
 #if SD1_MICRO_SD
 	vccq_sdhi1: regulator-vccq-sdhi1 {
 		compatible = "regulator-gpio";
@@ -104,6 +116,35 @@ sd0-emmc-ctrl-pins {
 		};
 	};
 
+#if SD0_SD
+	sdhi0-pwen-hog {
+		gpio-hog;
+		gpios = <RZT2H_GPIO(2, 5) GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "SD0_PWEN";
+	};
+#endif
+
+	sdhi0_sd_pins: sd0-sd-group {
+		sd0-sd-data-pins {
+			pinmux = <RZT2H_PORT_PINMUX(12, 2, 0x29)>, /* SD0_DATA0 */
+				 <RZT2H_PORT_PINMUX(12, 3, 0x29)>, /* SD0_DATA1 */
+				 <RZT2H_PORT_PINMUX(12, 4, 0x29)>, /* SD0_DATA2 */
+				 <RZT2H_PORT_PINMUX(12, 5, 0x29)>, /* SD0_DATA3 */
+				 <RZT2H_PORT_PINMUX(12, 6, 0x29)>, /* SD0_DATA4 */
+				 <RZT2H_PORT_PINMUX(12, 7, 0x29)>, /* SD0_DATA5 */
+				 <RZT2H_PORT_PINMUX(13, 0, 0x29)>, /* SD0_DATA6 */
+				 <RZT2H_PORT_PINMUX(13, 1, 0x29)>; /* SD0_DATA7 */
+		};
+
+		sd0-sd-ctrl-pins {
+			pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
+				 <RZT2H_PORT_PINMUX(12, 1, 0x29)>, /* SD0_CMD */
+				 <RZT2H_PORT_PINMUX(22, 5, 0x29)>, /* SD0_CD */
+				 <RZT2H_PORT_PINMUX(22, 6, 0x29)>; /* SD0_WP */
+		};
+	};
+
 #if SD1_MICRO_SD
 	sdhi1-pwen-hog {
 		gpio-hog;
@@ -150,6 +191,20 @@ &sdhi0 {
 };
 #endif
 
+#if SD0_SD
+&sdhi0 {
+	pinctrl-0 = <&sdhi0_sd_pins>;
+	pinctrl-1 = <&sdhi0_sd_pins>;
+	pinctrl-names = "default", "state_uhs";
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&vqmmc_sdhi0>;
+	bus-width = <4>;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+#endif
+
 #if SD1_MICRO_SD
 &sdhi1 {
 	pinctrl-0 = <&sdhi1_pins>;
-- 
2.50.1

Re: [PATCH 13/13] arm64: dts: renesas: rzt2h/rzn2h: Enable SD card slot

[Geert Uytterhoeven]

Hi Prabhakar,

On Tue, 12 Aug 2025 at 22:04, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Enable SD card slot which is connected to SDHI0 on the RZ/T2H and
> RZ/N2H EVKs.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi

> @@ -104,6 +116,35 @@ sd0-emmc-ctrl-pins {
>                 };
>         };
>
> +#if SD0_SD
> +       sdhi0-pwen-hog {
> +               gpio-hog;
> +               gpios = <RZT2H_GPIO(2, 5) GPIO_ACTIVE_HIGH>;
> +               output-high;
> +               line-name = "SD0_PWEN";
> +       };
> +#endif
> +
> +       sdhi0_sd_pins: sd0-sd-group {
> +               sd0-sd-data-pins {

No need for repeated sd0-sd-prefixes in the subnodes.

> +                       pinmux = <RZT2H_PORT_PINMUX(12, 2, 0x29)>, /* SD0_DATA0 */
> +                                <RZT2H_PORT_PINMUX(12, 3, 0x29)>, /* SD0_DATA1 */
> +                                <RZT2H_PORT_PINMUX(12, 4, 0x29)>, /* SD0_DATA2 */
> +                                <RZT2H_PORT_PINMUX(12, 5, 0x29)>, /* SD0_DATA3 */
> +                                <RZT2H_PORT_PINMUX(12, 6, 0x29)>, /* SD0_DATA4 */
> +                                <RZT2H_PORT_PINMUX(12, 7, 0x29)>, /* SD0_DATA5 */
> +                                <RZT2H_PORT_PINMUX(13, 0, 0x29)>, /* SD0_DATA6 */
> +                                <RZT2H_PORT_PINMUX(13, 1, 0x29)>; /* SD0_DATA7 */
> +               };

SDcard uses only DATA0-3?

> +
> +               sd0-sd-ctrl-pins {
> +                       pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
> +                                <RZT2H_PORT_PINMUX(12, 1, 0x29)>, /* SD0_CMD */
> +                                <RZT2H_PORT_PINMUX(22, 5, 0x29)>, /* SD0_CD */
> +                                <RZT2H_PORT_PINMUX(22, 6, 0x29)>; /* SD0_WP */
> +               };
> +       };
> +
>  #if SD1_MICRO_SD
>         sdhi1-pwen-hog {
>                 gpio-hog;

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 13/13] arm64: dts: renesas: rzt2h/rzn2h: Enable SD card slot

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Mon, Aug 18, 2025 at 5:03 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, 12 Aug 2025 at 22:04, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Enable SD card slot which is connected to SDHI0 on the RZ/T2H and
> > RZ/N2H EVKs.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
>
> > @@ -104,6 +116,35 @@ sd0-emmc-ctrl-pins {
> >                 };
> >         };
> >
> > +#if SD0_SD
> > +       sdhi0-pwen-hog {
> > +               gpio-hog;
> > +               gpios = <RZT2H_GPIO(2, 5) GPIO_ACTIVE_HIGH>;
> > +               output-high;
> > +               line-name = "SD0_PWEN";
> > +       };
> > +#endif
> > +
> > +       sdhi0_sd_pins: sd0-sd-group {
> > +               sd0-sd-data-pins {
>
> No need for repeated sd0-sd-prefixes in the subnodes.
>
Ok, I will drop it.

> > +                       pinmux = <RZT2H_PORT_PINMUX(12, 2, 0x29)>, /* SD0_DATA0 */
> > +                                <RZT2H_PORT_PINMUX(12, 3, 0x29)>, /* SD0_DATA1 */
> > +                                <RZT2H_PORT_PINMUX(12, 4, 0x29)>, /* SD0_DATA2 */
> > +                                <RZT2H_PORT_PINMUX(12, 5, 0x29)>, /* SD0_DATA3 */
> > +                                <RZT2H_PORT_PINMUX(12, 6, 0x29)>, /* SD0_DATA4 */
> > +                                <RZT2H_PORT_PINMUX(12, 7, 0x29)>, /* SD0_DATA5 */
> > +                                <RZT2H_PORT_PINMUX(13, 0, 0x29)>, /* SD0_DATA6 */
> > +                                <RZT2H_PORT_PINMUX(13, 1, 0x29)>; /* SD0_DATA7 */
> > +               };
>
> SDcard uses only DATA0-3?
>
Agreed, I will drop the rest.

Cheers,
Prabhakar

> > +
> > +               sd0-sd-ctrl-pins {
> > +                       pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
> > +                                <RZT2H_PORT_PINMUX(12, 1, 0x29)>, /* SD0_CMD */
> > +                                <RZT2H_PORT_PINMUX(22, 5, 0x29)>, /* SD0_CD */
> > +                                <RZT2H_PORT_PINMUX(22, 6, 0x29)>; /* SD0_WP */
> > +               };
> > +       };
> > +
> >  #if SD1_MICRO_SD
> >         sdhi1-pwen-hog {
> >                 gpio-hog;
>
> The rest LGTM.
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds