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AJvYcCVHt1BUYpb2Ve9kaYGP0HS22MACkuTGh61CtPdiLSV5XBuZETlgeKtU6BA9NMR8shRTOpBUxJFfywKK+7lbr4FyxW4=@vger.kernel.org, AJvYcCXOJJpYlGI15UKRuQsrdLPgOG71lasAs0btPXeN+HD01IabRteMwqZ9/0+mHboLU2kuDRpPTg7HviPR@vger.kernel.org X-Gm-Message-State: AOJu0YzUf6PvVl1+aJ22+gyS05yrRUT5W/Ue3fkoC/Axla9KI4SkYsip Kqa8Qg5fx8cAKnYD26vebhLBflDWcbPFgpAmhoLBF/afTQz8mjhj6E2uCTV8NsVE/n2OqJgraql MdJ4PH5ldxWvOs0dOo7SQ1HEuiHAL0Go= X-Gm-Gg: ASbGncugKmOOyGWmeG4InvAdLSv5Sqas7D6NS/jE6Zls97XWAKnB7D1fT4VYjKpN470 M3BmzkjLSfUwX0jy0lVgbqIEjWY+FPDeOhpwQEmiP7SNF/j0p9fzUKe2Ae1GSaAQwlzgZzbrQoj wak8qHeusXnkL4Bf8hnBSXSV4mOemSHFBV/Ju+iaixc2O7Jd4VR+iPA1NrbidRP3bj5kNXqIlEl yA1FNvO X-Google-Smtp-Source: AGHT+IFMnO6qItU+vRGyl4nDXCXdkg2NGNrZXC0avjMX7zs5Kl/eMq1l2xfLh7HRUy9Varv9K9gV8qL0CKfdQ2nHxts= X-Received: by 2002:a05:600c:35ca:b0:453:81a:2f3f with SMTP id 5b1f17b1804b1-45868d4f48bmr77390065e9.30.1753372555411; Thu, 24 Jul 2025 08:55:55 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250714-ivc-v4-0-534ea488c738@ideasonboard.com> <20250714-ivc-v4-1-534ea488c738@ideasonboard.com> In-Reply-To: <20250714-ivc-v4-1-534ea488c738@ideasonboard.com> From: "Lad, Prabhakar" Date: Thu, 24 Jul 2025 16:55:28 +0100 X-Gm-Features: Ac12FXwe5ZLJsySMlTXpMt2Y8Acn98NBwBlSRLjuAJkA3ES3k2mkCyrzY6-wbOE Message-ID: Subject: Re: [PATCH v4 1/3] dt-bindings: media: Add bindings for the RZ/V2H IVC block To: Daniel Scally Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Philipp Zabel , jacopo.mondi@ideasonboard.com, biju.das.jz@bp.renesas.com, laurent.pinchart@ideasonboard.com, Krzysztof Kozlowski Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Daniel, Thank you for the patch. On Mon, Jul 14, 2025 at 4:28=E2=80=AFPM Daniel Scally wrote: > > The RZ/V2H SoC has a block called the Input Video Control block which > feeds image data into the Image Signal Processor. Add dt bindings to > describe the IVC. > > Reviewed-by: Krzysztof Kozlowski > Signed-off-by: Daniel Scally > --- > Changes in v3: > > - Rename from rzv2h-ivc.yaml to r9a09g057-ivc.yaml > - Update clock and reset names > > Changes in v2: > > - compatible matches filename > - Added power-domains > - Aligned clock and reset entries on opening "<" > - Removed status =3D "okay"; from example > --- > .../bindings/media/renesas,r9a09g057-ivc.yaml | 103 +++++++++++++++= ++++++ > 1 file changed, 103 insertions(+) > > diff --git a/Documentation/devicetree/bindings/media/renesas,r9a09g057-iv= c.yaml b/Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml > new file mode 100644 > index 0000000000000000000000000000000000000000..3ecccf0a4b05ffcf90c130924= bfe50065b06f87e > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml > @@ -0,0 +1,103 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/renesas,r9a09g057-ivc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/V2H Input Video Control Block > + s/ RZ/V2H/RZ/V2HP The 'P' variant is the one which has the Mali-C55 (also in the commit messa= ge). Rest LGTM. Cheers, Prabhakar > +maintainers: > + - Daniel Scally > + > +description: > + The IVC block is a module that takes video frames from memory and feed= s them > + to the Image Signal Processor for processing. > + > +properties: > + compatible: > + const: renesas,r9a09g057-ivc > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + items: > + - description: Input Video Control block register access clock > + - description: Video input data AXI bus clock > + - description: ISP system clock > + > + clock-names: > + items: > + - const: reg > + - const: axi > + - const: isp > + > + power-domains: > + maxItems: 1 > + > + resets: > + items: > + - description: Input Video Control block register access reset > + - description: Video input data AXI bus reset > + - description: ISP core reset > + > + reset-names: > + items: > + - const: reg > + - const: axi > + - const: isp > + > + port: > + $ref: /schemas/graph.yaml#/properties/port > + description: Output parallel video bus > + > + properties: > + endpoint: > + $ref: /schemas/graph.yaml#/properties/endpoint > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - power-domains > + - resets > + - reset-names > + - port > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + > + isp-input@16040000 { > + compatible =3D "renesas,r9a09g057-ivc"; > + reg =3D <0x16040000 0x230>; > + > + clocks =3D <&cpg CPG_MOD 0xe3>, > + <&cpg CPG_MOD 0xe4>, > + <&cpg CPG_MOD 0xe5>; > + clock-names =3D "reg", "axi", "isp"; > + > + power-domains =3D <&cpg>; > + > + resets =3D <&cpg 0xd4>, > + <&cpg 0xd1>, > + <&cpg 0xd3>; > + reset-names =3D "reg", "axi", "isp"; > + > + interrupts =3D ; > + > + port { > + ivc_out: endpoint { > + remote-endpoint =3D <&isp_in>; > + }; > + }; > + }; > +... > > -- > 2.34.1 > >