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Mon, 16 Jun 2025 04:21:19 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250530171841.423274-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20250530171841.423274-5-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: "Lad, Prabhakar" Date: Mon, 16 Jun 2025 12:20:53 +0100 X-Gm-Features: AX0GCFtgrcxJq-tg2C4PkYvICy9lU_woFiUNZXsfPzvEdHMwe4O6KkHnXumJ2Xc Message-ID: Subject: Re: [PATCH v6 4/4] drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC To: Biju Das Cc: Geert Uytterhoeven , Andrzej Hajda , Neil Armstrong , Robert Foss , "laurent.pinchart" , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Magnus Damm , "dri-devel@lists.freedesktop.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-renesas-soc@vger.kernel.org" , "linux-clk@vger.kernel.org" , Fabrizio Castro , Prabhakar Mahadev Lad Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Biju, On Mon, Jun 16, 2025 at 11:54=E2=80=AFAM Biju Das wrote: > > > > > -----Original Message----- > > From: Lad, Prabhakar > > Sent: Monday, June 16, 2025 11:48 AM > > To: Biju Das > > Cc: Geert Uytterhoeven ; Andrzej Hajda > > ; Neil Armstrong ; > > Robert Foss ; laurent.pinchart > > ; Jonas Karlman ; > > Jernej Skrabec ; Maarten Lankhorst > > ; Maxime Ripard = ; > > Thomas Zimmermann ; David Airlie ; > > Simona Vetter ; Rob Herring ; Krzyszt= of > > Kozlowski ; Conor Dooley ; > > Michael Turquette ; Stephen Boyd > > ; Magnus Damm ; dri- > > devel@lists.freedesktop.org; devicetree@vger.kernel.org; linux- > > kernel@vger.kernel.org; linux-renesas-soc@vger.kernel.org; linux- > > clk@vger.kernel.org; Fabrizio Castro ; > > Prabhakar Mahadev Lad > > Subject: Re: [PATCH v6 4/4] drm: renesas: rz-du: mipi_dsi: Add support = for > > RZ/V2H(P) SoC > > > > Hi Biju, > > > > Thank you for the review. > > > > On Fri, Jun 13, 2025 at 7:17=E2=80=AFAM Biju Das > > wrote: > > > > > > Hi Prabhakar, > > > > > > > -----Original Message----- > > > > From: Prabhakar > > > > Sent: 30 May 2025 18:19 > > > > Subject: [PATCH v6 4/4] drm: renesas: rz-du: mipi_dsi: Add support > > > > for RZ/V2H(P) SoC > > > > > > > > From: Lad Prabhakar > > > > > > > > Add DSI support for Renesas RZ/V2H(P) SoC. > > > > > > > > Co-developed-by: Fabrizio Castro > > > > Signed-off-by: Fabrizio Castro > > > > Signed-off-by: Lad Prabhakar > > > > > > > > --- > > > > v5->v6: > > > > - Made use of GENMASK() macro for PLLCLKSET0R_PLL_*, > > > > PHYTCLKSETR_* and PHYTHSSETR_* macros. > > > > - Replaced 10000000UL with 10 * MEGA > > > > - Renamed mode_freq_hz to mode_freq_khz in rzv2h_dsi_mode_calc > > > > - Replaced `i -=3D 1;` with `i--;` > > > > - Renamed RZV2H_MIPI_DPHY_FOUT_MIN_IN_MEGA to > > > > RZV2H_MIPI_DPHY_FOUT_MIN_IN_MHZ and > > > > RZV2H_MIPI_DPHY_FOUT_MAX_IN_MEGA to > > > > RZV2H_MIPI_DPHY_FOUT_MAX_IN_MHZ. > > > > > > > > v4->v5: > > > > - No changes > > > > > > > > v3->v4 > > > > - In rzv2h_dphy_find_ulpsexit() made the array static const. > > > > > > > > v2->v3: > > > > - Simplifed V2H DSI timings array to save space > > > > - Switched to use fsleep() instead of udelay() > > > > > > > > v1->v2: > > > > - Dropped unused macros > > > > - Added missing LPCLK flag to rzv2h info > > > > --- > > > > .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 345 > > ++++++++++++++++++ > > > > .../drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h | 34 ++ > > > > 2 files changed, 379 insertions(+) > > > > > > > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > > > > b/drivers/gpu/drm/renesas/rz- du/rzg2l_mipi_dsi.c index > > > > a31f9b6aa920..ea554ced6713 100644 > > > > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > > > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > > > > @@ -5,6 +5,7 @@ > > > > * Copyright (C) 2022 Renesas Electronics Corporation > > > > */ > > > > #include > > > > +#include > > > > #include > > > > #include > > > > #include > > > > > > + > > > > +static int rzv2h_dphy_conf_clks(struct rzg2l_mipi_dsi *dsi, unsign= ed > > long mode_freq, > > > > + u64 *hsfreq_millihz) { > > > > + struct rzv2h_plldsi_parameters *dsi_parameters =3D &dsi- > > >dsi_parameters; > > > > + unsigned long status; > > > > + > > > > + if (dsi->mode_calc.mode_freq_khz !=3D mode_freq) { > > > > + status =3D rzv2h_dphy_mode_clk_check(dsi, mode_freq); > > > > + if (status !=3D MODE_OK) { > > > > + dev_err(dsi->dev, "No PLL parameters found fo= r > > mode clk %lu\n", > > > > + mode_freq); > > > > + return -EINVAL; > > > > + } > > > > + } > > > > + > > > > + clk_set_rate(dsi->vclk, dsi->mode_calc.mode_freq_hz); > > > > > > Not sure, Can we use the DSI divider required based on the data rate > > > (vclk, bpp and numlanes) here > > > > > > and then the set parent clk of PLLDSI as well here (dsi->vclk * the > > divider value) ?? > > > > > > 24MHZ->PLL DSI->DSI DIVIDER->VCLOCK > > > > > > Maybe then the clock framework has all the information for setting > > PLL_DSI and DSI_DIVIDER clks?? > > > > > Can you please elaborate here with a detailed example. > > There will be determine_clk followed by set_clock for setting new rate fo= r PLL DSI(dsi->vclk * the divider value) > For eg: vclk_max =3D 187.5 MHz, DSI Divider required =3D 16 > Then set PLL_DSI =3D 187.5 * 16 MHz using clk_set. > You mean to use `clk_set_rate(dsi->vclk, (clk_get_rate(dsi->vclk) * dsi_divider));` ? Cheers, Prabhakar