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Tue, 24 Jun 2025 08:21:31 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250530171841.423274-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20250530171841.423274-2-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: "Lad, Prabhakar" Date: Tue, 24 Jun 2025 16:21:04 +0100 X-Gm-Features: Ac12FXyQhJvTm3Vt5IE8okL9cJwCx1ROPfDGJLKpKmizT9GNro2NPH4XIHLGGPU Message-ID: Subject: Re: [PATCH v6 1/4] clk: renesas: rzv2h-cpg: Add support for DSI clocks To: Biju Das Cc: Geert Uytterhoeven , Andrzej Hajda , Neil Armstrong , Robert Foss , "laurent.pinchart" , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Magnus Damm , "dri-devel@lists.freedesktop.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-renesas-soc@vger.kernel.org" , "linux-clk@vger.kernel.org" , Fabrizio Castro , Prabhakar Mahadev Lad Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Biju, On Thu, Jun 19, 2025 at 6:05=E2=80=AFAM Biju Das wrote: > > Hi Prabhakar, > > > -----Original Message----- > > From: Biju Das > > Sent: 18 June 2025 14:26 > > Subject: RE: [PATCH v6 1/4] clk: renesas: rzv2h-cpg: Add support for DS= I clocks > > > > Hi Prabhakar, > > > > > -----Original Message----- > > > From: dri-devel On Behalf O= f > > > Lad, Prabhakar > > > Sent: 16 June 2025 11:45 > > > Subject: Re: [PATCH v6 1/4] clk: renesas: rzv2h-cpg: Add support for > > > DSI clocks > > > > > > Hi Biju, > > > > > > Thank you for the review. > > > > > > On Fri, Jun 13, 2025 at 6:57=E2=80=AFAM Biju Das wrote: > > > > > > > > Hi Prabhakar, > > > > > > > > > -----Original Message----- > > > > > From: Prabhakar > > > > > Sent: 30 May 2025 18:19 > > > > .castro.jz@renesas.com>; Prabhakar Mahadev Lad > > > > lad.rj@bp.renesas.com> > > > > > Subject: [PATCH v6 1/4] clk: renesas: rzv2h-cpg: Add support for > > > > > DSI clocks > > > > > > > > > > From: Lad Prabhakar > > > > > > > > > > Add support for PLLDSI and PLLDSI divider clocks. > > > > > > > > > > Introduce the `renesas-rzv2h-dsi.h` header to centralize and shar= e > > > > > PLLDSI-related data structures, limits, and algorithms between th= e RZ/V2H CPG and DSI drivers. > > > > > > > > > > The DSI PLL is functionally similar to the CPG's PLLDSI, but has > > > > > slightly different parameter limits and omits the programmable > > > > > divider present in CPG. To ensure precise frequency > > > > > calculations-especially for milliHz-level accuracy needed by the > > > > > DSI driver-the shared algorithm > > > allows both drivers to compute PLL parameters consistently using the = same logic and input clock. > > > > > > > > > > Co-developed-by: Fabrizio Castro > > > > > Signed-off-by: Fabrizio Castro > > > > > Signed-off-by: Lad Prabhakar > > > > > > > > > > --- > > > > > v5->v6: > > > > > - Renamed CPG_PLL_STBY_SSCGEN_WEN to CPG_PLL_STBY_SSC_EN_WEN > > > > > - Updated CPG_PLL_CLK1_DIV_K, CPG_PLL_CLK1_DIV_M, and > > > > > CPG_PLL_CLK1_DIV_P macros to use GENMASK > > > > > - Updated req->rate in rzv2h_cpg_plldsi_div_determine_rate() > > > > > - Dropped the cast in rzv2h_cpg_plldsi_div_set_rate() > > > > > - Dropped rzv2h_cpg_plldsi_round_rate() and implemented > > > > > rzv2h_cpg_plldsi_determine_rate() instead > > > > > - Made use of FIELD_PREP() > > > > > - Moved CPG_CSDIV1 macro in patch 2/4 > > > > > - Dropped two_pow_s in rzv2h_dsi_get_pll_parameters_values() > > > > > - Used mul_u32_u32() while calculating output_m and output_k_rang= e > > > > > - Used div_s64() instead of div64_s64() while calculating > > > > > pll_k > > > > > - Used mul_u32_u32() while calculating fvco and fvco checks > > > > > - Rounded the final output using DIV_U64_ROUND_CLOSEST() > > > > > > > > > > v4->v5: > > > > > - No changes > > > > > > > > > > v3->v4: > > > > > - Corrected parameter name in rzv2h_dsi_get_pll_parameters_values= () > > > > > description freq_millihz > > > > > > > > > > v2->v3: > > > > > - Update the commit message to clarify the purpose of `renesas-rz= v2h-dsi.h` > > > > > header > > > > > - Used mul_u32_u32() in rzv2h_cpg_plldsi_div_determine_rate() > > > > > - Replaced *_mhz to *_millihz for clarity > > > > > - Updated u64->u32 for fvco limits > > > > > - Initialized the members in declaration order for > > > > > RZV2H_CPG_PLL_DSI_LIMITS() macro > > > > > - Used clk_div_mask() in rzv2h_cpg_plldsi_div_recalc_rate() > > > > > - Replaced `unsigned long long` with u64 > > > > > - Dropped rzv2h_cpg_plldsi_clk_recalc_rate() and reused > > > > > rzv2h_cpg_pll_clk_recalc_rate() instead > > > > > - In rzv2h_cpg_plldsi_div_set_rate() followed the same style > > > > > of RMW-operation as done in the other functions > > > > > - Renamed rzv2h_cpg_plldsi_set_rate() to rzv2h_cpg_pll_set_rate() > > > > > - Dropped rzv2h_cpg_plldsi_clk_register() and reused > > > > > rzv2h_cpg_pll_clk_register() instead > > > > > - Added a gaurd in renesas-rzv2h-dsi.h header > > > > > > > > > > v1->v2: > > > > > - No changes > > > > > --- > > > > > drivers/clk/renesas/rzv2h-cpg.c | 278 ++++++++++++++++++++= +++++- > > > > > drivers/clk/renesas/rzv2h-cpg.h | 13 ++ > > > > > include/linux/clk/renesas-rzv2h-dsi.h | 210 +++++++++++++++++++ > > > > > 3 files changed, 492 insertions(+), 9 deletions(-) create mode > > > > > 100644 include/linux/clk/renesas- rzv2h-dsi.h > > > > > > > > > > diff --git a/drivers/clk/renesas/rzv2h-cpg.c > > > > > b/drivers/clk/renesas/rzv2h-cpg.c index > > > > > 761da3bf77ce..d590f9f47371 100644 > > > > > --- a/drivers/clk/renesas/rzv2h-cpg.c > > > > > +++ b/drivers/clk/renesas/rzv2h-cpg.c > > > > > @@ -14,9 +14,13 @@ > > > > > #include > > > > > #include > > > > > #include > > > > > +#include > > > > > #include > > > > > #include > > > > > #include > > > > > +#include > > > > > > > > > > > > > > > > > + req->rate =3D > > > > > + DIV_ROUND_CLOSEST_ULL(dsi_dividers->freq_millihz, > > > > > + MILLI); > > > > > + > > > > > + return 0; > > > > > +}; > > > > > + > > > > > +static int rzv2h_cpg_plldsi_div_set_rate(struct clk_hw *hw, > > > > > + unsigned long rate, > > > > > + unsigned long parent_rate)= { > > > > > + struct rzv2h_plldsi_div_clk *dsi_div =3D to_plldsi_div_clk(= hw); > > > > > + struct rzv2h_cpg_priv *priv =3D dsi_div->priv; > > > > > + struct rzv2h_plldsi_parameters *dsi_dividers =3D &priv->pll= dsi_div_parameters; > > > > > + struct ddiv ddiv =3D dsi_div->ddiv; > > > > > + const struct clk_div_table *clkt; > > > > > + bool div_found =3D false; > > > > > + u32 val, shift, div; > > > > > + > > > > > + div =3D dsi_dividers->csdiv; > > > > > + for (clkt =3D dsi_div->dtable; clkt->div; clkt++) { > > > > > + if (clkt->div =3D=3D div) { > > > > > + div_found =3D true; > > > > > + break; > > > > > + } > > > > > + } > > > > > + > > > > > + if (!div_found) > > > > > + return -EINVAL; > > > > > > > > This check can be done in determine rate and cache the divider?? > > > > > > > Ok, I'll drop this check as the divider is already cached. The for > > > loop above is to determine the val which is used below to program the= registers. > > > > If you are caching actual divider value, then the check is not required= here. > > Otherwise the above code is fine. > > > > Assume the csdiv you found, have no corresponding match in the table. > > > 1) By looking at RZ/G3E, can we make this code more scalable? > > RZ/G3E has 2 PLL-DSI's > PLL-DSI1 supports DUAL LVDS, Single LVDS and DSI > PLL-DSI2 supports single LVDS, DPI and DSI > Sure, I'll make it more scalable. > In total there will be 4 limit tables (DSI, single LVDS, Dual LVDS and DP= I) > > Based on the display output, each PLL needs to pick the appropriate limit= table > to compute PLL parameters. > > 2) Can we drop DSI divider limits from the limit table and use the values= from dsi divider table > itself which is passed in DEF_PLLDSI_DIV? > Sure, I will do that. Cheers, Prabhakar