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From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
To: Wolfram Sang <wsa+renesas@sang-engineering.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
	Rob Herring <robh+dt@kernel.org>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	Miquel Raynal <miquel.raynal@bootlin.com>,
	Richard Weinberger <richard@nod.at>,
	Mark Brown <broonie@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Sergei Shtylyov <sergei.shtylyov@gmail.com>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
	<devicetree@vger.kernel.org>, LKML <linux-kernel@vger.kernel.org>,
	linux-mtd@lists.infradead.org,
	linux-spi <linux-spi@vger.kernel.org>,
	Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
	Prabhakar <prabhakar.csengg@gmail.com>,
	Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH v2 7/7] memory: renesas-rpc-if: Add support for RZ/G2L
Date: Tue, 2 Nov 2021 23:25:40 +0000	[thread overview]
Message-ID: <CA+V-a8uJxeSr=uoF14gccuSLG7WRqRk8X8uD9UDoxKPGM8hGgQ@mail.gmail.com> (raw)
In-Reply-To: <YYElefbpP4pwfmUl@shikoro>

Hi Wolfram,

Thank you for the review.

On Tue, Nov 2, 2021 at 11:48 AM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
>
> Hi Prabhakar,
>
> > +#define RPCIF_PHYADD         0x0070  /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
> > +#define RPCIF_PHYWR          0x0074  /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
>
> Nice detailed research, thanks! Minor nit: Keep the sorting
> alphabetical: D3, E3, V3M.
>
> > +static void rpcif_rzg2l_timing_adjust_sdr(struct rpcif *rpc)
> > +{
> > +     u32 data;
> > +
> > +     regmap_write(rpc->regmap, RPCIF_PHYWR, 0xa5390000);
> > +     regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000000);
> > +     regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080);
> > +     regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000022);
> > +     regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080);
> > +     regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000024);
> > +
> > +     regmap_read(rpc->regmap, RPCIF_PHYCNT, &data);
> > +     regmap_write(rpc->regmap, RPCIF_PHYCNT, data | RPCIF_PHYCNT_CKSEL(3));
> > +     regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00000030);
> > +     regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000032);
> > +}
>
> Still magic values here. Don't you have them explained in your Gen3
> documentation? It is tables 62.16 and 62.17 in my versions.
>
Oops I missed that, does the below look good?

#define RPCIF_PHYADD_ADD_MD 0x00
#define RPCIF_PHYADD_ADD_RDLSEL 0x22
#define RPCIF_PHYADD_ADD_FDLSEL 0x24
#define RPCIF_PHYADD_ADD_RDLMON 0x26
#define RPCIF_PHYADD_ADD_FDLMON 0x28

#define RPCIF_PHYADD_ACCEN BIT(31)
#define RPCIF_PHYADD_RW BIT(30)
#define RPCIF_PHYADD_ADD(v) (v & 0x3f)

#define RPCIF_MD_PHYREGEN_VAL 0xa539
#define RPCIF_MD_PHYREGEN(v) ((v & 0xffff) << 16)

#define RPCIF_RDLSEL_QSPI0DLTAPSEL(v) (v & 0x1f)
#define RPCIF_RDLSEL_QSPI0DLSETEN(v) ((v & 0x1) << 7)
#define RPCIF_RDLSEL_QSPI1DLTAPSEL(v) ((v & 0x1f) << 8)
#define RPCIF_RDLSEL_QSPI1DLSETEN(v) ((v & 0x1) << 15)

#define RPCIF_FDLSEL_QSPI0DLTAPSEL(v) (v & 0x1f)
#define RPCIF_FDLSEL_QSPI0DLSETEN(v) ((v & 0x1) << 7)
#define RPCIF_FDLSEL_QSPI1DLTAPSEL(v) ((v & 0x1f) << 8)
#define RPCIF_FDLSEL_QSPI1DLSETEN(v) ((v & 0x1) << 15)

> +     regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00000030);
> +     regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000032);
>
For the above do you have any suggestions? As I couldn't find any
details about it or shall I just go with magic numbers for now?

> Other than these, looks good.
>
thanks, once we agree upon above I shall re-spin v3.

Cheers,
Prabhakar

> Thanks,
>
>    Wolfram

  reply	other threads:[~2021-11-02 23:26 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-25 20:56 [PATCH v2 0/7] Add SPI Multi I/O Bus Controller support for RZ/G2L Lad Prabhakar
2021-10-25 20:56 ` [PATCH v2 1/7] dt-bindings: memory: renesas,rpc-if: Add support for the R9A07G044 Lad Prabhakar
2021-11-16 10:31   ` (subset) " Krzysztof Kozlowski
2021-10-25 20:56 ` [PATCH v2 2/7] dt-bindings: memory: renesas,rpc-if: Add optional interrupts property Lad Prabhakar
2021-11-16 10:31   ` (subset) " Krzysztof Kozlowski
2021-10-25 20:56 ` [PATCH v2 3/7] spi: spi-rpc-if: Check return value of rpcif_sw_init() Lad Prabhakar
2021-10-25 20:56 ` [PATCH v2 4/7] mtd: hyperbus: rpc-if: " Lad Prabhakar
2021-10-25 20:56 ` [PATCH v2 5/7] memory: renesas-rpc-if: Return error in case devm_ioremap_resource() fails Lad Prabhakar
2021-10-27  7:17   ` Geert Uytterhoeven
2021-10-27  7:21     ` Geert Uytterhoeven
2021-11-16 10:31   ` (subset) " Krzysztof Kozlowski
2021-10-25 20:56 ` [PATCH v2 6/7] memory: renesas-rpc-if: Drop usage of RPCIF_DIRMAP_SIZE macro Lad Prabhakar
2021-10-27  7:22   ` Geert Uytterhoeven
2021-11-16 10:31   ` (subset) " Krzysztof Kozlowski
2021-10-25 20:56 ` [PATCH v2 7/7] memory: renesas-rpc-if: Add support for RZ/G2L Lad Prabhakar
2021-10-26 14:46   ` Krzysztof Kozlowski
2021-10-27 16:16     ` Lad, Prabhakar
2021-11-02 11:48   ` Wolfram Sang
2021-11-02 23:25     ` Lad, Prabhakar [this message]
2021-11-03  8:41       ` Wolfram Sang
2021-11-03  9:12         ` Lad, Prabhakar
2021-11-15 13:03   ` Wolfram Sang
2021-11-16 11:11   ` (subset) " Krzysztof Kozlowski
2021-10-26 14:48 ` [PATCH v2 0/7] Add SPI Multi I/O Bus Controller " Krzysztof Kozlowski
2021-10-26 19:07 ` (subset) " Mark Brown
2021-11-16 10:33 ` Krzysztof Kozlowski
2021-11-16 10:40   ` Lad, Prabhakar
2021-11-16 11:11     ` Krzysztof Kozlowski

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