Re: [PATCH 1/8] riscv: add Andes SoC family Kconfig support

["Lad, Prabhakar" <prabhakar.csengg@gmail.com>]

Hi Ben,

Thank you for the patch.

On Fri, Jul 4, 2025 at 10:02 AM Ben Zong-You Xie <ben717@andestech.com> wrote:
>
> The first SoC in the Andes series is QiLai. It includes a high-performance
> quad-core RISC-V AX45MP cluster and one NX27V vector processor.
>
> For further information, refer to [1].
>
> [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
>
> Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
> ---
>  arch/riscv/Kconfig.errata | 2 +-
>  arch/riscv/Kconfig.socs   | 9 +++++++++
>  2 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> index e318119d570d..be76883704a6 100644
> --- a/arch/riscv/Kconfig.errata
> +++ b/arch/riscv/Kconfig.errata
> @@ -12,7 +12,7 @@ config ERRATA_ANDES
>
>  config ERRATA_ANDES_CMO
>         bool "Apply Andes cache management errata"
> -       depends on ERRATA_ANDES && ARCH_R9A07G043
> +       depends on ERRATA_ANDES && (ARCH_R9A07G043 || ARCH_ANDES)
>         select RISCV_DMA_NONCOHERENT
>         default y
>         help
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index a9c3d2f6debc..1bf5637f2601 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -1,5 +1,14 @@
>  menu "SoC selection"
>
> +config ARCH_ANDES
> +       bool "Andes SoCs"
> +       depends on MMU && !XIP_KERNEL
> +       select ERRATA_ANDES
> +       select ERRATA_ANDES_CMO
> +       select AX45MP_L2_CACHE
Do all the Andes SoCs require all the above three configs? (If not I
would add it based on the SoC which requires it.)

Cheers,
Prabhakar