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Fri, 05 Sep 2025 03:01:33 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250904114204.4148520-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20250904114204.4148520-7-prabhakar.mahadev-lad.rj@bp.renesas.com> <021e970a-f606-4702-9f0e-b4b0576bc5d6@lunn.ch> In-Reply-To: From: "Lad, Prabhakar" Date: Fri, 5 Sep 2025 11:01:06 +0100 X-Gm-Features: Ac12FXxIWUyvkEfUz4q5orurH6BJWRXeslXNcn11rYAmFLfl-aoQgiX5uzP0Hng Message-ID: Subject: Re: [PATCH net-next v2 6/9] net: pcs: rzn1-miic: Make switch mode mask SoC-specific To: Geert Uytterhoeven Cc: Andrew Lunn , =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Wolfram Sang , linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Fabrizio Castro , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Geert, On Fri, Sep 5, 2025 at 8:02=E2=80=AFAM Geert Uytterhoeven wrote: > > Hi Andrew, > > On Thu, 4 Sept 2025 at 22:37, Andrew Lunn wrote: > > On Thu, Sep 04, 2025 at 12:42:00PM +0100, Prabhakar wrote: > > > From: Lad Prabhakar > > > > > > Move the hardcoded switch mode mask definition into the SoC-specific > > > miic_of_data structure. This allows each SoC to define its own mask > > > value rather than relying on a single fixed constant. For RZ/N1 the > > > mask remains GENMASK(4, 0). > > > > > > This is in preparation for adding support for RZ/T2H, where the > > > switch mode mask is GENMASK(2, 0). > > > > > -#define MIIC_MODCTRL_SW_MODE GENMASK(4, 0) > > > > > miic_reg_writel(miic, MIIC_MODCTRL, > > > - FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode)); > > > + ((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_ma= sk)); > > > > _ffs() should return 0 for both GENMASK(2,0) and GENMASK(4, 0). So > > this __ffs() is pointless. > > > > You might however want to add a comment that this assumption is being > > made. > > I guess Prabhakar did it this way to make it easier to find > candidates for a future conversion to field_prep(), if this ever becomes > available[1]. > > [1] "[PATCH v3 0/4] Non-const bitfield helpers" > https://lore.kernel.org/all/cover.1739540679.git.geert+renesas@glider= .be > Ah thanks, I wanted to explore this and add a new macro but I thought it might delay this series so I dropped it. Hopefully your series will get in soon. Cheers, Prabhakar