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AJvYcCU++AHeY1PuLlt0HlqH35WJ2SmkBv2AXDauTQGqk52b7D0iWwK82OpP3Rg7twe1BpuXDtl2LW+Gz+8Hx30ge7JLh6U=@vger.kernel.org, AJvYcCVpS0o4tYHbbmh+nUgUKRihFR2veXY4GMH/n4XNdNmZS13Nm18OK2n9sFaZ2K9IpVx/NrcH52rS8Sbw9Ya/@vger.kernel.org, AJvYcCWzWCuJ8rNYBMGb6XkBGL2B3zqg9tWHCdfMzfp94PNGM4Y5ov5hqLuc1flGu3a5ADrJNVZIOec3zTk9@vger.kernel.org X-Gm-Message-State: AOJu0Yz9Bvam7xNE1MOfgwxSGz5+ZQMd2v3Lnty3mnY5O+Z4ynBjeq2Q LqqbbXoxzNyD+O+T1tiIOticjHqXUZeolsXJkttG5X1YtPvo2OnNwYnqgwbWhuWJdxiGhEHRx7e vo8KmudXJoi6mmUstt3RRIwiCnceGGlM1Fg== X-Gm-Gg: ASbGncvbIucCKkJPdw9mdoyCbokNAFI5mcjnTpTswZjQAlVc7arAziye71ZoYvbjGWI jffPArDAZdxXD2ULcPGrY5Bz81k4yYvQ/0QhGCgO4JN1ngiGOCsmjeXfjHj8RDgZIlZWiJhwEPh Ow55dnh1p7U6j6SBE3R49PVt5K6+cO9boyafdUhwx6WvXz X-Google-Smtp-Source: AGHT+IFam7AnBmamXnUVOGlJsNUroZcSdV81Gst0xilS6Q88T1PHuQXpPjhkDCLk/4lhHarbdYm39Y05LUdLc0jcq/M= X-Received: by 2002:a5d:5f53:0:b0:3a5:6860:f47f with SMTP id ffacd0b85a97d-3b495b88eedmr11142660f8f.6.1751894408902; Mon, 07 Jul 2025 06:20:08 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250704140823.163572-1-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: "Lad, Prabhakar" Date: Mon, 7 Jul 2025 14:19:42 +0100 X-Gm-Features: Ac12FXyOXebKNCVjvBbKSEe9juPyDNX0CdFTyS0OfJnPu-NDWx-uN_vg_3ec910 Message-ID: Subject: Re: [PATCH v2 0/4] arm64: dts: renesas: Add XSPI support for RZ/V2N and RZ/V2H(P) SoCs and EVK To: Geert Uytterhoeven Cc: Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Fabrizio Castro , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Geert, On Mon, Jul 7, 2025 at 2:13=E2=80=AFPM Geert Uytterhoeven wrote: > > Hi Prabhakar, > > On Fri, 4 Jul 2025 at 16:08, Prabhakar wrote= : > > From: Lad Prabhakar > > > > This patch series adds XSPI support to the Renesas RZ/V2N (R9A09G056) > > and RZ/V2H(P) (R9A09G057) SoCs. It introduces the XSPI controller nodes > > in the SoC-level DTSI files and enables a connected serial NOR flash > > device on the respective evaluation boards. > > > > Note, > > - DT binding patches have been posted seprately [0] > > > > > > [0] https://lore.kernel.org/all/20250624171605.469724-1-prabhakar.mahad= ev-lad.rj@bp.renesas.com/ > > > > v1->v2: > > - Added Reviewed-by tags from Geert > > - Moved assigned-clocks and assigned-clock-rates properties to board DT= S > > Thanks, will queue in renesas-devel for v6.17. > > * MT25QU512ABB8E12 flash chip is capable of running at 166MHz > * clock frequency. Set the maximum clock frequency to 133MHz > * supported by the RZ/V2N SoC. > > Shouldn't that be: > > * MT25QU512ABB8E12 flash chip is capable of running at 166MHz > * clock frequency. Set the clock frequency to the maximum 133MHz > * supported by the RZ/V2N SoC. > I agree that the above makes it clearer. Thank you for taking care of it. Cheers, Prabhakar