Re: [PATCH v7 06/10] ARM: dts: rockchip: Add Rockchip RV1126 SoC

[Jagan Teki <jagan@edgeble.ai>]

On Tue, 15 Nov 2022 at 13:25, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 15/11/2022 07:38, Jagan Teki wrote:
> > On Tue, 8 Nov 2022 at 23:43, Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >>
> >> On 08/11/2022 05:13, Jagan Teki wrote:
> >>> RV1126 is a high-performance vision processor SoC for IPC/CVR,
> >>> especially for AI related application.
> >>>
> >>> It is based on quad-core ARM Cortex-A7 32-bit core which integrates
> >>> NEON and FPU. There is a 32KB I-cache and 32KB D-cache for each core
> >>> and 512KB unified L2 cache. It has build-in NPU supports INT8/INT16
> >>> hybrid operation and computing power is up to 2.0TOPs.
> >>>
> >>> This patch add basic core dtsi support.
> >>>
> >>> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
> >>> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
> >>> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> >>> ---
> >>> Changes for v7:
> >>> - fix dtbs_check
> >>> - rearrange nodes
> >>> - remove Edegble in license text
> >>> Changes for v6:
> >>> - add psci node
> >>> Changes for v5:
> >>> - none
> >>> Changes for v4:
> >>> - update i2c0
> >>> - rebase on -next
> >>> Changes for v3:
> >>> - update cru and power file names
> >>> Changes for v2:
> >>> - split pinctrl in separate patch
> >>>
> >>>  arch/arm/boot/dts/rv1126.dtsi | 438 ++++++++++++++++++++++++++++++++++
> >>>  1 file changed, 438 insertions(+)
> >>>  create mode 100644 arch/arm/boot/dts/rv1126.dtsi
> >>>
> >>> diff --git a/arch/arm/boot/dts/rv1126.dtsi b/arch/arm/boot/dts/rv1126.dtsi
> >>> new file mode 100644
> >>> index 000000000000..a485420551f5
> >>> --- /dev/null
> >>> +++ b/arch/arm/boot/dts/rv1126.dtsi
> >>> @@ -0,0 +1,438 @@
> >>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> >>> +/*
> >>> + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
> >>> + */
> >>> +
> >>> +#include <dt-bindings/clock/rockchip,rv1126-cru.h>
> >>> +#include <dt-bindings/gpio/gpio.h>
> >>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> >>> +#include <dt-bindings/interrupt-controller/irq.h>
> >>> +#include <dt-bindings/pinctrl/rockchip.h>
> >>> +#include <dt-bindings/power/rockchip,rv1126-power.h>
> >>> +#include <dt-bindings/soc/rockchip,boot-mode.h>
> >>> +
> >>> +/ {
> >>> +     #address-cells = <1>;
> >>> +     #size-cells = <1>;
> >>> +
> >>> +     compatible = "rockchip,rv1126";
> >>> +
> >>> +     interrupt-parent = <&gic>;
> >>> +
> >>> +     aliases {
> >>> +             i2c0 = &i2c0;
> >>> +             serial0 = &uart0;
> >>> +             serial1 = &uart1;
> >>> +             serial2 = &uart2;
> >>> +             serial3 = &uart3;
> >>> +             serial4 = &uart4;
> >>> +             serial5 = &uart5;
> >>
> >> These are not properties of a SoC but board. They depend on the
> >> particular routing on the board... unless this SoC is an exception from
> >> all others?
> >
> > Was this a new feature to follow, didn't see this before at least
> > rockchip SoC's.
> >
>
> It's not exactly new comment, but rather not always enforced/given.

It seems like i2c0 and serial aliases are required across SoC instead
of the specific board. An example of which i2c0 connected via PMIC
which indeed require aliases to get a probe, which is common across
SoC.

[    1.778941] i2c_dev: i2c /dev entries driver
[    1.780877] rk3x-i2c ff3f0000.i2c: rk3x-i2c needs i2cX alias
[    1.781410] rk3x-i2c: probe of ff3f0000.i2c failed with error -22
[    1.791312] Bluetooth: HCI UART driver ver 2.3

Thanks,
Jagan.