From: Zong Li <zongbox@gmail.com>
To: Conor.Dooley@microchip.com
Cc: zong.li@sifive.com, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com,
paul.walmsley@sifive.com, aou@eecs.berkeley.edu,
greentime.hu@sifive.com, ben.dooks@sifive.com, bp@alien8.de,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 5/6] soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes
Date: Tue, 6 Sep 2022 09:38:10 +0800 [thread overview]
Message-ID: <CA+ZOyahFAQGPb4Ffqb_6NcaoxNLCdyBEeoY=ySJ4zLK8bhqWkg@mail.gmail.com> (raw)
In-Reply-To: <74571708-be33-bee2-fdc2-01492f121cda@microchip.com>
<Conor.Dooley@microchip.com> 於 2022年9月6日 週二 凌晨2:47寫道：
>
> On 05/09/2022 09:31, Zong Li wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > From: Ben Dooks <ben.dooks@sifive.com>
> >
> > Use the pr_fmt() macro to prefix all the output with "CCACHE:"
> > to avoid having to write it out each time, or make a large diff
> > when the next change comes along.
> >
> > Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
>
> Missing your SoB again here Zong Li btw, other than that:
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks, I would add it in V3.
>
> > ---
> > drivers/soc/sifive/sifive_ccache.c | 15 +++++++++------
> > 1 file changed, 9 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> > index 401c67a485e2..d749600c0bf8 100644
> > --- a/drivers/soc/sifive/sifive_ccache.c
> > +++ b/drivers/soc/sifive/sifive_ccache.c
> > @@ -5,6 +5,9 @@
> > * Copyright (C) 2018-2022 SiFive, Inc.
> > *
> > */
> > +
> > +#define pr_fmt(fmt) "CCACHE: " fmt
> > +
> > #include <linux/debugfs.h>
> > #include <linux/interrupt.h>
> > #include <linux/of_irq.h>
> > @@ -85,13 +88,13 @@ static void ccache_config_read(void)
> >
> > cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> >
> > - pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
> > + pr_info("%u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
> > (cfg & 0xff), (cfg >> 8) & 0xff,
> > BIT_ULL((cfg >> 16) & 0xff),
> > BIT_ULL((cfg >> 24) & 0xff));
> >
> > cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> > - pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg);
> > + pr_info("Index of the largest way enabled: %d\n", cfg);
> > }
> >
> > static const struct of_device_id sifive_ccache_ids[] = {
> > @@ -154,7 +157,7 @@ static irqreturn_t ccache_int_handler(int irq, void *device)
> > if (irq == g_irq[DIR_CORR]) {
> > add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH);
> > add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW);
> > - pr_err("CCACHE: DirError @ 0x%08X.%08X\n", add_h, add_l);
> > + pr_err("DirError @ 0x%08X.%08X\n", add_h, add_l);
> > /* Reading this register clears the DirError interrupt sig */
> > readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT);
> > atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE,
> > @@ -172,7 +175,7 @@ static irqreturn_t ccache_int_handler(int irq, void *device)
> > if (irq == g_irq[DATA_CORR]) {
> > add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH);
> > add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW);
> > - pr_err("CCACHE: DataError @ 0x%08X.%08X\n", add_h, add_l);
> > + pr_err("DataError @ 0x%08X.%08X\n", add_h, add_l);
> > /* Reading this register clears the DataError interrupt sig */
> > readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT);
> > atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE,
> > @@ -181,7 +184,7 @@ static irqreturn_t ccache_int_handler(int irq, void *device)
> > if (irq == g_irq[DATA_UNCORR]) {
> > add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH);
> > add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW);
> > - pr_err("CCACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l);
> > + pr_err("DataFail @ 0x%08X.%08X\n", add_h, add_l);
> > /* Reading this register clears the DataFail interrupt sig */
> > readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT);
> > atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_UE,
> > @@ -221,7 +224,7 @@ static int __init sifive_ccache_init(void)
> > g_irq[i] = irq_of_parse_and_map(np, i);
> > rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", NULL);
> > if (rc) {
> > - pr_err("CCACHE: Could not request IRQ %d\n", g_irq[i]);
> > + pr_err("Could not request IRQ %d\n", g_irq[i]);
> > return rc;
> > }
> > }
> > --
> > 2.17.1
> >
>
next prev parent reply other threads:[~2022-09-06 1:38 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-05 8:31 [PATCH v2 0/6] Use composable cache instead of L2 cache Zong Li
2022-09-05 8:31 ` [PATCH v2 1/6] dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache Zong Li
2022-09-05 18:02 ` Conor.Dooley
2022-09-08 21:21 ` Rob Herring
2022-09-08 21:32 ` Conor.Dooley
2022-09-05 8:31 ` [PATCH v2 2/6] soc: sifive: ccache: Rename SiFive " Zong Li
2022-09-05 18:10 ` Conor.Dooley
2022-09-06 1:52 ` Zong Li
2022-09-05 18:46 ` Conor.Dooley
2022-09-06 1:44 ` Zong Li
2022-09-06 6:23 ` Conor.Dooley
2022-09-06 6:51 ` Zong Li
2022-09-05 8:31 ` [PATCH v2 3/6] soc: sifive: ccache: determine the cache level from dts Zong Li
2022-09-05 18:14 ` Conor.Dooley
2022-09-06 1:57 ` Zong Li
2022-09-05 8:31 ` [PATCH v2 4/6] soc: sifive: ccache: reduce printing on init Zong Li
2022-09-05 18:36 ` Conor.Dooley
2022-09-06 1:40 ` Zong Li
2022-09-05 8:31 ` [PATCH v2 5/6] soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes Zong Li
2022-09-05 18:44 ` Conor.Dooley
2022-09-06 1:38 ` Zong Li [this message]
2022-09-05 8:31 ` [PATCH v2 6/6] EDAC/sifive: use sifive_ccache instead of sifive_l2 Zong Li
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