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AJvYcCU46TBywit1ngTmT67cmvf//62jqKIhrCVvrR6q1kspnkmQn0PxE6Sz8Hh9NXXaUPuD3VKN+gczE0jM@vger.kernel.org X-Gm-Message-State: AOJu0YxcIXIE9/wBamyAi7tsB8tBEEuT/EUIpzT4Rz+aSlyDw5cORTYu a55MBafyx73IlgeTQEPMrFfVaB8f1/NhgJ7EhFNRO+2/tnwA02SrYfgDXSlKh07JzN2Bkc1H/Hh hCmtYwoIH6HCoYHKt48DmG/zAG8wRZU3wWbYpP1b5 X-Gm-Gg: ASbGnctA8SYTa7OGkZpsbkaWSl83iA7BJkSIUUTvvlUgFIvMPKFUv589A0TZ2Kmcclo F0VsO6NI58LWiEH8xFw8BoIjU3+KOrls709koIXltUY82wi8t4LxirDjwyctoZL9e3SlYPgY+I1 he2tgu4Judayy9XNSySApA4AVbaArM3QyYZtMSpupnls/C7lmSnl3/tKQKTgPBLrcsZi6Xj8mNB 65F1GGUQbCYDSY9N+czNp/azI+TMK2Cd6sDWIGSnTSRmRjUAyq+9SDlAuQByTmtpCYSQYZi+VUo X-Google-Smtp-Source: AGHT+IH/gaVhehz3sRp9VrrzaU79D/o/NZJP8CN7/dl/fC68uxDpeqnl6j3qA8EnLxqoVUctH31vKw6FBzQox/YYs6w= X-Received: by 2002:a17:903:2408:b0:28e:7fce:667e with SMTP id d9443c01a7336-2902723f51emr324260245ad.17.1760406045183; Mon, 13 Oct 2025 18:40:45 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20251010201607.1190967-1-royluo@google.com> <20251010201607.1190967-2-royluo@google.com> <066a9598-ad30-4327-be68-87299bba6fda@kernel.org> In-Reply-To: <066a9598-ad30-4327-be68-87299bba6fda@kernel.org> From: Roy Luo Date: Mon, 13 Oct 2025 18:40:08 -0700 X-Gm-Features: AS18NWCf063mHzWv1lf5a6FraaWgtqWiANzRpv6KaU2cy8h_cSvnS3pGamEVoLc Message-ID: Subject: Re: [PATCH v3 1/4] dt-bindings: usb: dwc3: Add Google Tensor G5 DWC3 To: Krzysztof Kozlowski Cc: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Thinh Nguyen , Philipp Zabel , Peter Griffin , =?UTF-8?Q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Joy Chakraborty , Naveen Kumar , Badhri Jagan Sridharan , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, Oct 10, 2025 at 5:09=E2=80=AFPM Krzysztof Kozlowski wrote: > > On 10/10/2025 22:16, Roy Luo wrote: > > Document the device tree bindings for the DWC3 USB controller found in > > Google Tensor SoCs, starting with the G5 generation. > > > > The Tensor G5 silicon represents a complete architectural departure fro= m > > previous generations (like gs101), including entirely new clock/reset > > schemes, top-level wrapper and register interface. Consequently, > > existing Samsung/Exynos DWC3 USB bindings are incompatible, necessitati= ng > > this new device tree binding. > > > > The USB controller on Tensor G5 is based on Synopsys DWC3 IP and featur= es > > Dual-Role Device single port with hibernation support. > > You still mix, completely unnecessarily, subsystems. For Greg this is > actually even undesired, but regardless don't do this for any cases > because it just makes everything slower or more difficult to apply. > > Really, think how maintainers should deal with your patches. > Understood, I will separate the patches into two distinct series: one for the controller and one for the PHY. Appreciate the feedback and the explanation. > > > > Signed-off-by: Roy Luo > > --- > > .../bindings/usb/google,gs5-dwc3.yaml | 141 ++++++++++++++++++ > > 1 file changed, 141 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/usb/google,gs5-dw= c3.yaml > > > > diff --git a/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml= b/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml > > new file mode 100644 > > index 000000000000..6fadea7f41e8 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml > > @@ -0,0 +1,141 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +# Copyright (c) 2025, Google LLC > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/usb/google,gs5-dwc3.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Google Tensor Series (G5+) DWC3 USB SoC Controller > > + > > +maintainers: > > + - Roy Luo > > + > > +description: > > + Describes the DWC3 USB controller block implemented on Google Tensor= SoCs, > > + starting with the G5 generation. Based on Synopsys DWC3 IP, the cont= roller > > + features Dual-Role Device single port with hibernation add-on. > > + > > +properties: > > + compatible: > > + const: google,gs5-dwc3 > > + > > + reg: > > + items: > > + - description: Core DWC3 IP registers. > > + - description: USB host controller configuration registers. > > + - description: USB custom interrrupts control registers. > > + > > + reg-names: > > + items: > > + - const: dwc3_core > > + - const: host_cfg > > + - const: usbint_cfg > > + > > + interrupts: > > + items: > > + - description: Core DWC3 interrupt. > > + - description: High speed power management event for remote wake= up from hibernation. > > + - description: Super speed power management event for remote wak= eup from hibernation. > > Wrap at 80 (see coding style) or just shorten these. Ack, will fix it in the next patch. > > > + > > + interrupt-names: > > + items: > > + - const: dwc_usb3 > > So just "core"? I'd prefer to stick to "dwc_usb3" as that's 1. more expressive by referring to the underlying IP name, 2. consistent with established dwc3 bindings such as Documentation/devicetree/bindings/usb/snps,dwc3.yaml, Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml, unless you have a strong preference for the alternative naming. > > > + - const: hs_pme > > + - const: ss_pme > > + > > + clocks: > > + items: > > + - description: Non-sticky module clock. > > + - description: Sticky module clock. > > + - description: USB2 PHY APB clock. > > This looks wrong. This is not the USB2 phy, so how can it consume APB clo= ck? That's a fair point, I'll look into the necessity and placement of this spe= cific clk/reset and get back. Thanks, Roy Luo > > > + > > + clock-names: > > + items: > > + - const: non_sticky > > + - const: sticky > > + - const: u2phy_apb > > + > > + resets: > > + items: > > + - description: Non-sticky module reset. > > + - description: Sticky module reset. > > + - description: USB2 PHY APB reset. > > This as well. > > > + - description: DRD bus reset. > > + - description: Top-level reset. > > + > > + reset-names: > > + items: > > + - const: non_sticky > > + - const: sticky > > + - const: u2phy_apb > > + - const: drd_bus > > + - const: top > > > Best regards, > Krzysztof