From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Robert Marko <robimarko@gmail.com>
Cc: bjorn.andersson@linaro.org, agross@kernel.org,
konrad.dybcio@somainline.org, mturquette@baylibre.com,
sboyd@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, sivaprak@codeaurora.org,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Christian Marangi <ansuelsmth@gmail.com>
Subject: Re: [PATCH 1/6] clk: qcom: clk-rcg2: add rcg2 mux ops
Date: Mon, 11 Jul 2022 17:38:45 +0300 [thread overview]
Message-ID: <CAA8EJpo-83y=z_uRePLg0upUuhWc439FKBq_sy_Z=5kriD7unw@mail.gmail.com> (raw)
In-Reply-To: <20220711104719.40939-1-robimarko@gmail.com>
On Mon, 11 Jul 2022 at 14:22, Robert Marko <robimarko@gmail.com> wrote:
>
> From: Christian Marangi <ansuelsmth@gmail.com>
>
> An RCG may act as a mux that switch between 2 parents.
> This is the case on IPQ6018 and IPQ8074 where the APCS core clk that feeds
> the CPU cluster clock just switches between XO and the PLL that feeds it.
>
> Add the required ops to add support for this special configuration and use
> the generic mux function to determine the rate.
>
> This way we dont have to keep a essentially dummy frequency table to use
> RCG2 as a mux.
>
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/clk/qcom/clk-rcg.h | 1 +
> drivers/clk/qcom/clk-rcg2.c | 7 +++++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
> index 012e745794fd..01581f4d2c39 100644
> --- a/drivers/clk/qcom/clk-rcg.h
> +++ b/drivers/clk/qcom/clk-rcg.h
> @@ -167,6 +167,7 @@ struct clk_rcg2_gfx3d {
>
> extern const struct clk_ops clk_rcg2_ops;
> extern const struct clk_ops clk_rcg2_floor_ops;
> +extern const struct clk_ops clk_rcg2_mux_closest_ops;
> extern const struct clk_ops clk_edp_pixel_ops;
> extern const struct clk_ops clk_byte_ops;
> extern const struct clk_ops clk_byte2_ops;
> diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
> index 28019edd2a50..609c10f8d0d9 100644
> --- a/drivers/clk/qcom/clk-rcg2.c
> +++ b/drivers/clk/qcom/clk-rcg2.c
> @@ -509,6 +509,13 @@ const struct clk_ops clk_rcg2_floor_ops = {
> };
> EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops);
>
> +const struct clk_ops clk_rcg2_mux_closest_ops = {
> + .determine_rate = __clk_mux_determine_rate_closest,
> + .get_parent = clk_rcg2_get_parent,
> + .set_parent = clk_rcg2_set_parent,
> +};
> +EXPORT_SYMBOL_GPL(clk_rcg2_mux_closest_ops);
> +
> struct frac_entry {
> int num;
> int den;
> --
> 2.36.1
>
--
With best wishes
Dmitry
prev parent reply other threads:[~2022-07-11 14:39 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-11 10:47 [PATCH 1/6] clk: qcom: clk-rcg2: add rcg2 mux ops Robert Marko
2022-07-11 10:47 ` [PATCH 2/6] clk: qcom: apss-ipq6018: fix apcs_alias0_clk_src Robert Marko
2022-07-11 12:48 ` Dmitry Baryshkov
2022-07-11 13:23 ` Robert Marko
2022-07-11 14:38 ` Dmitry Baryshkov
2022-07-11 10:47 ` [PATCH 3/6] clk: qcom: apss-ipq6018: mark apcs_alias0_core_clk as critical Robert Marko
2022-07-11 12:49 ` Dmitry Baryshkov
2022-07-11 10:47 ` [PATCH 4/6] clk: qcom: apss-ipq6018: add MODULE_ALIAS Robert Marko
2022-07-11 11:05 ` Krzysztof Kozlowski
2022-07-11 11:46 ` Robert Marko
2022-07-11 12:02 ` Krzysztof Kozlowski
2022-07-11 12:45 ` Robert Marko
2022-07-11 10:47 ` [PATCH 5/6] dt-bindings: clock: qcom,a53pll: add IPQ8074 compatible Robert Marko
2022-07-11 11:04 ` Krzysztof Kozlowski
2022-07-11 10:47 ` [PATCH 6/6] clk: qcom: apss-ipq-pll: add support for IPQ8074 Robert Marko
2022-07-11 11:06 ` Krzysztof Kozlowski
2022-07-11 12:51 ` Dmitry Baryshkov
2022-07-11 12:55 ` Robert Marko
2022-07-11 12:56 ` Dmitry Baryshkov
2022-07-11 14:38 ` Dmitry Baryshkov [this message]
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