* [PATCH v3 1/6] dt-bindings: display/msm/gmu: add Adreno 660 support
2023-02-09 13:38 [PATCH v3 0/6] arm64: dts: qcom: sm8350: enable GPU on the HDK board Dmitry Baryshkov
@ 2023-02-09 13:38 ` Dmitry Baryshkov
2023-02-09 13:38 ` [PATCH v3 2/6] arm64: dts: qcom: sm8350: reorder device nodes Dmitry Baryshkov
` (6 subsequent siblings)
7 siblings, 0 replies; 17+ messages in thread
From: Dmitry Baryshkov @ 2023-02-09 13:38 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul,
Abhinav Kumar, Rob Herring, Krzysztof Kozlowski
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
devicetree, dri-devel, freedreno, Rob Herring
Add Adreno A660 to the A635 clause to define all version-specific
properties. There is no need to add it to the top-level clause, since
top-level compatible uses pattern to define compatible strings.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Documentation/devicetree/bindings/display/msm/gmu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml
index ab14e81cb050..d5ce0dff4220 100644
--- a/Documentation/devicetree/bindings/display/msm/gmu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml
@@ -122,6 +122,7 @@ allOf:
contains:
enum:
- qcom,adreno-gmu-635.0
+ - qcom,adreno-gmu-660.1
then:
properties:
reg:
--
2.39.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v3 2/6] arm64: dts: qcom: sm8350: reorder device nodes
2023-02-09 13:38 [PATCH v3 0/6] arm64: dts: qcom: sm8350: enable GPU on the HDK board Dmitry Baryshkov
2023-02-09 13:38 ` [PATCH v3 1/6] dt-bindings: display/msm/gmu: add Adreno 660 support Dmitry Baryshkov
@ 2023-02-09 13:38 ` Dmitry Baryshkov
2023-02-09 13:38 ` [PATCH v3 3/6] arm64: dts: qcom: sm8350: move more nodes to correct place Dmitry Baryshkov
` (5 subsequent siblings)
7 siblings, 0 replies; 17+ messages in thread
From: Dmitry Baryshkov @ 2023-02-09 13:38 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul,
Abhinav Kumar, Rob Herring, Krzysztof Kozlowski
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
devicetree, dri-devel, freedreno
Somehow sm8350 got its device nodes not fully sorted. Start reordering
DT nodes by their address. Move apps SMMU, GIC, timer, apps RSC, cpufreq
ADSP and cDSP nodes to the end to the proper position at the end of
/soc/.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 1228 +++++++++++++-------------
1 file changed, 614 insertions(+), 614 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 0a422637b61f..b85bd8fd28c0 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1421,111 +1421,6 @@ spi13: spi@a94000 {
};
};
- apps_smmu: iommu@15000000 {
- compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
- reg = <0 0x15000000 0 0x100000>;
- #iommu-cells = <2>;
- #global-interrupts = <2>;
- interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
- };
-
config_noc: interconnect@1500000 {
compatible = "qcom,sm8350-config-noc";
reg = <0 0x01500000 0 0xa580>;
@@ -2124,253 +2019,92 @@ rng: rng@10d3000 {
clock-names = "core";
};
- intc: interrupt-controller@17a00000 {
- compatible = "arm,gic-v3";
- #interrupt-cells = <3>;
- interrupt-controller;
- #redistributor-regions = <1>;
- redistributor-stride = <0 0x20000>;
- reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
- <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- };
+ ufs_mem_hc: ufshc@1d84000 {
+ compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
+ "jedec,ufs-2.0";
+ reg = <0 0x01d84000 0 0x3000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&ufs_mem_phy_lanes>;
+ phy-names = "ufsphy";
+ lanes-per-direction = <2>;
+ #reset-cells = <1>;
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
- timer@17c20000 {
- compatible = "arm,armv7-timer-mem";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0 0x20000000>;
- reg = <0x0 0x17c20000 0x0 0x1000>;
- clock-frequency = <19200000>;
+ power-domains = <&gcc UFS_PHY_GDSC>;
- frame@17c21000 {
- frame-number = <0>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x17c21000 0x1000>,
- <0x17c22000 0x1000>;
- };
+ iommus = <&apps_smmu 0xe0 0x0>;
- frame@17c23000 {
- frame-number = <1>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x17c23000 0x1000>;
- status = "disabled";
- };
+ clock-names =
+ "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
+ clocks =
+ <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ freq-table-hz =
+ <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+ status = "disabled";
+ };
- frame@17c25000 {
- frame-number = <2>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x17c25000 0x1000>;
- status = "disabled";
- };
+ ufs_mem_phy: phy@1d87000 {
+ compatible = "qcom,sm8350-qmp-ufs-phy";
+ reg = <0 0x01d87000 0 0x1c4>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ clock-names = "ref",
+ "ref_aux";
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
- frame@17c27000 {
- frame-number = <3>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x17c27000 0x1000>;
- status = "disabled";
- };
+ resets = <&ufs_mem_hc 0>;
+ reset-names = "ufsphy";
+ status = "disabled";
- frame@17c29000 {
- frame-number = <4>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x17c29000 0x1000>;
- status = "disabled";
+ ufs_mem_phy_lanes: phy@1d87400 {
+ reg = <0 0x01d87400 0 0x188>,
+ <0 0x01d87600 0 0x200>,
+ <0 0x01d87c00 0 0x200>,
+ <0 0x01d87800 0 0x188>,
+ <0 0x01d87a00 0 0x200>;
+ #clock-cells = <1>;
+ #phy-cells = <0>;
};
+ };
- frame@17c2b000 {
- frame-number = <5>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x17c2b000 0x1000>;
- status = "disabled";
- };
+ slpi: remoteproc@5c00000 {
+ compatible = "qcom,sm8350-slpi-pas";
+ reg = <0 0x05c00000 0 0x4000>;
- frame@17c2d000 {
- frame-number = <6>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x17c2d000 0x1000>;
- status = "disabled";
- };
- };
+ interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
+ <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready",
+ "handover", "stop-ack";
- apps_rsc: rsc@18200000 {
- label = "apps_rsc";
- compatible = "qcom,rpmh-rsc";
- reg = <0x0 0x18200000 0x0 0x10000>,
- <0x0 0x18210000 0x0 0x10000>,
- <0x0 0x18220000 0x0 0x10000>;
- reg-names = "drv-0", "drv-1", "drv-2";
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- qcom,tcs-offset = <0xd00>;
- qcom,drv-id = <2>;
- qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
- <WAKE_TCS 3>, <CONTROL_TCS 0>;
- power-domains = <&CLUSTER_PD>;
-
- rpmhcc: clock-controller {
- compatible = "qcom,sm8350-rpmh-clk";
- #clock-cells = <1>;
- clock-names = "xo";
- clocks = <&xo_board>;
- };
-
- rpmhpd: power-controller {
- compatible = "qcom,sm8350-rpmhpd";
- #power-domain-cells = <1>;
- operating-points-v2 = <&rpmhpd_opp_table>;
-
- rpmhpd_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- rpmhpd_opp_ret: opp1 {
- opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
- };
-
- rpmhpd_opp_min_svs: opp2 {
- opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
- };
-
- rpmhpd_opp_low_svs: opp3 {
- opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
- };
-
- rpmhpd_opp_svs: opp4 {
- opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
- };
-
- rpmhpd_opp_svs_l1: opp5 {
- opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
- };
-
- rpmhpd_opp_nom: opp6 {
- opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
- };
-
- rpmhpd_opp_nom_l1: opp7 {
- opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
- };
-
- rpmhpd_opp_nom_l2: opp8 {
- opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
- };
-
- rpmhpd_opp_turbo: opp9 {
- opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
- };
-
- rpmhpd_opp_turbo_l1: opp10 {
- opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
- };
- };
- };
-
- apps_bcm_voter: bcm-voter {
- compatible = "qcom,bcm-voter";
- };
- };
-
- cpufreq_hw: cpufreq@18591000 {
- compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
- reg = <0 0x18591000 0 0x1000>,
- <0 0x18592000 0 0x1000>,
- <0 0x18593000 0 0x1000>;
- reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
-
- clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
- clock-names = "xo", "alternate";
-
- #freq-domain-cells = <1>;
- };
-
- ufs_mem_hc: ufshc@1d84000 {
- compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
- "jedec,ufs-2.0";
- reg = <0 0x01d84000 0 0x3000>;
- interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufs_mem_phy_lanes>;
- phy-names = "ufsphy";
- lanes-per-direction = <2>;
- #reset-cells = <1>;
- resets = <&gcc GCC_UFS_PHY_BCR>;
- reset-names = "rst";
-
- power-domains = <&gcc UFS_PHY_GDSC>;
-
- iommus = <&apps_smmu 0xe0 0x0>;
-
- clock-names =
- "core_clk",
- "bus_aggr_clk",
- "iface_clk",
- "core_clk_unipro",
- "ref_clk",
- "tx_lane0_sync_clk",
- "rx_lane0_sync_clk",
- "rx_lane1_sync_clk";
- clocks =
- <&gcc GCC_UFS_PHY_AXI_CLK>,
- <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
- <&gcc GCC_UFS_PHY_AHB_CLK>,
- <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
- <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
- <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
- freq-table-hz =
- <75000000 300000000>,
- <0 0>,
- <0 0>,
- <75000000 300000000>,
- <0 0>,
- <0 0>,
- <0 0>,
- <0 0>;
- status = "disabled";
- };
-
- ufs_mem_phy: phy@1d87000 {
- compatible = "qcom,sm8350-qmp-ufs-phy";
- reg = <0 0x01d87000 0 0x1c4>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- clock-names = "ref",
- "ref_aux";
- clocks = <&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
-
- resets = <&ufs_mem_hc 0>;
- reset-names = "ufsphy";
- status = "disabled";
-
- ufs_mem_phy_lanes: phy@1d87400 {
- reg = <0 0x01d87400 0 0x188>,
- <0 0x01d87600 0 0x200>,
- <0 0x01d87c00 0 0x200>,
- <0 0x01d87800 0 0x188>,
- <0 0x01d87a00 0 0x200>;
- #clock-cells = <1>;
- #phy-cells = <0>;
- };
- };
-
- slpi: remoteproc@5c00000 {
- compatible = "qcom,sm8350-slpi-pas";
- reg = <0 0x05c00000 0 0x4000>;
-
- interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
- <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "wdog", "fatal", "ready",
- "handover", "stop-ack";
-
- clocks = <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "xo";
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
power-domains = <&rpmhpd SM8350_LCX>,
<&rpmhpd SM8350_LMX>;
@@ -2425,176 +2159,67 @@ compute-cb@3 {
};
};
- cdsp: remoteproc@98900000 {
- compatible = "qcom,sm8350-cdsp-pas";
- reg = <0 0x98900000 0 0x1400000>;
-
- interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
- <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "wdog", "fatal", "ready",
- "handover", "stop-ack";
+ sdhc_2: mmc@8804000 {
+ compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0 0x08804000 0 0x1000>;
- clocks = <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "xo";
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
- power-domains = <&rpmhpd SM8350_CX>,
- <&rpmhpd SM8350_MXC>;
- power-domain-names = "cx", "mxc";
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "core", "xo";
+ resets = <&gcc GCC_SDCC2_BCR>;
+ interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
+ interconnect-names = "sdhc-ddr","cpu-sdhc";
+ iommus = <&apps_smmu 0x4a0 0x0>;
+ power-domains = <&rpmhpd SM8350_CX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
+ bus-width = <4>;
+ dma-coherent;
- interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
+ status = "disabled";
- memory-region = <&pil_cdsp_mem>;
+ sdhc2_opp_table: opp-table {
+ compatible = "operating-points-v2";
- qcom,qmp = <&aoss_qmp>;
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
- qcom,smem-states = <&smp2p_cdsp_out 0>;
- qcom,smem-state-names = "stop";
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+ usb_1_hsphy: phy@88e3000 {
+ compatible = "qcom,sm8350-usb-hs-phy",
+ "qcom,usb-snps-hs-7nm-phy";
+ reg = <0 0x088e3000 0 0x400>;
status = "disabled";
+ #phy-cells = <0>;
- glink-edge {
- interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
- IPCC_MPROC_SIGNAL_GLINK_QMP
- IRQ_TYPE_EDGE_RISING>;
- mboxes = <&ipcc IPCC_CLIENT_CDSP
- IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "ref";
- label = "cdsp";
- qcom,remote-pid = <5>;
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+ };
- fastrpc {
- compatible = "qcom,fastrpc";
- qcom,glink-channels = "fastrpcglink-apps-dsp";
- label = "cdsp";
- qcom,non-secure-domain;
- #address-cells = <1>;
- #size-cells = <0>;
+ usb_2_hsphy: phy@88e4000 {
+ compatible = "qcom,sm8250-usb-hs-phy",
+ "qcom,usb-snps-hs-7nm-phy";
+ reg = <0 0x088e4000 0 0x400>;
+ status = "disabled";
+ #phy-cells = <0>;
- compute-cb@1 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <1>;
- iommus = <&apps_smmu 0x2161 0x0400>,
- <&apps_smmu 0x1181 0x0420>;
- };
-
- compute-cb@2 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <2>;
- iommus = <&apps_smmu 0x2162 0x0400>,
- <&apps_smmu 0x1182 0x0420>;
- };
-
- compute-cb@3 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <3>;
- iommus = <&apps_smmu 0x2163 0x0400>,
- <&apps_smmu 0x1183 0x0420>;
- };
-
- compute-cb@4 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <4>;
- iommus = <&apps_smmu 0x2164 0x0400>,
- <&apps_smmu 0x1184 0x0420>;
- };
-
- compute-cb@5 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <5>;
- iommus = <&apps_smmu 0x2165 0x0400>,
- <&apps_smmu 0x1185 0x0420>;
- };
-
- compute-cb@6 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <6>;
- iommus = <&apps_smmu 0x2166 0x0400>,
- <&apps_smmu 0x1186 0x0420>;
- };
-
- compute-cb@7 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <7>;
- iommus = <&apps_smmu 0x2167 0x0400>,
- <&apps_smmu 0x1187 0x0420>;
- };
-
- compute-cb@8 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <8>;
- iommus = <&apps_smmu 0x2168 0x0400>,
- <&apps_smmu 0x1188 0x0420>;
- };
-
- /* note: secure cb9 in downstream */
- };
- };
- };
-
- sdhc_2: mmc@8804000 {
- compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";
- reg = <0 0x08804000 0 0x1000>;
-
- interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hc_irq", "pwr_irq";
-
- clocks = <&gcc GCC_SDCC2_AHB_CLK>,
- <&gcc GCC_SDCC2_APPS_CLK>,
- <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "iface", "core", "xo";
- resets = <&gcc GCC_SDCC2_BCR>;
- interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
- interconnect-names = "sdhc-ddr","cpu-sdhc";
- iommus = <&apps_smmu 0x4a0 0x0>;
- power-domains = <&rpmhpd SM8350_CX>;
- operating-points-v2 = <&sdhc2_opp_table>;
- bus-width = <4>;
- dma-coherent;
-
- status = "disabled";
-
- sdhc2_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- required-opps = <&rpmhpd_opp_low_svs>;
- };
-
- opp-202000000 {
- opp-hz = /bits/ 64 <202000000>;
- required-opps = <&rpmhpd_opp_svs_l1>;
- };
- };
- };
-
- usb_1_hsphy: phy@88e3000 {
- compatible = "qcom,sm8350-usb-hs-phy",
- "qcom,usb-snps-hs-7nm-phy";
- reg = <0 0x088e3000 0 0x400>;
- status = "disabled";
- #phy-cells = <0>;
-
- clocks = <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "ref";
-
- resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
- };
-
- usb_2_hsphy: phy@88e4000 {
- compatible = "qcom,sm8250-usb-hs-phy",
- "qcom,usb-snps-hs-7nm-phy";
- reg = <0 0x088e4000 0 0x400>;
- status = "disabled";
- #phy-cells = <0>;
-
- clocks = <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "ref";
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "ref";
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
};
@@ -2985,190 +2610,565 @@ mdss_dsi0_phy: phy@ae94400 {
status = "disabled";
};
- mdss_dsi1: dsi@ae96000 {
- compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
- reg = <0 0x0ae96000 0 0x400>;
- reg-names = "dsi_ctrl";
+ mdss_dsi1: dsi@ae96000 {
+ compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae96000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <5>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC1_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi1_phy 0>,
+ <&mdss_dsi1_phy 1>;
+
+ operating-points-v2 = <&dsi1_opp_table>;
+ power-domains = <&rpmhpd SM8350_MMCX>;
+
+ phys = <&mdss_dsi1_phy>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ dsi1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /* TODO: opp-187500000 should work with
+ * &rpmhpd_opp_low_svs, but one some of
+ * sm8350_hdk boards reboot using this
+ * opp.
+ */
+ opp-187500000 {
+ opp-hz = /bits/ 64 <187500000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dsi1_in: endpoint {
+ remote-endpoint = <&dpu_intf2_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss_dsi1_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi1_phy: phy@ae96400 {
+ compatible = "qcom,sm8350-dsi-phy-5nm";
+ reg = <0 0x0ae96400 0 0x200>,
+ <0 0x0ae96600 0 0x280>,
+ <0 0x0ae96900 0 0x27c>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+ };
+
+ dispcc: clock-controller@af00000 {
+ compatible = "qcom,sm8350-dispcc";
+ reg = <0 0x0af00000 0 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>,
+ <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>,
+ <0>,
+ <0>;
+ clock-names = "bi_tcxo",
+ "dsi0_phy_pll_out_byteclk",
+ "dsi0_phy_pll_out_dsiclk",
+ "dsi1_phy_pll_out_byteclk",
+ "dsi1_phy_pll_out_dsiclk",
+ "dp_phy_pll_link_clk",
+ "dp_phy_pll_vco_div_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+
+ power-domains = <&rpmhpd SM8350_MMCX>;
+ };
+
+ apps_smmu: iommu@15000000 {
+ compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
+ reg = <0 0x15000000 0 0x100000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ adsp: remoteproc@17300000 {
+ compatible = "qcom,sm8350-adsp-pas";
+ reg = <0 0x17300000 0 0x100>;
+
+ interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
+ <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready",
+ "handover", "stop-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd SM8350_LCX>,
+ <&rpmhpd SM8350_LMX>;
+ power-domain-names = "lcx", "lmx";
+
+ memory-region = <&pil_adsp_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_adsp_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ label = "lpass";
+ qcom,remote-pid = <2>;
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "adsp";
+ qcom,non-secure-domain;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <&apps_smmu 0x1803 0x0>;
+ };
+
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+ iommus = <&apps_smmu 0x1804 0x0>;
+ };
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+ iommus = <&apps_smmu 0x1805 0x0>;
+ };
+ };
+ };
+ };
+
+ intc: interrupt-controller@17a00000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ #redistributor-regions = <1>;
+ redistributor-stride = <0 0x20000>;
+ reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
+ <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ timer@17c20000 {
+ compatible = "arm,armv7-timer-mem";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0x20000000>;
+ reg = <0x0 0x17c20000 0x0 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@17c21000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c21000 0x1000>,
+ <0x17c22000 0x1000>;
+ };
+
+ frame@17c23000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c23000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c25000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c25000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c27000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c27000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c29000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c29000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c2b000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c2b000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c2d000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c2d000 0x1000>;
+ status = "disabled";
+ };
+ };
- interrupt-parent = <&mdss>;
- interrupts = <5>;
+ apps_rsc: rsc@18200000 {
+ label = "apps_rsc";
+ compatible = "qcom,rpmh-rsc";
+ reg = <0x0 0x18200000 0x0 0x10000>,
+ <0x0 0x18210000 0x0 0x10000>,
+ <0x0 0x18220000 0x0 0x10000>;
+ reg-names = "drv-0", "drv-1", "drv-2";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
+ <WAKE_TCS 3>, <CONTROL_TCS 0>;
+ power-domains = <&CLUSTER_PD>;
- clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
- <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
- <&dispcc DISP_CC_MDSS_ESC1_CLK>,
- <&dispcc DISP_CC_MDSS_AHB_CLK>,
- <&gcc GCC_DISP_HF_AXI_CLK>;
- clock-names = "byte",
- "byte_intf",
- "pixel",
- "core",
- "iface",
- "bus";
+ rpmhcc: clock-controller {
+ compatible = "qcom,sm8350-rpmh-clk";
+ #clock-cells = <1>;
+ clock-names = "xo";
+ clocks = <&xo_board>;
+ };
- assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
- assigned-clock-parents = <&mdss_dsi1_phy 0>,
- <&mdss_dsi1_phy 1>;
+ rpmhpd: power-controller {
+ compatible = "qcom,sm8350-rpmhpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmhpd_opp_table>;
- operating-points-v2 = <&dsi1_opp_table>;
- power-domains = <&rpmhpd SM8350_MMCX>;
+ rpmhpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
- phys = <&mdss_dsi1_phy>;
+ rpmhpd_opp_ret: opp1 {
+ opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
- #address-cells = <1>;
- #size-cells = <0>;
+ rpmhpd_opp_min_svs: opp2 {
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
- status = "disabled";
+ rpmhpd_opp_low_svs: opp3 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
- dsi1_opp_table: opp-table {
- compatible = "operating-points-v2";
+ rpmhpd_opp_svs: opp4 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
- /* TODO: opp-187500000 should work with
- * &rpmhpd_opp_low_svs, but one some of
- * sm8350_hdk boards reboot using this
- * opp.
- */
- opp-187500000 {
- opp-hz = /bits/ 64 <187500000>;
- required-opps = <&rpmhpd_opp_svs>;
+ rpmhpd_opp_svs_l1: opp5 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
};
- opp-300000000 {
- opp-hz = /bits/ 64 <300000000>;
- required-opps = <&rpmhpd_opp_svs>;
+ rpmhpd_opp_nom: opp6 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
};
- opp-358000000 {
- opp-hz = /bits/ 64 <358000000>;
- required-opps = <&rpmhpd_opp_svs_l1>;
+ rpmhpd_opp_nom_l1: opp7 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
};
- };
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
+ rpmhpd_opp_nom_l2: opp8 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+ };
- port@0 {
- reg = <0>;
- mdss_dsi1_in: endpoint {
- remote-endpoint = <&dpu_intf2_out>;
- };
+ rpmhpd_opp_turbo: opp9 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
};
- port@1 {
- reg = <1>;
- mdss_dsi1_out: endpoint {
- };
+ rpmhpd_opp_turbo_l1: opp10 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
};
};
};
- mdss_dsi1_phy: phy@ae96400 {
- compatible = "qcom,sm8350-dsi-phy-5nm";
- reg = <0 0x0ae96400 0 0x200>,
- <0 0x0ae96600 0 0x280>,
- <0 0x0ae96900 0 0x27c>;
- reg-names = "dsi_phy",
- "dsi_phy_lane",
- "dsi_pll";
-
- #clock-cells = <1>;
- #phy-cells = <0>;
-
- clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
- <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "iface", "ref";
-
- status = "disabled";
+ apps_bcm_voter: bcm-voter {
+ compatible = "qcom,bcm-voter";
};
};
- dispcc: clock-controller@af00000 {
- compatible = "qcom,sm8350-dispcc";
- reg = <0 0x0af00000 0 0x10000>;
- clocks = <&rpmhcc RPMH_CXO_CLK>,
- <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>,
- <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>,
- <0>,
- <0>;
- clock-names = "bi_tcxo",
- "dsi0_phy_pll_out_byteclk",
- "dsi0_phy_pll_out_dsiclk",
- "dsi1_phy_pll_out_byteclk",
- "dsi1_phy_pll_out_dsiclk",
- "dp_phy_pll_link_clk",
- "dp_phy_pll_vco_div_clk";
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
+ cpufreq_hw: cpufreq@18591000 {
+ compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
+ reg = <0 0x18591000 0 0x1000>,
+ <0 0x18592000 0 0x1000>,
+ <0 0x18593000 0 0x1000>;
+ reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
- power-domains = <&rpmhpd SM8350_MMCX>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+
+ #freq-domain-cells = <1>;
};
- adsp: remoteproc@17300000 {
- compatible = "qcom,sm8350-adsp-pas";
- reg = <0 0x17300000 0 0x100>;
+ cdsp: remoteproc@98900000 {
+ compatible = "qcom,sm8350-cdsp-pas";
+ reg = <0 0x98900000 0 0x1400000>;
- interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
- <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
+ <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&rpmhpd SM8350_LCX>,
- <&rpmhpd SM8350_LMX>;
- power-domain-names = "lcx", "lmx";
+ power-domains = <&rpmhpd SM8350_CX>,
+ <&rpmhpd SM8350_MXC>;
+ power-domain-names = "cx", "mxc";
- memory-region = <&pil_adsp_mem>;
+ interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
+
+ memory-region = <&pil_cdsp_mem>;
qcom,qmp = <&aoss_qmp>;
- qcom,smem-states = <&smp2p_adsp_out 0>;
+ qcom,smem-states = <&smp2p_cdsp_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
glink-edge {
- interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+ interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
- mboxes = <&ipcc IPCC_CLIENT_LPASS
+ mboxes = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
- label = "lpass";
- qcom,remote-pid = <2>;
+ label = "cdsp";
+ qcom,remote-pid = <5>;
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
- label = "adsp";
+ label = "cdsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
+ compute-cb@1 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <1>;
+ iommus = <&apps_smmu 0x2161 0x0400>,
+ <&apps_smmu 0x1181 0x0420>;
+ };
+
+ compute-cb@2 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <2>;
+ iommus = <&apps_smmu 0x2162 0x0400>,
+ <&apps_smmu 0x1182 0x0420>;
+ };
+
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
- iommus = <&apps_smmu 0x1803 0x0>;
+ iommus = <&apps_smmu 0x2163 0x0400>,
+ <&apps_smmu 0x1183 0x0420>;
};
compute-cb@4 {
compatible = "qcom,fastrpc-compute-cb";
reg = <4>;
- iommus = <&apps_smmu 0x1804 0x0>;
+ iommus = <&apps_smmu 0x2164 0x0400>,
+ <&apps_smmu 0x1184 0x0420>;
};
compute-cb@5 {
compatible = "qcom,fastrpc-compute-cb";
reg = <5>;
- iommus = <&apps_smmu 0x1805 0x0>;
+ iommus = <&apps_smmu 0x2165 0x0400>,
+ <&apps_smmu 0x1185 0x0420>;
+ };
+
+ compute-cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+ iommus = <&apps_smmu 0x2166 0x0400>,
+ <&apps_smmu 0x1186 0x0420>;
};
+
+ compute-cb@7 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <7>;
+ iommus = <&apps_smmu 0x2167 0x0400>,
+ <&apps_smmu 0x1187 0x0420>;
+ };
+
+ compute-cb@8 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <8>;
+ iommus = <&apps_smmu 0x2168 0x0400>,
+ <&apps_smmu 0x1188 0x0420>;
+ };
+
+ /* note: secure cb9 in downstream */
};
};
};
--
2.39.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v3 3/6] arm64: dts: qcom: sm8350: move more nodes to correct place
2023-02-09 13:38 [PATCH v3 0/6] arm64: dts: qcom: sm8350: enable GPU on the HDK board Dmitry Baryshkov
2023-02-09 13:38 ` [PATCH v3 1/6] dt-bindings: display/msm/gmu: add Adreno 660 support Dmitry Baryshkov
2023-02-09 13:38 ` [PATCH v3 2/6] arm64: dts: qcom: sm8350: reorder device nodes Dmitry Baryshkov
@ 2023-02-09 13:38 ` Dmitry Baryshkov
2023-02-10 11:03 ` Konrad Dybcio
2023-02-09 13:38 ` [PATCH v3 4/6] arm64: dts: qcom: sm8350: finish reordering nodes Dmitry Baryshkov
` (4 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Dmitry Baryshkov @ 2023-02-09 13:38 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul,
Abhinav Kumar, Rob Herring, Krzysztof Kozlowski
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
devicetree, dri-devel, freedreno
Continue ordering DT nodes by their address. Move RNG, UFS, system NoC
and SLPI nodes to the proper position.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 314 +++++++++++++--------------
1 file changed, 157 insertions(+), 157 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index b85bd8fd28c0..8bf38d350521 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1421,6 +1421,13 @@ spi13: spi@a94000 {
};
};
+ rng: rng@10d3000 {
+ compatible = "qcom,prng-ee";
+ reg = <0 0x010d3000 0 0x1000>;
+ clocks = <&rpmhcc RPMH_HWKM_CLK>;
+ clock-names = "core";
+ };
+
config_noc: interconnect@1500000 {
compatible = "qcom,sm8350-config-noc";
reg = <0 0x01500000 0 0xa580>;
@@ -1641,18 +1648,76 @@ pcie1_phy: phy@1c0f000 {
status = "disabled";
};
- lpass_ag_noc: interconnect@3c40000 {
- compatible = "qcom,sm8350-lpass-ag-noc";
- reg = <0 0x03c40000 0 0xf080>;
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
+ ufs_mem_hc: ufshc@1d84000 {
+ compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
+ "jedec,ufs-2.0";
+ reg = <0 0x01d84000 0 0x3000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&ufs_mem_phy_lanes>;
+ phy-names = "ufsphy";
+ lanes-per-direction = <2>;
+ #reset-cells = <1>;
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
+
+ power-domains = <&gcc UFS_PHY_GDSC>;
+
+ iommus = <&apps_smmu 0xe0 0x0>;
+
+ clock-names =
+ "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
+ clocks =
+ <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ freq-table-hz =
+ <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+ status = "disabled";
};
- compute_noc: interconnect@a0c0000 {
- compatible = "qcom,sm8350-compute-noc";
- reg = <0 0x0a0c0000 0 0xa180>;
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
+ ufs_mem_phy: phy@1d87000 {
+ compatible = "qcom,sm8350-qmp-ufs-phy";
+ reg = <0 0x01d87000 0 0x1c4>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ clock-names = "ref",
+ "ref_aux";
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+
+ resets = <&ufs_mem_hc 0>;
+ reset-names = "ufsphy";
+ status = "disabled";
+
+ ufs_mem_phy_lanes: phy@1d87400 {
+ reg = <0 0x01d87400 0 0x188>,
+ <0 0x01d87600 0 0x200>,
+ <0 0x01d87c00 0 0x200>,
+ <0 0x01d87800 0 0x188>,
+ <0 0x01d87a00 0 0x200>;
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+ };
};
ipa: ipa@1e40000 {
@@ -1700,6 +1765,13 @@ tcsr_mutex: hwlock@1f40000 {
#hwlock-cells = <1>;
};
+ lpass_ag_noc: interconnect@3c40000 {
+ compatible = "qcom,sm8350-lpass-ag-noc";
+ reg = <0 0x03c40000 0 0xf080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
mpss: remoteproc@4080000 {
compatible = "qcom,sm8350-mpss-pas";
reg = <0x0 0x04080000 0x0 0x4040>;
@@ -1742,6 +1814,74 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
};
};
+ slpi: remoteproc@5c00000 {
+ compatible = "qcom,sm8350-slpi-pas";
+ reg = <0 0x05c00000 0 0x4000>;
+
+ interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
+ <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready",
+ "handover", "stop-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd SM8350_LCX>,
+ <&rpmhpd SM8350_LMX>;
+ power-domain-names = "lcx", "lmx";
+
+ memory-region = <&pil_slpi_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_slpi_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_SLPI
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ label = "slpi";
+ qcom,remote-pid = <3>;
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "sdsp";
+ qcom,non-secure-domain;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@1 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <1>;
+ iommus = <&apps_smmu 0x0541 0x0>;
+ };
+
+ compute-cb@2 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <2>;
+ iommus = <&apps_smmu 0x0542 0x0>;
+ };
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <&apps_smmu 0x0543 0x0>;
+ /* note: shared-cb = <4> in downstream */
+ };
+ };
+ };
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8350-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
@@ -2012,153 +2152,6 @@ qup_i2c19_default: qup-i2c19-default-state {
};
};
- rng: rng@10d3000 {
- compatible = "qcom,prng-ee";
- reg = <0 0x010d3000 0 0x1000>;
- clocks = <&rpmhcc RPMH_HWKM_CLK>;
- clock-names = "core";
- };
-
- ufs_mem_hc: ufshc@1d84000 {
- compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
- "jedec,ufs-2.0";
- reg = <0 0x01d84000 0 0x3000>;
- interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufs_mem_phy_lanes>;
- phy-names = "ufsphy";
- lanes-per-direction = <2>;
- #reset-cells = <1>;
- resets = <&gcc GCC_UFS_PHY_BCR>;
- reset-names = "rst";
-
- power-domains = <&gcc UFS_PHY_GDSC>;
-
- iommus = <&apps_smmu 0xe0 0x0>;
-
- clock-names =
- "core_clk",
- "bus_aggr_clk",
- "iface_clk",
- "core_clk_unipro",
- "ref_clk",
- "tx_lane0_sync_clk",
- "rx_lane0_sync_clk",
- "rx_lane1_sync_clk";
- clocks =
- <&gcc GCC_UFS_PHY_AXI_CLK>,
- <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
- <&gcc GCC_UFS_PHY_AHB_CLK>,
- <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
- <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
- <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
- freq-table-hz =
- <75000000 300000000>,
- <0 0>,
- <0 0>,
- <75000000 300000000>,
- <0 0>,
- <0 0>,
- <0 0>,
- <0 0>;
- status = "disabled";
- };
-
- ufs_mem_phy: phy@1d87000 {
- compatible = "qcom,sm8350-qmp-ufs-phy";
- reg = <0 0x01d87000 0 0x1c4>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- clock-names = "ref",
- "ref_aux";
- clocks = <&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
-
- resets = <&ufs_mem_hc 0>;
- reset-names = "ufsphy";
- status = "disabled";
-
- ufs_mem_phy_lanes: phy@1d87400 {
- reg = <0 0x01d87400 0 0x188>,
- <0 0x01d87600 0 0x200>,
- <0 0x01d87c00 0 0x200>,
- <0 0x01d87800 0 0x188>,
- <0 0x01d87a00 0 0x200>;
- #clock-cells = <1>;
- #phy-cells = <0>;
- };
- };
-
- slpi: remoteproc@5c00000 {
- compatible = "qcom,sm8350-slpi-pas";
- reg = <0 0x05c00000 0 0x4000>;
-
- interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
- <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "wdog", "fatal", "ready",
- "handover", "stop-ack";
-
- clocks = <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "xo";
-
- power-domains = <&rpmhpd SM8350_LCX>,
- <&rpmhpd SM8350_LMX>;
- power-domain-names = "lcx", "lmx";
-
- memory-region = <&pil_slpi_mem>;
-
- qcom,qmp = <&aoss_qmp>;
-
- qcom,smem-states = <&smp2p_slpi_out 0>;
- qcom,smem-state-names = "stop";
-
- status = "disabled";
-
- glink-edge {
- interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
- IPCC_MPROC_SIGNAL_GLINK_QMP
- IRQ_TYPE_EDGE_RISING>;
- mboxes = <&ipcc IPCC_CLIENT_SLPI
- IPCC_MPROC_SIGNAL_GLINK_QMP>;
-
- label = "slpi";
- qcom,remote-pid = <3>;
-
- fastrpc {
- compatible = "qcom,fastrpc";
- qcom,glink-channels = "fastrpcglink-apps-dsp";
- label = "sdsp";
- qcom,non-secure-domain;
- #address-cells = <1>;
- #size-cells = <0>;
-
- compute-cb@1 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <1>;
- iommus = <&apps_smmu 0x0541 0x0>;
- };
-
- compute-cb@2 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <2>;
- iommus = <&apps_smmu 0x0542 0x0>;
- };
-
- compute-cb@3 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <3>;
- iommus = <&apps_smmu 0x0543 0x0>;
- /* note: shared-cb = <4> in downstream */
- };
- };
- };
- };
-
sdhc_2: mmc@8804000 {
compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x08804000 0 0x1000>;
@@ -2307,6 +2300,13 @@ system-cache-controller@9200000 {
reg-names = "llcc_base", "llcc_broadcast_base";
};
+ compute_noc: interconnect@a0c0000 {
+ compatible = "qcom,sm8350-compute-noc";
+ reg = <0 0x0a0c0000 0 0xa180>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
usb_1: usb@a6f8800 {
compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
--
2.39.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v3 3/6] arm64: dts: qcom: sm8350: move more nodes to correct place
2023-02-09 13:38 ` [PATCH v3 3/6] arm64: dts: qcom: sm8350: move more nodes to correct place Dmitry Baryshkov
@ 2023-02-10 11:03 ` Konrad Dybcio
0 siblings, 0 replies; 17+ messages in thread
From: Konrad Dybcio @ 2023-02-10 11:03 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Rob Clark,
Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
devicetree, dri-devel, freedreno
On 9.02.2023 14:38, Dmitry Baryshkov wrote:
> Continue ordering DT nodes by their address. Move RNG, UFS, system NoC
> and SLPI nodes to the proper position.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 314 +++++++++++++--------------
> 1 file changed, 157 insertions(+), 157 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index b85bd8fd28c0..8bf38d350521 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -1421,6 +1421,13 @@ spi13: spi@a94000 {
> };
> };
>
> + rng: rng@10d3000 {
> + compatible = "qcom,prng-ee";
> + reg = <0 0x010d3000 0 0x1000>;
> + clocks = <&rpmhcc RPMH_HWKM_CLK>;
> + clock-names = "core";
> + };
> +
> config_noc: interconnect@1500000 {
> compatible = "qcom,sm8350-config-noc";
> reg = <0 0x01500000 0 0xa580>;
> @@ -1641,18 +1648,76 @@ pcie1_phy: phy@1c0f000 {
> status = "disabled";
> };
>
> - lpass_ag_noc: interconnect@3c40000 {
> - compatible = "qcom,sm8350-lpass-ag-noc";
> - reg = <0 0x03c40000 0 0xf080>;
> - #interconnect-cells = <2>;
> - qcom,bcm-voters = <&apps_bcm_voter>;
> + ufs_mem_hc: ufshc@1d84000 {
> + compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
> + "jedec,ufs-2.0";
> + reg = <0 0x01d84000 0 0x3000>;
> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&ufs_mem_phy_lanes>;
> + phy-names = "ufsphy";
> + lanes-per-direction = <2>;
> + #reset-cells = <1>;
> + resets = <&gcc GCC_UFS_PHY_BCR>;
> + reset-names = "rst";
> +
> + power-domains = <&gcc UFS_PHY_GDSC>;
> +
> + iommus = <&apps_smmu 0xe0 0x0>;
> +
> + clock-names =
> + "core_clk",
> + "bus_aggr_clk",
> + "iface_clk",
> + "core_clk_unipro",
> + "ref_clk",
> + "tx_lane0_sync_clk",
> + "rx_lane0_sync_clk",
> + "rx_lane1_sync_clk";
> + clocks =
> + <&gcc GCC_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_UFS_PHY_AHB_CLK>,
> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> + freq-table-hz =
> + <75000000 300000000>,
> + <0 0>,
> + <0 0>,
> + <75000000 300000000>,
> + <0 0>,
> + <0 0>,
> + <0 0>,
> + <0 0>;
> + status = "disabled";
> };
>
> - compute_noc: interconnect@a0c0000 {
> - compatible = "qcom,sm8350-compute-noc";
> - reg = <0 0x0a0c0000 0 0xa180>;
> - #interconnect-cells = <2>;
> - qcom,bcm-voters = <&apps_bcm_voter>;
> + ufs_mem_phy: phy@1d87000 {
> + compatible = "qcom,sm8350-qmp-ufs-phy";
> + reg = <0 0x01d87000 0 0x1c4>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + clock-names = "ref",
> + "ref_aux";
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
> +
> + resets = <&ufs_mem_hc 0>;
> + reset-names = "ufsphy";
> + status = "disabled";
> +
> + ufs_mem_phy_lanes: phy@1d87400 {
> + reg = <0 0x01d87400 0 0x188>,
> + <0 0x01d87600 0 0x200>,
> + <0 0x01d87c00 0 0x200>,
> + <0 0x01d87800 0 0x188>,
> + <0 0x01d87a00 0 0x200>;
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> + };
> };
>
> ipa: ipa@1e40000 {
> @@ -1700,6 +1765,13 @@ tcsr_mutex: hwlock@1f40000 {
> #hwlock-cells = <1>;
> };
>
> + lpass_ag_noc: interconnect@3c40000 {
> + compatible = "qcom,sm8350-lpass-ag-noc";
> + reg = <0 0x03c40000 0 0xf080>;
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> mpss: remoteproc@4080000 {
> compatible = "qcom,sm8350-mpss-pas";
> reg = <0x0 0x04080000 0x0 0x4040>;
> @@ -1742,6 +1814,74 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
> };
> };
>
> + slpi: remoteproc@5c00000 {
> + compatible = "qcom,sm8350-slpi-pas";
> + reg = <0 0x05c00000 0 0x4000>;
> +
> + interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
> + <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "wdog", "fatal", "ready",
> + "handover", "stop-ack";
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "xo";
> +
> + power-domains = <&rpmhpd SM8350_LCX>,
> + <&rpmhpd SM8350_LMX>;
> + power-domain-names = "lcx", "lmx";
> +
> + memory-region = <&pil_slpi_mem>;
> +
> + qcom,qmp = <&aoss_qmp>;
> +
> + qcom,smem-states = <&smp2p_slpi_out 0>;
> + qcom,smem-state-names = "stop";
> +
> + status = "disabled";
> +
> + glink-edge {
> + interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
> + IPCC_MPROC_SIGNAL_GLINK_QMP
> + IRQ_TYPE_EDGE_RISING>;
> + mboxes = <&ipcc IPCC_CLIENT_SLPI
> + IPCC_MPROC_SIGNAL_GLINK_QMP>;
> +
> + label = "slpi";
> + qcom,remote-pid = <3>;
> +
> + fastrpc {
> + compatible = "qcom,fastrpc";
> + qcom,glink-channels = "fastrpcglink-apps-dsp";
> + label = "sdsp";
> + qcom,non-secure-domain;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + compute-cb@1 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <1>;
> + iommus = <&apps_smmu 0x0541 0x0>;
> + };
> +
> + compute-cb@2 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <2>;
> + iommus = <&apps_smmu 0x0542 0x0>;
> + };
> +
> + compute-cb@3 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <3>;
> + iommus = <&apps_smmu 0x0543 0x0>;
> + /* note: shared-cb = <4> in downstream */
> + };
> + };
> + };
> + };
> +
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,sm8350-pdc", "qcom,pdc";
> reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
> @@ -2012,153 +2152,6 @@ qup_i2c19_default: qup-i2c19-default-state {
> };
> };
>
> - rng: rng@10d3000 {
> - compatible = "qcom,prng-ee";
> - reg = <0 0x010d3000 0 0x1000>;
> - clocks = <&rpmhcc RPMH_HWKM_CLK>;
> - clock-names = "core";
> - };
> -
> - ufs_mem_hc: ufshc@1d84000 {
> - compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
> - "jedec,ufs-2.0";
> - reg = <0 0x01d84000 0 0x3000>;
> - interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> - phys = <&ufs_mem_phy_lanes>;
> - phy-names = "ufsphy";
> - lanes-per-direction = <2>;
> - #reset-cells = <1>;
> - resets = <&gcc GCC_UFS_PHY_BCR>;
> - reset-names = "rst";
> -
> - power-domains = <&gcc UFS_PHY_GDSC>;
> -
> - iommus = <&apps_smmu 0xe0 0x0>;
> -
> - clock-names =
> - "core_clk",
> - "bus_aggr_clk",
> - "iface_clk",
> - "core_clk_unipro",
> - "ref_clk",
> - "tx_lane0_sync_clk",
> - "rx_lane0_sync_clk",
> - "rx_lane1_sync_clk";
> - clocks =
> - <&gcc GCC_UFS_PHY_AXI_CLK>,
> - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> - <&gcc GCC_UFS_PHY_AHB_CLK>,
> - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> - <&rpmhcc RPMH_CXO_CLK>,
> - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> - freq-table-hz =
> - <75000000 300000000>,
> - <0 0>,
> - <0 0>,
> - <75000000 300000000>,
> - <0 0>,
> - <0 0>,
> - <0 0>,
> - <0 0>;
> - status = "disabled";
> - };
> -
> - ufs_mem_phy: phy@1d87000 {
> - compatible = "qcom,sm8350-qmp-ufs-phy";
> - reg = <0 0x01d87000 0 0x1c4>;
> - #address-cells = <2>;
> - #size-cells = <2>;
> - ranges;
> - clock-names = "ref",
> - "ref_aux";
> - clocks = <&rpmhcc RPMH_CXO_CLK>,
> - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
> -
> - resets = <&ufs_mem_hc 0>;
> - reset-names = "ufsphy";
> - status = "disabled";
> -
> - ufs_mem_phy_lanes: phy@1d87400 {
> - reg = <0 0x01d87400 0 0x188>,
> - <0 0x01d87600 0 0x200>,
> - <0 0x01d87c00 0 0x200>,
> - <0 0x01d87800 0 0x188>,
> - <0 0x01d87a00 0 0x200>;
> - #clock-cells = <1>;
> - #phy-cells = <0>;
> - };
> - };
> -
> - slpi: remoteproc@5c00000 {
> - compatible = "qcom,sm8350-slpi-pas";
> - reg = <0 0x05c00000 0 0x4000>;
> -
> - interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
> - <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
> - <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
> - <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
> - <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
> - interrupt-names = "wdog", "fatal", "ready",
> - "handover", "stop-ack";
> -
> - clocks = <&rpmhcc RPMH_CXO_CLK>;
> - clock-names = "xo";
> -
> - power-domains = <&rpmhpd SM8350_LCX>,
> - <&rpmhpd SM8350_LMX>;
> - power-domain-names = "lcx", "lmx";
> -
> - memory-region = <&pil_slpi_mem>;
> -
> - qcom,qmp = <&aoss_qmp>;
> -
> - qcom,smem-states = <&smp2p_slpi_out 0>;
> - qcom,smem-state-names = "stop";
> -
> - status = "disabled";
> -
> - glink-edge {
> - interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
> - IPCC_MPROC_SIGNAL_GLINK_QMP
> - IRQ_TYPE_EDGE_RISING>;
> - mboxes = <&ipcc IPCC_CLIENT_SLPI
> - IPCC_MPROC_SIGNAL_GLINK_QMP>;
> -
> - label = "slpi";
> - qcom,remote-pid = <3>;
> -
> - fastrpc {
> - compatible = "qcom,fastrpc";
> - qcom,glink-channels = "fastrpcglink-apps-dsp";
> - label = "sdsp";
> - qcom,non-secure-domain;
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - compute-cb@1 {
> - compatible = "qcom,fastrpc-compute-cb";
> - reg = <1>;
> - iommus = <&apps_smmu 0x0541 0x0>;
> - };
> -
> - compute-cb@2 {
> - compatible = "qcom,fastrpc-compute-cb";
> - reg = <2>;
> - iommus = <&apps_smmu 0x0542 0x0>;
> - };
> -
> - compute-cb@3 {
> - compatible = "qcom,fastrpc-compute-cb";
> - reg = <3>;
> - iommus = <&apps_smmu 0x0543 0x0>;
> - /* note: shared-cb = <4> in downstream */
> - };
> - };
> - };
> - };
> -
> sdhc_2: mmc@8804000 {
> compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";
> reg = <0 0x08804000 0 0x1000>;
> @@ -2307,6 +2300,13 @@ system-cache-controller@9200000 {
> reg-names = "llcc_base", "llcc_broadcast_base";
> };
>
> + compute_noc: interconnect@a0c0000 {
> + compatible = "qcom,sm8350-compute-noc";
> + reg = <0 0x0a0c0000 0 0xa180>;
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> usb_1: usb@a6f8800 {
> compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
> reg = <0 0x0a6f8800 0 0x400>;
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v3 4/6] arm64: dts: qcom: sm8350: finish reordering nodes
2023-02-09 13:38 [PATCH v3 0/6] arm64: dts: qcom: sm8350: enable GPU on the HDK board Dmitry Baryshkov
` (2 preceding siblings ...)
2023-02-09 13:38 ` [PATCH v3 3/6] arm64: dts: qcom: sm8350: move more nodes to correct place Dmitry Baryshkov
@ 2023-02-09 13:38 ` Dmitry Baryshkov
2023-02-10 11:09 ` Konrad Dybcio
2023-02-09 13:38 ` [PATCH v3 5/6] arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes Dmitry Baryshkov
` (3 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Dmitry Baryshkov @ 2023-02-09 13:38 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul,
Abhinav Kumar, Rob Herring, Krzysztof Kozlowski
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
devicetree, dri-devel, freedreno
Finish reordering DT nodes by their address. Move PDC, tsens, AOSS,
SRAM, SPMI and TLMM nodes to the proper position.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 764 +++++++++++++--------------
1 file changed, 382 insertions(+), 382 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 8bf38d350521..742e9dd17084 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1882,276 +1882,6 @@ compute-cb@3 {
};
};
- pdc: interrupt-controller@b220000 {
- compatible = "qcom,sm8350-pdc", "qcom,pdc";
- reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
- qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
- <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>,
- <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>,
- <156 716 12>;
- #interrupt-cells = <2>;
- interrupt-parent = <&intc>;
- interrupt-controller;
- };
-
- tsens0: thermal-sensor@c263000 {
- compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
- reg = <0 0x0c263000 0 0x1ff>, /* TM */
- <0 0x0c222000 0 0x8>; /* SROT */
- #qcom,sensors = <15>;
- interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "uplow", "critical";
- #thermal-sensor-cells = <1>;
- };
-
- tsens1: thermal-sensor@c265000 {
- compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
- reg = <0 0x0c265000 0 0x1ff>, /* TM */
- <0 0x0c223000 0 0x8>; /* SROT */
- #qcom,sensors = <14>;
- interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "uplow", "critical";
- #thermal-sensor-cells = <1>;
- };
-
- aoss_qmp: power-management@c300000 {
- compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp";
- reg = <0 0x0c300000 0 0x400>;
- interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
- IRQ_TYPE_EDGE_RISING>;
- mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
-
- #clock-cells = <0>;
- };
-
- sram@c3f0000 {
- compatible = "qcom,rpmh-stats";
- reg = <0 0x0c3f0000 0 0x400>;
- };
-
- spmi_bus: spmi@c440000 {
- compatible = "qcom,spmi-pmic-arb";
- reg = <0x0 0x0c440000 0x0 0x1100>,
- <0x0 0x0c600000 0x0 0x2000000>,
- <0x0 0x0e600000 0x0 0x100000>,
- <0x0 0x0e700000 0x0 0xa0000>,
- <0x0 0x0c40a000 0x0 0x26000>;
- reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
- interrupt-names = "periph_irq";
- interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
- qcom,ee = <0>;
- qcom,channel = <0>;
- #address-cells = <2>;
- #size-cells = <0>;
- interrupt-controller;
- #interrupt-cells = <4>;
- };
-
- tlmm: pinctrl@f100000 {
- compatible = "qcom,sm8350-tlmm";
- reg = <0 0x0f100000 0 0x300000>;
- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-ranges = <&tlmm 0 0 204>;
- wakeup-parent = <&pdc>;
-
- sdc2_default_state: sdc2-default-state {
- clk-pins {
- pins = "sdc2_clk";
- drive-strength = <16>;
- bias-disable;
- };
-
- cmd-pins {
- pins = "sdc2_cmd";
- drive-strength = <16>;
- bias-pull-up;
- };
-
- data-pins {
- pins = "sdc2_data";
- drive-strength = <16>;
- bias-pull-up;
- };
- };
-
- sdc2_sleep_state: sdc2-sleep-state {
- clk-pins {
- pins = "sdc2_clk";
- drive-strength = <2>;
- bias-disable;
- };
-
- cmd-pins {
- pins = "sdc2_cmd";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- data-pins {
- pins = "sdc2_data";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- qup_uart3_default_state: qup-uart3-default-state {
- rx-pins {
- pins = "gpio18";
- function = "qup3";
- };
- tx-pins {
- pins = "gpio19";
- function = "qup3";
- };
- };
-
- qup_uart6_default: qup-uart6-default-state {
- pins = "gpio30", "gpio31";
- function = "qup6";
- drive-strength = <2>;
- bias-disable;
- };
-
- qup_uart18_default: qup-uart18-default-state {
- pins = "gpio58", "gpio59";
- function = "qup18";
- drive-strength = <2>;
- bias-disable;
- };
-
- qup_i2c0_default: qup-i2c0-default-state {
- pins = "gpio4", "gpio5";
- function = "qup0";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- qup_i2c1_default: qup-i2c1-default-state {
- pins = "gpio8", "gpio9";
- function = "qup1";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- qup_i2c2_default: qup-i2c2-default-state {
- pins = "gpio12", "gpio13";
- function = "qup2";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- qup_i2c4_default: qup-i2c4-default-state {
- pins = "gpio20", "gpio21";
- function = "qup4";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- qup_i2c5_default: qup-i2c5-default-state {
- pins = "gpio24", "gpio25";
- function = "qup5";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- qup_i2c6_default: qup-i2c6-default-state {
- pins = "gpio28", "gpio29";
- function = "qup6";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- qup_i2c7_default: qup-i2c7-default-state {
- pins = "gpio32", "gpio33";
- function = "qup7";
- drive-strength = <2>;
- bias-disable;
- };
-
- qup_i2c8_default: qup-i2c8-default-state {
- pins = "gpio36", "gpio37";
- function = "qup8";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- qup_i2c9_default: qup-i2c9-default-state {
- pins = "gpio40", "gpio41";
- function = "qup9";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- qup_i2c10_default: qup-i2c10-default-state {
- pins = "gpio44", "gpio45";
- function = "qup10";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- qup_i2c11_default: qup-i2c11-default-state {
- pins = "gpio48", "gpio49";
- function = "qup11";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- qup_i2c12_default: qup-i2c12-default-state {
- pins = "gpio52", "gpio53";
- function = "qup12";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- qup_i2c13_default: qup-i2c13-default-state {
- pins = "gpio0", "gpio1";
- function = "qup13";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- qup_i2c14_default: qup-i2c14-default-state {
- pins = "gpio56", "gpio57";
- function = "qup14";
- drive-strength = <2>;
- bias-disable;
- };
-
- qup_i2c15_default: qup-i2c15-default-state {
- pins = "gpio60", "gpio61";
- function = "qup15";
- drive-strength = <2>;
- bias-disable;
- };
-
- qup_i2c16_default: qup-i2c16-default-state {
- pins = "gpio64", "gpio65";
- function = "qup16";
- drive-strength = <2>;
- bias-disable;
- };
-
- qup_i2c17_default: qup-i2c17-default-state {
- pins = "gpio72", "gpio73";
- function = "qup17";
- drive-strength = <2>;
- bias-disable;
- };
-
- qup_i2c19_default: qup-i2c19-default-state {
- pins = "gpio76", "gpio77";
- function = "qup19";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
sdhc_2: mmc@8804000 {
compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x08804000 0 0x1000>;
@@ -2591,144 +2321,414 @@ mdss_dsi0_out: endpoint {
};
};
- mdss_dsi0_phy: phy@ae94400 {
- compatible = "qcom,sm8350-dsi-phy-5nm";
- reg = <0 0x0ae94400 0 0x200>,
- <0 0x0ae94600 0 0x280>,
- <0 0x0ae94900 0 0x27c>;
- reg-names = "dsi_phy",
- "dsi_phy_lane",
- "dsi_pll";
-
- #clock-cells = <1>;
- #phy-cells = <0>;
+ mdss_dsi0_phy: phy@ae94400 {
+ compatible = "qcom,sm8350-dsi-phy-5nm";
+ reg = <0 0x0ae94400 0 0x200>,
+ <0 0x0ae94600 0 0x280>,
+ <0 0x0ae94900 0 0x27c>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+
+ mdss_dsi1: dsi@ae96000 {
+ compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae96000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <5>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC1_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi1_phy 0>,
+ <&mdss_dsi1_phy 1>;
+
+ operating-points-v2 = <&dsi1_opp_table>;
+ power-domains = <&rpmhpd SM8350_MMCX>;
+
+ phys = <&mdss_dsi1_phy>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ dsi1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /* TODO: opp-187500000 should work with
+ * &rpmhpd_opp_low_svs, but one some of
+ * sm8350_hdk boards reboot using this
+ * opp.
+ */
+ opp-187500000 {
+ opp-hz = /bits/ 64 <187500000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dsi1_in: endpoint {
+ remote-endpoint = <&dpu_intf2_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss_dsi1_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi1_phy: phy@ae96400 {
+ compatible = "qcom,sm8350-dsi-phy-5nm";
+ reg = <0 0x0ae96400 0 0x200>,
+ <0 0x0ae96600 0 0x280>,
+ <0 0x0ae96900 0 0x27c>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+ };
+
+ dispcc: clock-controller@af00000 {
+ compatible = "qcom,sm8350-dispcc";
+ reg = <0 0x0af00000 0 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>,
+ <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>,
+ <0>,
+ <0>;
+ clock-names = "bi_tcxo",
+ "dsi0_phy_pll_out_byteclk",
+ "dsi0_phy_pll_out_dsiclk",
+ "dsi1_phy_pll_out_byteclk",
+ "dsi1_phy_pll_out_dsiclk",
+ "dp_phy_pll_link_clk",
+ "dp_phy_pll_vco_div_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+
+ power-domains = <&rpmhpd SM8350_MMCX>;
+ };
+
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,sm8350-pdc", "qcom,pdc";
+ reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
+ qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
+ <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>,
+ <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>,
+ <156 716 12>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
+ tsens0: thermal-sensor@c263000 {
+ compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c263000 0 0x1ff>, /* TM */
+ <0 0x0c222000 0 0x8>; /* SROT */
+ #qcom,sensors = <15>;
+ interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow", "critical";
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens1: thermal-sensor@c265000 {
+ compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c265000 0 0x1ff>, /* TM */
+ <0 0x0c223000 0 0x8>; /* SROT */
+ #qcom,sensors = <14>;
+ interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow", "critical";
+ #thermal-sensor-cells = <1>;
+ };
+
+ aoss_qmp: power-management@c300000 {
+ compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp";
+ reg = <0 0x0c300000 0 0x400>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ #clock-cells = <0>;
+ };
+
+ sram@c3f0000 {
+ compatible = "qcom,rpmh-stats";
+ reg = <0 0x0c3f0000 0 0x400>;
+ };
+
+ spmi_bus: spmi@c440000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x0 0x0c440000 0x0 0x1100>,
+ <0x0 0x0c600000 0x0 0x2000000>,
+ <0x0 0x0e600000 0x0 0x100000>,
+ <0x0 0x0e700000 0x0 0xa0000>,
+ <0x0 0x0c40a000 0x0 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
+
+ tlmm: pinctrl@f100000 {
+ compatible = "qcom,sm8350-tlmm";
+ reg = <0 0x0f100000 0 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 204>;
+ wakeup-parent = <&pdc>;
+
+ sdc2_default_state: sdc2-default-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_sleep_state: sdc2-sleep-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <2>;
+ bias-disable;
+ };
- clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
- <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "iface", "ref";
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
- status = "disabled";
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
};
- mdss_dsi1: dsi@ae96000 {
- compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
- reg = <0 0x0ae96000 0 0x400>;
- reg-names = "dsi_ctrl";
+ qup_uart3_default_state: qup-uart3-default-state {
+ rx-pins {
+ pins = "gpio18";
+ function = "qup3";
+ };
+ tx-pins {
+ pins = "gpio19";
+ function = "qup3";
+ };
+ };
- interrupt-parent = <&mdss>;
- interrupts = <5>;
+ qup_uart6_default: qup-uart6-default-state {
+ pins = "gpio30", "gpio31";
+ function = "qup6";
+ drive-strength = <2>;
+ bias-disable;
+ };
- clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
- <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
- <&dispcc DISP_CC_MDSS_ESC1_CLK>,
- <&dispcc DISP_CC_MDSS_AHB_CLK>,
- <&gcc GCC_DISP_HF_AXI_CLK>;
- clock-names = "byte",
- "byte_intf",
- "pixel",
- "core",
- "iface",
- "bus";
+ qup_uart18_default: qup-uart18-default-state {
+ pins = "gpio58", "gpio59";
+ function = "qup18";
+ drive-strength = <2>;
+ bias-disable;
+ };
- assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
- assigned-clock-parents = <&mdss_dsi1_phy 0>,
- <&mdss_dsi1_phy 1>;
+ qup_i2c0_default: qup-i2c0-default-state {
+ pins = "gpio4", "gpio5";
+ function = "qup0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
- operating-points-v2 = <&dsi1_opp_table>;
- power-domains = <&rpmhpd SM8350_MMCX>;
+ qup_i2c1_default: qup-i2c1-default-state {
+ pins = "gpio8", "gpio9";
+ function = "qup1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
- phys = <&mdss_dsi1_phy>;
+ qup_i2c2_default: qup-i2c2-default-state {
+ pins = "gpio12", "gpio13";
+ function = "qup2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
- #address-cells = <1>;
- #size-cells = <0>;
+ qup_i2c4_default: qup-i2c4-default-state {
+ pins = "gpio20", "gpio21";
+ function = "qup4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
- status = "disabled";
+ qup_i2c5_default: qup-i2c5-default-state {
+ pins = "gpio24", "gpio25";
+ function = "qup5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
- dsi1_opp_table: opp-table {
- compatible = "operating-points-v2";
+ qup_i2c6_default: qup-i2c6-default-state {
+ pins = "gpio28", "gpio29";
+ function = "qup6";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
- /* TODO: opp-187500000 should work with
- * &rpmhpd_opp_low_svs, but one some of
- * sm8350_hdk boards reboot using this
- * opp.
- */
- opp-187500000 {
- opp-hz = /bits/ 64 <187500000>;
- required-opps = <&rpmhpd_opp_svs>;
- };
+ qup_i2c7_default: qup-i2c7-default-state {
+ pins = "gpio32", "gpio33";
+ function = "qup7";
+ drive-strength = <2>;
+ bias-disable;
+ };
- opp-300000000 {
- opp-hz = /bits/ 64 <300000000>;
- required-opps = <&rpmhpd_opp_svs>;
- };
+ qup_i2c8_default: qup-i2c8-default-state {
+ pins = "gpio36", "gpio37";
+ function = "qup8";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
- opp-358000000 {
- opp-hz = /bits/ 64 <358000000>;
- required-opps = <&rpmhpd_opp_svs_l1>;
- };
- };
+ qup_i2c9_default: qup-i2c9-default-state {
+ pins = "gpio40", "gpio41";
+ function = "qup9";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
+ qup_i2c10_default: qup-i2c10-default-state {
+ pins = "gpio44", "gpio45";
+ function = "qup10";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
- port@0 {
- reg = <0>;
- mdss_dsi1_in: endpoint {
- remote-endpoint = <&dpu_intf2_out>;
- };
- };
+ qup_i2c11_default: qup-i2c11-default-state {
+ pins = "gpio48", "gpio49";
+ function = "qup11";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
- port@1 {
- reg = <1>;
- mdss_dsi1_out: endpoint {
- };
- };
- };
+ qup_i2c12_default: qup-i2c12-default-state {
+ pins = "gpio52", "gpio53";
+ function = "qup12";
+ drive-strength = <2>;
+ bias-pull-up;
};
- mdss_dsi1_phy: phy@ae96400 {
- compatible = "qcom,sm8350-dsi-phy-5nm";
- reg = <0 0x0ae96400 0 0x200>,
- <0 0x0ae96600 0 0x280>,
- <0 0x0ae96900 0 0x27c>;
- reg-names = "dsi_phy",
- "dsi_phy_lane",
- "dsi_pll";
+ qup_i2c13_default: qup-i2c13-default-state {
+ pins = "gpio0", "gpio1";
+ function = "qup13";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
- #clock-cells = <1>;
- #phy-cells = <0>;
+ qup_i2c14_default: qup-i2c14-default-state {
+ pins = "gpio56", "gpio57";
+ function = "qup14";
+ drive-strength = <2>;
+ bias-disable;
+ };
- clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
- <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "iface", "ref";
+ qup_i2c15_default: qup-i2c15-default-state {
+ pins = "gpio60", "gpio61";
+ function = "qup15";
+ drive-strength = <2>;
+ bias-disable;
+ };
- status = "disabled";
+ qup_i2c16_default: qup-i2c16-default-state {
+ pins = "gpio64", "gpio65";
+ function = "qup16";
+ drive-strength = <2>;
+ bias-disable;
};
- };
- dispcc: clock-controller@af00000 {
- compatible = "qcom,sm8350-dispcc";
- reg = <0 0x0af00000 0 0x10000>;
- clocks = <&rpmhcc RPMH_CXO_CLK>,
- <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>,
- <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>,
- <0>,
- <0>;
- clock-names = "bi_tcxo",
- "dsi0_phy_pll_out_byteclk",
- "dsi0_phy_pll_out_dsiclk",
- "dsi1_phy_pll_out_byteclk",
- "dsi1_phy_pll_out_dsiclk",
- "dp_phy_pll_link_clk",
- "dp_phy_pll_vco_div_clk";
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
+ qup_i2c17_default: qup-i2c17-default-state {
+ pins = "gpio72", "gpio73";
+ function = "qup17";
+ drive-strength = <2>;
+ bias-disable;
+ };
- power-domains = <&rpmhpd SM8350_MMCX>;
+ qup_i2c19_default: qup-i2c19-default-state {
+ pins = "gpio76", "gpio77";
+ function = "qup19";
+ drive-strength = <2>;
+ bias-disable;
+ };
};
apps_smmu: iommu@15000000 {
--
2.39.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v3 4/6] arm64: dts: qcom: sm8350: finish reordering nodes
2023-02-09 13:38 ` [PATCH v3 4/6] arm64: dts: qcom: sm8350: finish reordering nodes Dmitry Baryshkov
@ 2023-02-10 11:09 ` Konrad Dybcio
2023-02-10 11:12 ` Dmitry Baryshkov
0 siblings, 1 reply; 17+ messages in thread
From: Konrad Dybcio @ 2023-02-10 11:09 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Rob Clark,
Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
devicetree, dri-devel, freedreno
On 9.02.2023 14:38, Dmitry Baryshkov wrote:
> Finish reordering DT nodes by their address. Move PDC, tsens, AOSS,
> SRAM, SPMI and TLMM nodes to the proper position.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
[...]
> + phys = <&mdss_dsi1_phy>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + dsi1_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + /* TODO: opp-187500000 should work with
> + * &rpmhpd_opp_low_svs, but one some of
> + * sm8350_hdk boards reboot using this
> + * opp.
> + */
It's not a part of this patch, but an idea came into my
head.. could you check with socid that your HDK has an
8350v2.1?
As for the patch itself.. I *think* I don't see anything
wrong..
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> + opp-187500000 {
> + opp-hz = /bits/ 64 <187500000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-358000000 {
> + opp-hz = /bits/ 64 <358000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> + };
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + mdss_dsi1_in: endpoint {
> + remote-endpoint = <&dpu_intf2_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + mdss_dsi1_out: endpoint {
> + };
> + };
> + };
> + };
> +
> + mdss_dsi1_phy: phy@ae96400 {
> + compatible = "qcom,sm8350-dsi-phy-5nm";
> + reg = <0 0x0ae96400 0 0x200>,
> + <0 0x0ae96600 0 0x280>,
> + <0 0x0ae96900 0 0x27c>;
> + reg-names = "dsi_phy",
> + "dsi_phy_lane",
> + "dsi_pll";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface", "ref";
> +
> + status = "disabled";
> + };
> + };
> +
> + dispcc: clock-controller@af00000 {
> + compatible = "qcom,sm8350-dispcc";
> + reg = <0 0x0af00000 0 0x10000>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>,
> + <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>,
> + <0>,
> + <0>;
> + clock-names = "bi_tcxo",
> + "dsi0_phy_pll_out_byteclk",
> + "dsi0_phy_pll_out_dsiclk",
> + "dsi1_phy_pll_out_byteclk",
> + "dsi1_phy_pll_out_dsiclk",
> + "dp_phy_pll_link_clk",
> + "dp_phy_pll_vco_div_clk";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> +
> + power-domains = <&rpmhpd SM8350_MMCX>;
> + };
> +
> + pdc: interrupt-controller@b220000 {
> + compatible = "qcom,sm8350-pdc", "qcom,pdc";
> + reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
> + qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
> + <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>,
> + <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>,
> + <156 716 12>;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&intc>;
> + interrupt-controller;
> + };
> +
> + tsens0: thermal-sensor@c263000 {
> + compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
> + reg = <0 0x0c263000 0 0x1ff>, /* TM */
> + <0 0x0c222000 0 0x8>; /* SROT */
> + #qcom,sensors = <15>;
> + interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
> + <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "uplow", "critical";
> + #thermal-sensor-cells = <1>;
> + };
> +
> + tsens1: thermal-sensor@c265000 {
> + compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
> + reg = <0 0x0c265000 0 0x1ff>, /* TM */
> + <0 0x0c223000 0 0x8>; /* SROT */
> + #qcom,sensors = <14>;
> + interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
> + <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "uplow", "critical";
> + #thermal-sensor-cells = <1>;
> + };
> +
> + aoss_qmp: power-management@c300000 {
> + compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp";
> + reg = <0 0x0c300000 0 0x400>;
> + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
> + IRQ_TYPE_EDGE_RISING>;
> + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
> +
> + #clock-cells = <0>;
> + };
> +
> + sram@c3f0000 {
> + compatible = "qcom,rpmh-stats";
> + reg = <0 0x0c3f0000 0 0x400>;
> + };
> +
> + spmi_bus: spmi@c440000 {
> + compatible = "qcom,spmi-pmic-arb";
> + reg = <0x0 0x0c440000 0x0 0x1100>,
> + <0x0 0x0c600000 0x0 0x2000000>,
> + <0x0 0x0e600000 0x0 0x100000>,
> + <0x0 0x0e700000 0x0 0xa0000>,
> + <0x0 0x0c40a000 0x0 0x26000>;
> + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
> + interrupt-names = "periph_irq";
> + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
> + qcom,ee = <0>;
> + qcom,channel = <0>;
> + #address-cells = <2>;
> + #size-cells = <0>;
> + interrupt-controller;
> + #interrupt-cells = <4>;
> + };
> +
> + tlmm: pinctrl@f100000 {
> + compatible = "qcom,sm8350-tlmm";
> + reg = <0 0x0f100000 0 0x300000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-ranges = <&tlmm 0 0 204>;
> + wakeup-parent = <&pdc>;
> +
> + sdc2_default_state: sdc2-default-state {
> + clk-pins {
> + pins = "sdc2_clk";
> + drive-strength = <16>;
> + bias-disable;
> + };
> +
> + cmd-pins {
> + pins = "sdc2_cmd";
> + drive-strength = <16>;
> + bias-pull-up;
> + };
> +
> + data-pins {
> + pins = "sdc2_data";
> + drive-strength = <16>;
> + bias-pull-up;
> + };
> + };
> +
> + sdc2_sleep_state: sdc2-sleep-state {
> + clk-pins {
> + pins = "sdc2_clk";
> + drive-strength = <2>;
> + bias-disable;
> + };
>
> - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> - <&rpmhcc RPMH_CXO_CLK>;
> - clock-names = "iface", "ref";
> + cmd-pins {
> + pins = "sdc2_cmd";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
>
> - status = "disabled";
> + data-pins {
> + pins = "sdc2_data";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> };
>
> - mdss_dsi1: dsi@ae96000 {
> - compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
> - reg = <0 0x0ae96000 0 0x400>;
> - reg-names = "dsi_ctrl";
> + qup_uart3_default_state: qup-uart3-default-state {
> + rx-pins {
> + pins = "gpio18";
> + function = "qup3";
> + };
> + tx-pins {
> + pins = "gpio19";
> + function = "qup3";
> + };
> + };
>
> - interrupt-parent = <&mdss>;
> - interrupts = <5>;
> + qup_uart6_default: qup-uart6-default-state {
> + pins = "gpio30", "gpio31";
> + function = "qup6";
> + drive-strength = <2>;
> + bias-disable;
> + };
>
> - clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
> - <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
> - <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
> - <&dispcc DISP_CC_MDSS_ESC1_CLK>,
> - <&dispcc DISP_CC_MDSS_AHB_CLK>,
> - <&gcc GCC_DISP_HF_AXI_CLK>;
> - clock-names = "byte",
> - "byte_intf",
> - "pixel",
> - "core",
> - "iface",
> - "bus";
> + qup_uart18_default: qup-uart18-default-state {
> + pins = "gpio58", "gpio59";
> + function = "qup18";
> + drive-strength = <2>;
> + bias-disable;
> + };
>
> - assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
> - <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
> - assigned-clock-parents = <&mdss_dsi1_phy 0>,
> - <&mdss_dsi1_phy 1>;
> + qup_i2c0_default: qup-i2c0-default-state {
> + pins = "gpio4", "gpio5";
> + function = "qup0";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
>
> - operating-points-v2 = <&dsi1_opp_table>;
> - power-domains = <&rpmhpd SM8350_MMCX>;
> + qup_i2c1_default: qup-i2c1-default-state {
> + pins = "gpio8", "gpio9";
> + function = "qup1";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
>
> - phys = <&mdss_dsi1_phy>;
> + qup_i2c2_default: qup-i2c2-default-state {
> + pins = "gpio12", "gpio13";
> + function = "qup2";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
>
> - #address-cells = <1>;
> - #size-cells = <0>;
> + qup_i2c4_default: qup-i2c4-default-state {
> + pins = "gpio20", "gpio21";
> + function = "qup4";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
>
> - status = "disabled";
> + qup_i2c5_default: qup-i2c5-default-state {
> + pins = "gpio24", "gpio25";
> + function = "qup5";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
>
> - dsi1_opp_table: opp-table {
> - compatible = "operating-points-v2";
> + qup_i2c6_default: qup-i2c6-default-state {
> + pins = "gpio28", "gpio29";
> + function = "qup6";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
>
> - /* TODO: opp-187500000 should work with
> - * &rpmhpd_opp_low_svs, but one some of
> - * sm8350_hdk boards reboot using this
> - * opp.
> - */
> - opp-187500000 {
> - opp-hz = /bits/ 64 <187500000>;
> - required-opps = <&rpmhpd_opp_svs>;
> - };
> + qup_i2c7_default: qup-i2c7-default-state {
> + pins = "gpio32", "gpio33";
> + function = "qup7";
> + drive-strength = <2>;
> + bias-disable;
> + };
>
> - opp-300000000 {
> - opp-hz = /bits/ 64 <300000000>;
> - required-opps = <&rpmhpd_opp_svs>;
> - };
> + qup_i2c8_default: qup-i2c8-default-state {
> + pins = "gpio36", "gpio37";
> + function = "qup8";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
>
> - opp-358000000 {
> - opp-hz = /bits/ 64 <358000000>;
> - required-opps = <&rpmhpd_opp_svs_l1>;
> - };
> - };
> + qup_i2c9_default: qup-i2c9-default-state {
> + pins = "gpio40", "gpio41";
> + function = "qup9";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
>
> - ports {
> - #address-cells = <1>;
> - #size-cells = <0>;
> + qup_i2c10_default: qup-i2c10-default-state {
> + pins = "gpio44", "gpio45";
> + function = "qup10";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
>
> - port@0 {
> - reg = <0>;
> - mdss_dsi1_in: endpoint {
> - remote-endpoint = <&dpu_intf2_out>;
> - };
> - };
> + qup_i2c11_default: qup-i2c11-default-state {
> + pins = "gpio48", "gpio49";
> + function = "qup11";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
>
> - port@1 {
> - reg = <1>;
> - mdss_dsi1_out: endpoint {
> - };
> - };
> - };
> + qup_i2c12_default: qup-i2c12-default-state {
> + pins = "gpio52", "gpio53";
> + function = "qup12";
> + drive-strength = <2>;
> + bias-pull-up;
> };
>
> - mdss_dsi1_phy: phy@ae96400 {
> - compatible = "qcom,sm8350-dsi-phy-5nm";
> - reg = <0 0x0ae96400 0 0x200>,
> - <0 0x0ae96600 0 0x280>,
> - <0 0x0ae96900 0 0x27c>;
> - reg-names = "dsi_phy",
> - "dsi_phy_lane",
> - "dsi_pll";
> + qup_i2c13_default: qup-i2c13-default-state {
> + pins = "gpio0", "gpio1";
> + function = "qup13";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
>
> - #clock-cells = <1>;
> - #phy-cells = <0>;
> + qup_i2c14_default: qup-i2c14-default-state {
> + pins = "gpio56", "gpio57";
> + function = "qup14";
> + drive-strength = <2>;
> + bias-disable;
> + };
>
> - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> - <&rpmhcc RPMH_CXO_CLK>;
> - clock-names = "iface", "ref";
> + qup_i2c15_default: qup-i2c15-default-state {
> + pins = "gpio60", "gpio61";
> + function = "qup15";
> + drive-strength = <2>;
> + bias-disable;
> + };
>
> - status = "disabled";
> + qup_i2c16_default: qup-i2c16-default-state {
> + pins = "gpio64", "gpio65";
> + function = "qup16";
> + drive-strength = <2>;
> + bias-disable;
> };
> - };
>
> - dispcc: clock-controller@af00000 {
> - compatible = "qcom,sm8350-dispcc";
> - reg = <0 0x0af00000 0 0x10000>;
> - clocks = <&rpmhcc RPMH_CXO_CLK>,
> - <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>,
> - <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>,
> - <0>,
> - <0>;
> - clock-names = "bi_tcxo",
> - "dsi0_phy_pll_out_byteclk",
> - "dsi0_phy_pll_out_dsiclk",
> - "dsi1_phy_pll_out_byteclk",
> - "dsi1_phy_pll_out_dsiclk",
> - "dp_phy_pll_link_clk",
> - "dp_phy_pll_vco_div_clk";
> - #clock-cells = <1>;
> - #reset-cells = <1>;
> - #power-domain-cells = <1>;
> + qup_i2c17_default: qup-i2c17-default-state {
> + pins = "gpio72", "gpio73";
> + function = "qup17";
> + drive-strength = <2>;
> + bias-disable;
> + };
>
> - power-domains = <&rpmhpd SM8350_MMCX>;
> + qup_i2c19_default: qup-i2c19-default-state {
> + pins = "gpio76", "gpio77";
> + function = "qup19";
> + drive-strength = <2>;
> + bias-disable;
> + };
> };
>
> apps_smmu: iommu@15000000 {
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v3 4/6] arm64: dts: qcom: sm8350: finish reordering nodes
2023-02-10 11:09 ` Konrad Dybcio
@ 2023-02-10 11:12 ` Dmitry Baryshkov
2023-02-10 11:13 ` Konrad Dybcio
0 siblings, 1 reply; 17+ messages in thread
From: Dmitry Baryshkov @ 2023-02-10 11:12 UTC (permalink / raw)
To: Konrad Dybcio, Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul,
Abhinav Kumar, Rob Herring, Krzysztof Kozlowski
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
devicetree, dri-devel, freedreno
On 10/02/2023 13:09, Konrad Dybcio wrote:
>
>
> On 9.02.2023 14:38, Dmitry Baryshkov wrote:
>> Finish reordering DT nodes by their address. Move PDC, tsens, AOSS,
>> SRAM, SPMI and TLMM nodes to the proper position.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
> [...]
>
>> + phys = <&mdss_dsi1_phy>;
>> +
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + status = "disabled";
>> +
>> + dsi1_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + /* TODO: opp-187500000 should work with
>> + * &rpmhpd_opp_low_svs, but one some of
>> + * sm8350_hdk boards reboot using this
>> + * opp.
>> + */
> It's not a part of this patch, but an idea came into my
> head.. could you check with socid that your HDK has an
> 8350v2.1?
I checked with the bootloader instead, if you don't mind:
Platform Init [ 2701] BDS
UEFI Ver : 6.0.210914.BOOT.MXF.1.0-00848-LAHAINA-1
Platform : HDK
Subtype : 0
Boot Device : UFS
Chip Name : SMP_LAHAINA
Chip Ver : 2.1
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v3 4/6] arm64: dts: qcom: sm8350: finish reordering nodes
2023-02-10 11:12 ` Dmitry Baryshkov
@ 2023-02-10 11:13 ` Konrad Dybcio
0 siblings, 0 replies; 17+ messages in thread
From: Konrad Dybcio @ 2023-02-10 11:13 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Rob Clark,
Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
devicetree, dri-devel, freedreno
On 10.02.2023 12:12, Dmitry Baryshkov wrote:
> On 10/02/2023 13:09, Konrad Dybcio wrote:
>>
>>
>> On 9.02.2023 14:38, Dmitry Baryshkov wrote:
>>> Finish reordering DT nodes by their address. Move PDC, tsens, AOSS,
>>> SRAM, SPMI and TLMM nodes to the proper position.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>> [...]
>>
>>> + phys = <&mdss_dsi1_phy>;
>>> +
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + status = "disabled";
>>> +
>>> + dsi1_opp_table: opp-table {
>>> + compatible = "operating-points-v2";
>>> +
>>> + /* TODO: opp-187500000 should work with
>>> + * &rpmhpd_opp_low_svs, but one some of
>>> + * sm8350_hdk boards reboot using this
>>> + * opp.
>>> + */
>> It's not a part of this patch, but an idea came into my
>> head.. could you check with socid that your HDK has an
>> 8350v2.1?
>
> I checked with the bootloader instead, if you don't mind:
>
> Platform Init [ 2701] BDS
> UEFI Ver : 6.0.210914.BOOT.MXF.1.0-00848-LAHAINA-1
> Platform : HDK
> Subtype : 0
> Boot Device : UFS
> Chip Name : SMP_LAHAINA
> Chip Ver : 2.1
Hm okay, perhaps it was something else..
Konrad
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v3 5/6] arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes
2023-02-09 13:38 [PATCH v3 0/6] arm64: dts: qcom: sm8350: enable GPU on the HDK board Dmitry Baryshkov
` (3 preceding siblings ...)
2023-02-09 13:38 ` [PATCH v3 4/6] arm64: dts: qcom: sm8350: finish reordering nodes Dmitry Baryshkov
@ 2023-02-09 13:38 ` Dmitry Baryshkov
2023-02-10 11:10 ` Konrad Dybcio
2023-02-09 13:38 ` [PATCH v3 6/6] arm64: dts: qcom: sm8350-hdk: enable GPU Dmitry Baryshkov
` (2 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Dmitry Baryshkov @ 2023-02-09 13:38 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul,
Abhinav Kumar, Rob Herring, Krzysztof Kozlowski
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
devicetree, dri-devel, freedreno
Add device nodes required to enable GPU on the SM8350 platform.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 178 +++++++++++++++++++++++++++
1 file changed, 178 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 742e9dd17084..4c1a2f814b5c 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,dispcc-sm8350.h>
#include <dt-bindings/clock/qcom,gcc-sm8350.h>
+#include <dt-bindings/clock/qcom,gpucc-sm8350.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/gpio/gpio.h>
@@ -1765,6 +1766,183 @@ tcsr_mutex: hwlock@1f40000 {
#hwlock-cells = <1>;
};
+ gpu: gpu@3d00000 {
+ compatible = "qcom,adreno-660.1", "qcom,adreno";
+
+ reg = <0 0x03d00000 0 0x40000>,
+ <0 0x03d9e000 0 0x1000>,
+ <0 0x03d61000 0 0x800>;
+ reg-names = "kgsl_3d0_reg_memory",
+ "cx_mem",
+ "cx_dbgc";
+
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>;
+
+ operating-points-v2 = <&gpu_opp_table>;
+
+ qcom,gmu = <&gmu>;
+
+ status = "disabled";
+
+ zap-shader {
+ memory-region = <&pil_gpu_mem>;
+ };
+
+ /* note: downstream checks gpu binning for 670 Mhz */
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-840000000 {
+ opp-hz = /bits/ 64 <840000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+
+ opp-778000000 {
+ opp-hz = /bits/ 64 <778000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ opp-738000000 {
+ opp-hz = /bits/ 64 <738000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ opp-676000000 {
+ opp-hz = /bits/ 64 <676000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ opp-608000000 {
+ opp-hz = /bits/ 64 <608000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ opp-491000000 {
+ opp-hz = /bits/ 64 <491000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+ };
+
+ opp-443000000 {
+ opp-hz = /bits/ 64 <443000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ opp-379000000 {
+ opp-hz = /bits/ 64 <379000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+ };
+
+ opp-315000000 {
+ opp-hz = /bits/ 64 <315000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+ };
+ };
+
+ gmu: gmu@3d6a000 {
+ compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu";
+
+ reg = <0 0x03d6a000 0 0x34000>,
+ <0 0x03de0000 0 0x10000>,
+ <0 0x0b290000 0 0x10000>;
+ reg-names = "gmu", "rscc", "gmu_pdc";
+
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+ clock-names = "gmu",
+ "cxo",
+ "axi",
+ "memnoc",
+ "ahb",
+ "hub",
+ "smmu_vote";
+
+ power-domains = <&gpucc GPU_CX_GDSC>,
+ <&gpucc GPU_GX_GDSC>;
+ power-domain-names = "cx",
+ "gx";
+
+ iommus = <&adreno_smmu 5 0x400>;
+
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+ };
+ };
+
+ gpucc: clock-controller@3d90000 {
+ compatible = "qcom,sm8350-gpucc";
+ reg = <0 0x03d90000 0 0x9000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+ clock-names = "bi_tcxo",
+ "gcc_gpu_gpll0_clk_src",
+ "gcc_gpu_gpll0_div_clk_src";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ adreno_smmu: iommu@3da0000 {
+ compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
+ reg = <0 0x03da0000 0 0x20000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_HUB_AON_CLK>;
+ clock-names = "bus",
+ "iface",
+ "ahb",
+ "hlos1_vote_gpu_smmu",
+ "cx_gmu",
+ "hub_cx_int",
+ "hub_aon";
+
+ power-domains = <&gpucc GPU_CX_GDSC>;
+ dma-coherent;
+ };
+
lpass_ag_noc: interconnect@3c40000 {
compatible = "qcom,sm8350-lpass-ag-noc";
reg = <0 0x03c40000 0 0xf080>;
--
2.39.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v3 5/6] arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes
2023-02-09 13:38 ` [PATCH v3 5/6] arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes Dmitry Baryshkov
@ 2023-02-10 11:10 ` Konrad Dybcio
2023-02-10 11:14 ` Dmitry Baryshkov
0 siblings, 1 reply; 17+ messages in thread
From: Konrad Dybcio @ 2023-02-10 11:10 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Rob Clark,
Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
devicetree, dri-devel, freedreno
On 9.02.2023 14:38, Dmitry Baryshkov wrote:
> Add device nodes required to enable GPU on the SM8350 platform.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 178 +++++++++++++++++++++++++++
> 1 file changed, 178 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index 742e9dd17084..4c1a2f814b5c 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -7,6 +7,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
> #include <dt-bindings/clock/qcom,gcc-sm8350.h>
> +#include <dt-bindings/clock/qcom,gpucc-sm8350.h>
> #include <dt-bindings/clock/qcom,rpmh.h>
> #include <dt-bindings/dma/qcom-gpi.h>
> #include <dt-bindings/gpio/gpio.h>
> @@ -1765,6 +1766,183 @@ tcsr_mutex: hwlock@1f40000 {
> #hwlock-cells = <1>;
> };
>
> + gpu: gpu@3d00000 {
> + compatible = "qcom,adreno-660.1", "qcom,adreno";
> +
The newlines between compatible and reg trigger my OCD..
But the patch looks good!
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
P.S I can add binning after the big GMUless series lands..
And maybe I should also rework the binning code a bit to
be cleaner..
> + reg = <0 0x03d00000 0 0x40000>,
> + <0 0x03d9e000 0 0x1000>,
> + <0 0x03d61000 0 0x800>;
> + reg-names = "kgsl_3d0_reg_memory",
> + "cx_mem",
> + "cx_dbgc";
> +
> + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> +
> + iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>;
> +
> + operating-points-v2 = <&gpu_opp_table>;
> +
> + qcom,gmu = <&gmu>;
> +
> + status = "disabled";
> +
> + zap-shader {
> + memory-region = <&pil_gpu_mem>;
> + };
> +
> + /* note: downstream checks gpu binning for 670 Mhz */
> + gpu_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-840000000 {
> + opp-hz = /bits/ 64 <840000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> + };
> +
> + opp-778000000 {
> + opp-hz = /bits/ 64 <778000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> + };
> +
> + opp-738000000 {
> + opp-hz = /bits/ 64 <738000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> + };
> +
> + opp-676000000 {
> + opp-hz = /bits/ 64 <676000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> + };
> +
> + opp-608000000 {
> + opp-hz = /bits/ 64 <608000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
> + };
> +
> + opp-540000000 {
> + opp-hz = /bits/ 64 <540000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> + };
> +
> + opp-491000000 {
> + opp-hz = /bits/ 64 <491000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
> + };
> +
> + opp-443000000 {
> + opp-hz = /bits/ 64 <443000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> + };
> +
> + opp-379000000 {
> + opp-hz = /bits/ 64 <379000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
> + };
> +
> + opp-315000000 {
> + opp-hz = /bits/ 64 <315000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> + };
> + };
> + };
> +
> + gmu: gmu@3d6a000 {
> + compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu";
> +
> + reg = <0 0x03d6a000 0 0x34000>,
> + <0 0x03de0000 0 0x10000>,
> + <0 0x0b290000 0 0x10000>;
> + reg-names = "gmu", "rscc", "gmu_pdc";
> +
> + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hfi", "gmu";
> +
> + clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
> + <&gpucc GPU_CC_CXO_CLK>,
> + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> + <&gpucc GPU_CC_AHB_CLK>,
> + <&gpucc GPU_CC_HUB_CX_INT_CLK>,
> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
> + clock-names = "gmu",
> + "cxo",
> + "axi",
> + "memnoc",
> + "ahb",
> + "hub",
> + "smmu_vote";
> +
> + power-domains = <&gpucc GPU_CX_GDSC>,
> + <&gpucc GPU_GX_GDSC>;
> + power-domain-names = "cx",
> + "gx";
> +
> + iommus = <&adreno_smmu 5 0x400>;
> +
> + operating-points-v2 = <&gmu_opp_table>;
> +
> + gmu_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-200000000 {
> + opp-hz = /bits/ 64 <200000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> + };
> + };
> + };
> +
> + gpucc: clock-controller@3d90000 {
> + compatible = "qcom,sm8350-gpucc";
> + reg = <0 0x03d90000 0 0x9000>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_GPU_GPLL0_CLK_SRC>,
> + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
> + clock-names = "bi_tcxo",
> + "gcc_gpu_gpll0_clk_src",
> + "gcc_gpu_gpll0_div_clk_src";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> + adreno_smmu: iommu@3da0000 {
> + compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
> + reg = <0 0x03da0000 0 0x20000>;
> + #iommu-cells = <2>;
> + #global-interrupts = <2>;
> + interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
> + <&gpucc GPU_CC_AHB_CLK>,
> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
> + <&gpucc GPU_CC_CX_GMU_CLK>,
> + <&gpucc GPU_CC_HUB_CX_INT_CLK>,
> + <&gpucc GPU_CC_HUB_AON_CLK>;
> + clock-names = "bus",
> + "iface",
> + "ahb",
> + "hlos1_vote_gpu_smmu",
> + "cx_gmu",
> + "hub_cx_int",
> + "hub_aon";
> +
> + power-domains = <&gpucc GPU_CX_GDSC>;
> + dma-coherent;
> + };
> +
> lpass_ag_noc: interconnect@3c40000 {
> compatible = "qcom,sm8350-lpass-ag-noc";
> reg = <0 0x03c40000 0 0xf080>;
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v3 5/6] arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes
2023-02-10 11:10 ` Konrad Dybcio
@ 2023-02-10 11:14 ` Dmitry Baryshkov
0 siblings, 0 replies; 17+ messages in thread
From: Dmitry Baryshkov @ 2023-02-10 11:14 UTC (permalink / raw)
To: Konrad Dybcio, Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul,
Abhinav Kumar, Rob Herring, Krzysztof Kozlowski
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
devicetree, dri-devel, freedreno
On 10/02/2023 13:10, Konrad Dybcio wrote:
>
>
> On 9.02.2023 14:38, Dmitry Baryshkov wrote:
>> Add device nodes required to enable GPU on the SM8350 platform.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>> arch/arm64/boot/dts/qcom/sm8350.dtsi | 178 +++++++++++++++++++++++++++
>> 1 file changed, 178 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
>> index 742e9dd17084..4c1a2f814b5c 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
>> @@ -7,6 +7,7 @@
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
>> #include <dt-bindings/clock/qcom,gcc-sm8350.h>
>> +#include <dt-bindings/clock/qcom,gpucc-sm8350.h>
>> #include <dt-bindings/clock/qcom,rpmh.h>
>> #include <dt-bindings/dma/qcom-gpi.h>
>> #include <dt-bindings/gpio/gpio.h>
>> @@ -1765,6 +1766,183 @@ tcsr_mutex: hwlock@1f40000 {
>> #hwlock-cells = <1>;
>> };
>>
>> + gpu: gpu@3d00000 {
>> + compatible = "qcom,adreno-660.1", "qcom,adreno";
>> +
> The newlines between compatible and reg trigger my OCD..
>
> But the patch looks good!
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>
> Konrad
>
> P.S I can add binning after the big GMUless series lands..
> And maybe I should also rework the binning code a bit to
> be cleaner..
Good! I didn't see (or maybe I didn't notice binning for v2.1), so I
skipped it.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v3 6/6] arm64: dts: qcom: sm8350-hdk: enable GPU
2023-02-09 13:38 [PATCH v3 0/6] arm64: dts: qcom: sm8350: enable GPU on the HDK board Dmitry Baryshkov
` (4 preceding siblings ...)
2023-02-09 13:38 ` [PATCH v3 5/6] arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes Dmitry Baryshkov
@ 2023-02-09 13:38 ` Dmitry Baryshkov
2023-02-10 8:29 ` [PATCH v3 0/6] arm64: dts: qcom: sm8350: enable GPU on the HDK board Neil Armstrong
2023-02-13 22:23 ` Bjorn Andersson
7 siblings, 0 replies; 17+ messages in thread
From: Dmitry Baryshkov @ 2023-02-09 13:38 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul,
Abhinav Kumar, Rob Herring, Krzysztof Kozlowski
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
devicetree, dri-devel, freedreno
Enable the GPU on the SM8350-HDK device. The ZAP shader is required for
the GPU to function properly.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index 54654eb75c28..09baf6959c71 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -284,6 +284,14 @@ &gpi_dma1 {
status = "okay";
};
+&gpu {
+ status = "okay";
+
+ zap-shader {
+ firmware-name = "qcom/sm8350/a660_zap.mbn";
+ };
+};
+
&i2c15 {
clock-frequency = <400000>;
status = "okay";
--
2.39.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v3 0/6] arm64: dts: qcom: sm8350: enable GPU on the HDK board
2023-02-09 13:38 [PATCH v3 0/6] arm64: dts: qcom: sm8350: enable GPU on the HDK board Dmitry Baryshkov
` (5 preceding siblings ...)
2023-02-09 13:38 ` [PATCH v3 6/6] arm64: dts: qcom: sm8350-hdk: enable GPU Dmitry Baryshkov
@ 2023-02-10 8:29 ` Neil Armstrong
2023-02-10 10:32 ` Dmitry Baryshkov
2023-02-13 22:23 ` Bjorn Andersson
7 siblings, 1 reply; 17+ messages in thread
From: Neil Armstrong @ 2023-02-10 8:29 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring,
Krzysztof Kozlowski
Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm,
devicetree, dri-devel, freedreno
On 09/02/2023 14:38, Dmitry Baryshkov wrote:
> Add A660 device to the Qualcomm SM8350 platform and enable it for the
> sm8350-hdk board. Unfortunately while adding the GPU & related devices I
> noticed that DT nodes on SM8350 are greatly out of the adress sorting
> order, so patches 2-4 reorder DT nodes to follow the agreement.
>
> Changes since v1:
> - Dropped merged patches
> - Expanded commit messages to mention the sort order (by the node
> address)
> - Rebased on top of latest Bjorn's tree
Can you specify which tree and commit ?
I tried next-20230207, next-20230208 & next-20230209 and patch 2 doesn't apply.
On the 3 trees I have:
d7133d6d25fb arm64: dts: qcom: sm8350: use qcom,sm8350-dsi-ctrl compatibles
b904227a4b69 arm64: dts: qcom: sm8350: Hook up DSI1 to MDP
2a07efb8c086 arm64: dts: qcom: sm8350: Add mdss_ prefix to DSIn out labels
e3e654ced376 arm64: dts: qcom: sm8350: Fix DSI PLL size
45cd807de143 arm64: dts: qcom: sm8350: Fix DSI PHY compatibles
0af6a4012b38 arm64: dts: qcom: sm8350: Feed DSI1 PHY clocks to DISPCC
1eed7995d9da arm64: dts: qcom: sm8350: Fix DSI1 interrupt
6636818ecf0f arm64: dts: qcom: sm8350: Add missing #address/size-cells to DSIn
f3c08ae6fea7 arm64: dts: qcom: sm8350: Pad addresses to 8 hex digits
1ccad21aa996 Merge tag 'qcom-arm64-fixes-for-6.2' into arm64-for-6.3
...
Can you use --base in format-patch (or use b4 prep !) ?
Thanks,
Neil
>
> Changes since v1:
> - Fixed the subject and commit message for patch 1
> - Fixed GMU's clocks to follow the vendor kernel
> - Marked Adreno SMMU as dma-coherent
> - Dropped comments targeting sm8350 v1, we do not support that chip
> revision.
>
> Dmitry Baryshkov (6):
> dt-bindings: display/msm/gmu: add Adreno 660 support
> arm64: dts: qcom: sm8350: reorder device nodes
> arm64: dts: qcom: sm8350: move more nodes to correct place
> arm64: dts: qcom: sm8350: finish reordering nodes
> arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes
> arm64: dts: qcom: sm8350-hdk: enable GPU
>
> .../devicetree/bindings/display/msm/gmu.yaml | 1 +
> arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 8 +
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 2512 +++++++++--------
> 3 files changed, 1354 insertions(+), 1167 deletions(-)
>
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v3 0/6] arm64: dts: qcom: sm8350: enable GPU on the HDK board
2023-02-10 8:29 ` [PATCH v3 0/6] arm64: dts: qcom: sm8350: enable GPU on the HDK board Neil Armstrong
@ 2023-02-10 10:32 ` Dmitry Baryshkov
2023-02-10 11:06 ` neil.armstrong
0 siblings, 1 reply; 17+ messages in thread
From: Dmitry Baryshkov @ 2023-02-10 10:32 UTC (permalink / raw)
To: neil.armstrong
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul,
Abhinav Kumar, Rob Herring, Krzysztof Kozlowski, Stephen Boyd,
David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel,
freedreno
On Fri, 10 Feb 2023 at 10:29, Neil Armstrong <neil.armstrong@linaro.org> wrote:
>
> On 09/02/2023 14:38, Dmitry Baryshkov wrote:
> > Add A660 device to the Qualcomm SM8350 platform and enable it for the
> > sm8350-hdk board. Unfortunately while adding the GPU & related devices I
> > noticed that DT nodes on SM8350 are greatly out of the adress sorting
> > order, so patches 2-4 reorder DT nodes to follow the agreement.
> >
> > Changes since v1:
> > - Dropped merged patches
> > - Expanded commit messages to mention the sort order (by the node
> > address)
> > - Rebased on top of latest Bjorn's tree
>
> Can you specify which tree and commit ?
>
> I tried next-20230207, next-20230208 & next-20230209 and patch 2 doesn't apply.
It was crafted on top of Bjorn's tree and as such it applies on top of
20230210 without any issues.
>
> On the 3 trees I have:
> d7133d6d25fb arm64: dts: qcom: sm8350: use qcom,sm8350-dsi-ctrl compatibles
> b904227a4b69 arm64: dts: qcom: sm8350: Hook up DSI1 to MDP
> 2a07efb8c086 arm64: dts: qcom: sm8350: Add mdss_ prefix to DSIn out labels
> e3e654ced376 arm64: dts: qcom: sm8350: Fix DSI PLL size
> 45cd807de143 arm64: dts: qcom: sm8350: Fix DSI PHY compatibles
> 0af6a4012b38 arm64: dts: qcom: sm8350: Feed DSI1 PHY clocks to DISPCC
> 1eed7995d9da arm64: dts: qcom: sm8350: Fix DSI1 interrupt
> 6636818ecf0f arm64: dts: qcom: sm8350: Add missing #address/size-cells to DSIn
> f3c08ae6fea7 arm64: dts: qcom: sm8350: Pad addresses to 8 hex digits
> 1ccad21aa996 Merge tag 'qcom-arm64-fixes-for-6.2' into arm64-for-6.3
> ...
>
> Can you use --base in format-patch (or use b4 prep !) ?
>
> Thanks,
> Neil
>
> >
> > Changes since v1:
> > - Fixed the subject and commit message for patch 1
> > - Fixed GMU's clocks to follow the vendor kernel
> > - Marked Adreno SMMU as dma-coherent
> > - Dropped comments targeting sm8350 v1, we do not support that chip
> > revision.
> >
> > Dmitry Baryshkov (6):
> > dt-bindings: display/msm/gmu: add Adreno 660 support
> > arm64: dts: qcom: sm8350: reorder device nodes
> > arm64: dts: qcom: sm8350: move more nodes to correct place
> > arm64: dts: qcom: sm8350: finish reordering nodes
> > arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes
> > arm64: dts: qcom: sm8350-hdk: enable GPU
> >
> > .../devicetree/bindings/display/msm/gmu.yaml | 1 +
> > arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 8 +
> > arch/arm64/boot/dts/qcom/sm8350.dtsi | 2512 +++++++++--------
> > 3 files changed, 1354 insertions(+), 1167 deletions(-)
> >
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 0/6] arm64: dts: qcom: sm8350: enable GPU on the HDK board
2023-02-10 10:32 ` Dmitry Baryshkov
@ 2023-02-10 11:06 ` neil.armstrong
0 siblings, 0 replies; 17+ messages in thread
From: neil.armstrong @ 2023-02-10 11:06 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul,
Abhinav Kumar, Rob Herring, Krzysztof Kozlowski, Stephen Boyd,
David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel,
freedreno
On 10/02/2023 11:32, Dmitry Baryshkov wrote:
> On Fri, 10 Feb 2023 at 10:29, Neil Armstrong <neil.armstrong@linaro.org> wrote:
>>
>> On 09/02/2023 14:38, Dmitry Baryshkov wrote:
>>> Add A660 device to the Qualcomm SM8350 platform and enable it for the
>>> sm8350-hdk board. Unfortunately while adding the GPU & related devices I
>>> noticed that DT nodes on SM8350 are greatly out of the adress sorting
>>> order, so patches 2-4 reorder DT nodes to follow the agreement.
>>>
>>> Changes since v1:
>>> - Dropped merged patches
>>> - Expanded commit messages to mention the sort order (by the node
>>> address)
>>> - Rebased on top of latest Bjorn's tree
>>
>> Can you specify which tree and commit ?
>>
>> I tried next-20230207, next-20230208 & next-20230209 and patch 2 doesn't apply.
>
> It was crafted on top of Bjorn's tree and as such it applies on top of
> 20230210 without any issues.
Ack, will rebase my DP stuff on that,
Thanks,
Neil
>
>>
>> On the 3 trees I have:
>> d7133d6d25fb arm64: dts: qcom: sm8350: use qcom,sm8350-dsi-ctrl compatibles
>> b904227a4b69 arm64: dts: qcom: sm8350: Hook up DSI1 to MDP
>> 2a07efb8c086 arm64: dts: qcom: sm8350: Add mdss_ prefix to DSIn out labels
>> e3e654ced376 arm64: dts: qcom: sm8350: Fix DSI PLL size
>> 45cd807de143 arm64: dts: qcom: sm8350: Fix DSI PHY compatibles
>> 0af6a4012b38 arm64: dts: qcom: sm8350: Feed DSI1 PHY clocks to DISPCC
>> 1eed7995d9da arm64: dts: qcom: sm8350: Fix DSI1 interrupt
>> 6636818ecf0f arm64: dts: qcom: sm8350: Add missing #address/size-cells to DSIn
>> f3c08ae6fea7 arm64: dts: qcom: sm8350: Pad addresses to 8 hex digits
>> 1ccad21aa996 Merge tag 'qcom-arm64-fixes-for-6.2' into arm64-for-6.3
>> ...
>>
>> Can you use --base in format-patch (or use b4 prep !) ?
>>
>> Thanks,
>> Neil
>>
>>>
>>> Changes since v1:
>>> - Fixed the subject and commit message for patch 1
>>> - Fixed GMU's clocks to follow the vendor kernel
>>> - Marked Adreno SMMU as dma-coherent
>>> - Dropped comments targeting sm8350 v1, we do not support that chip
>>> revision.
>>>
>>> Dmitry Baryshkov (6):
>>> dt-bindings: display/msm/gmu: add Adreno 660 support
>>> arm64: dts: qcom: sm8350: reorder device nodes
>>> arm64: dts: qcom: sm8350: move more nodes to correct place
>>> arm64: dts: qcom: sm8350: finish reordering nodes
>>> arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes
>>> arm64: dts: qcom: sm8350-hdk: enable GPU
>>>
>>> .../devicetree/bindings/display/msm/gmu.yaml | 1 +
>>> arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 8 +
>>> arch/arm64/boot/dts/qcom/sm8350.dtsi | 2512 +++++++++--------
>>> 3 files changed, 1354 insertions(+), 1167 deletions(-)
>>>
>>
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 0/6] arm64: dts: qcom: sm8350: enable GPU on the HDK board
2023-02-09 13:38 [PATCH v3 0/6] arm64: dts: qcom: sm8350: enable GPU on the HDK board Dmitry Baryshkov
` (6 preceding siblings ...)
2023-02-10 8:29 ` [PATCH v3 0/6] arm64: dts: qcom: sm8350: enable GPU on the HDK board Neil Armstrong
@ 2023-02-13 22:23 ` Bjorn Andersson
7 siblings, 0 replies; 17+ messages in thread
From: Bjorn Andersson @ 2023-02-13 22:23 UTC (permalink / raw)
To: Andy Gross, Sean Paul, Rob Herring, Krzysztof Kozlowski,
Abhinav Kumar, Rob Clark, Konrad Dybcio, Dmitry Baryshkov
Cc: Daniel Vetter, dri-devel, David Airlie, freedreno, Stephen Boyd,
linux-arm-msm, devicetree
On Thu, 9 Feb 2023 15:38:33 +0200, Dmitry Baryshkov wrote:
> Add A660 device to the Qualcomm SM8350 platform and enable it for the
> sm8350-hdk board. Unfortunately while adding the GPU & related devices I
> noticed that DT nodes on SM8350 are greatly out of the adress sorting
> order, so patches 2-4 reorder DT nodes to follow the agreement.
>
> Changes since v1:
> - Dropped merged patches
> - Expanded commit messages to mention the sort order (by the node
> address)
> - Rebased on top of latest Bjorn's tree
>
> [...]
Applied, thanks!
[1/6] dt-bindings: display/msm/gmu: add Adreno 660 support
(no commit info)
[2/6] arm64: dts: qcom: sm8350: reorder device nodes
commit: f5f6bd58186afa4ec1ebcd074bc30255826e8480
[3/6] arm64: dts: qcom: sm8350: move more nodes to correct place
commit: 1417372f4f846fbc28b4306370eb011d1f0853ca
[4/6] arm64: dts: qcom: sm8350: finish reordering nodes
commit: 51f83fbbf1c8d7a09885099f9a8f25b3c9139797
[5/6] arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes
commit: 54af0ceb75958a8b7e62138646cfa6c114e71a77
[6/6] arm64: dts: qcom: sm8350-hdk: enable GPU
commit: a8ecd17bb681d1743309b0d2a4622b643b61d69c
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 17+ messages in thread