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Thu, 31 Oct 2024 08:15:01 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20241019-qcs615-mm-clockcontroller-v1-0-4cfb96d779ae@quicinc.com> <20241019-qcs615-mm-clockcontroller-v1-8-4cfb96d779ae@quicinc.com> <2aa768a4-b0e9-4b2f-8d74-736a88cf81cd@quicinc.com> In-Reply-To: <2aa768a4-b0e9-4b2f-8d74-736a88cf81cd@quicinc.com> From: Dmitry Baryshkov Date: Thu, 31 Oct 2024 17:14:57 +0200 Message-ID: Subject: Re: [PATCH 08/11] clk: qcom: gpucc-qcs615: Add QCS615 graphics clock controller driver To: Taniya Das Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Abhishek Sahu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Ajit Pandey , Imran Shaik , Jagadeesh Kona , Stephen Boyd , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="UTF-8" On Wed, 30 Oct 2024 at 20:04, Taniya Das wrote: > > > > On 10/19/2024 1:58 AM, Dmitry Baryshkov wrote: > >> +static struct gdsc gx_gdsc = { > >> + .gdscr = 0x100c, > >> + .en_rest_wait_val = 0x2, > >> + .en_few_wait_val = 0x2, > >> + .clk_dis_wait_val = 0x2, > >> + .pd = { > >> + .name = "gx_gdsc", > > .power_on = gdsc_gx_do_nothing_enable ? Or is it controlled directly on > > this platform? > > > > On QCS615 the GPU clocks are directly controlled by high level OS. Is it one of the gmu-wrapper platforms? > > >> + }, > >> + .pwrsts = PWRSTS_OFF_ON, > >> + .flags = POLL_CFG_GDSCR, > >> +}; > >> + > > -- > Thanks & Regards, > Taniya Das. -- With best wishes Dmitry