From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAE33C433EF for ; Thu, 26 May 2022 20:29:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231663AbiEZU32 (ORCPT ); Thu, 26 May 2022 16:29:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36484 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229822AbiEZU30 (ORCPT ); Thu, 26 May 2022 16:29:26 -0400 Received: from mail-qv1-xf31.google.com (mail-qv1-xf31.google.com [IPv6:2607:f8b0:4864:20::f31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9033CAEE25 for ; Thu, 26 May 2022 13:29:25 -0700 (PDT) Received: by mail-qv1-xf31.google.com with SMTP id j14so1930422qvo.3 for ; Thu, 26 May 2022 13:29:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=w7U8ZxQJcCt/aMdBrHfCcBBglr9/HQ3epyWgRB+XBNQ=; b=C1pwrXuf/a3Rus/0i1yLLGIWkl+ZKCRp1bMczp3YWWS5G0T10MNpbweX0RL4iJoFv1 fkvxJ/fUR/6MVoP2R7jpkm/XVkTOjRCwbMNe15mzo4Pr7wCFrRYnz6ShhMq516/aFqjF YRZPXkVU8XE3II8CtsKYgiJ7H1gE203ju79VVaA+RIh4D6V2am+2apFH4QBorL72H9KY 6VEdOH15xkaG5Jps0xyfm8i0+rvlVVeLIbtI+YjooI9LaoNXVDYN/1SizRKytW5tQbX/ yB0hG7NFnqxiAyDr1+stokkDWBnsn4JHP7Vnh3AIoU345gwtJtKZ3FpD0eD8ihpkDYY7 nkAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=w7U8ZxQJcCt/aMdBrHfCcBBglr9/HQ3epyWgRB+XBNQ=; b=3Rnh1oXN7QG/pdIug5NNnQj1bm/YKXtx2+z39qCbOziTOwPkzD6ZbFCsupJuisZaNf QQya4GUsQ1s/5z8N8Q0xCITEOCAE+Y3Qk4ZGl8J69J+oeOrg5uITR51SR29EYD6CdtUZ XiZRV8lNgiivVt6CppWKpEWSICeAt+3gxUZxMn73DnQtrd3MBBgcXxCq2hkDGRF00jdB L3YUqMDSOM3fOHDM2UnL4Sk2lLbE3O9HSh11KgpZgWf5acxseBwMoMpu/WKBLEav9O/q 3MWCiEVM12XHSGJCLVYr59jV9jfWDv9AZq/uFie7zWJq8HL+ivWqdHGqKbGJVdO8SAsp tQ1Q== X-Gm-Message-State: AOAM531RIstGUgoy+4OEc1Gm6kHeTMRD5yPEczsOTN7VmlXcHs1yWKEo SYNgZg7+FuKIBHRrEHqrKK+kqdMizpFvabIeQqKaGw== X-Google-Smtp-Source: ABdhPJzWE6+/aFfASD6rZIFfbyF9nJaVk/sa/ZUHMyOQjnKRJ3h7r8yBH5vrbLsawyP3ZThVvAXaqR5lwwPSQ7yJ3X4= X-Received: by 2002:a05:6214:931:b0:461:d289:b7f6 with SMTP id dk17-20020a056214093100b00461d289b7f6mr32636342qvb.55.1653596964734; Thu, 26 May 2022 13:29:24 -0700 (PDT) MIME-Version: 1.0 References: <20220523181836.2019180-1-dmitry.baryshkov@linaro.org> <20220523181836.2019180-7-dmitry.baryshkov@linaro.org> <20220526184228.GF54904-robh@kernel.org> In-Reply-To: <20220526184228.GF54904-robh@kernel.org> From: Dmitry Baryshkov Date: Thu, 26 May 2022 23:29:13 +0300 Message-ID: Subject: Re: [PATCH v12 6/8] PCI: dwc: Implement special ISR handler for split MSI IRQ setup To: Rob Herring Cc: Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, 26 May 2022 at 21:42, Rob Herring wrote: > > On Mon, May 23, 2022 at 09:18:34PM +0300, Dmitry Baryshkov wrote: > > If the PCIe DWC controller uses split MSI IRQs for reporting MSI > > vectors, it is possible to detect, which group triggered the interrupt. > > Provide an optimized version of MSI ISR handler that will handle just a > > single MSI group instead of handling all of them. > > A lot more complexity to save 7 register reads... Thus it is a separate patch. It can be dropped w/o any issues. > > > > > Signed-off-by: Dmitry Baryshkov > > --- > > .../pci/controller/dwc/pcie-designware-host.c | 86 ++++++++++++++----- > > 1 file changed, 65 insertions(+), 21 deletions(-) > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > > index 98a57249ecaf..2b2de517301a 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > > @@ -52,34 +52,42 @@ static struct msi_domain_info dw_pcie_msi_domain_info = { > > .chip = &dw_pcie_msi_irq_chip, > > }; > > > > +static inline irqreturn_t dw_handle_single_msi_group(struct pcie_port *pp, int i) > > +{ > > + int pos; > > + unsigned long val; > > + u32 status; > > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > + > > + status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + > > + (i * MSI_REG_CTRL_BLOCK_SIZE)); > > + if (!status) > > + return IRQ_NONE; > > + > > + val = status; > > + pos = 0; > > + while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, > > + pos)) != MAX_MSI_IRQS_PER_CTRL) { > > for_each_set_bit() doesn't work here? Good question, I just moved the existing DWC code. > > > + generic_handle_domain_irq(pp->irq_domain, > > + (i * MAX_MSI_IRQS_PER_CTRL) + > > + pos); > > + pos++; > > + } > > + > > + return IRQ_HANDLED; > > +} > > + > > /* MSI int handler */ > > irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) > > { > > - int i, pos; > > - unsigned long val; > > - u32 status, num_ctrls; > > + int i; > > + u32 num_ctrls; > > irqreturn_t ret = IRQ_NONE; > > - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > > > num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; > > > > - for (i = 0; i < num_ctrls; i++) { > > - status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + > > - (i * MSI_REG_CTRL_BLOCK_SIZE)); > > - if (!status) > > - continue; > > - > > - ret = IRQ_HANDLED; > > - val = status; > > - pos = 0; > > - while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, > > - pos)) != MAX_MSI_IRQS_PER_CTRL) { > > - generic_handle_domain_irq(pp->irq_domain, > > - (i * MAX_MSI_IRQS_PER_CTRL) + > > - pos); > > - pos++; > > - } > > - } > > + for (i = 0; i < num_ctrls; i++) > > + ret |= dw_handle_single_msi_group(pp, i); > > > > return ret; > > } -- With best wishes Dmitry